LSI L64005 User manual

Final Edition May 1998
L64005
Enhanced MPEG-2
Audio/Video Decoder
Technical Manual

ii
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
This document contains proprietary information of LSI Corporation. The informa-
tion contained herein is not to be used by or disclosed to third parties without the
express written permission of an officer of LSI Corporation.
Document DB14-000045-00, Final Revision F (May, 1998)
This document describes revisions D through F of LSI Logic Corporation’s
L64005 MPEG-2 Audio/Video Decoder and will remain the official reference
source for all revisions/releases of this product until rescinded by an update.
To receive product literature, call us at 1.800.574.4286 (U.S. and Canada);
+32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, and Europe)
and ask for Department JDS; or visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or lia-
bility arising out of the application or use of any product described herein, except
as expressly agreed to in writing by LSI Logic; nor does the purchase or use of
a product from LSI Logic convey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual property rights of LSI Logic or
third parties.
In particular, supply of the LSI Logic IC L64005 does not convey a license or
imply a right under certain patents and/or other industrial or intellectual property
rights claimed by IRT, CCETT and Philips, to use this IC in any ready-to-use elec-
tronic product. The purchaser is herby notified that Philips, CCETT and IRT are
of the opinion that a generally available patent license for such use is required
from them. No warranty or indemnity of any sort is provided by LSI Logic regard-
ing patent infringement.
Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI Logic logo design is a registered trademark of LSI Logic Corporation. All
other brand and product names may be trademarks of their respective compa-
nies.

L64005 MPEG-2 Audio/Video Decoder Technical Manual iii
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and technical manual for the L64005
MPEG-2 Audio/Video Decoder. It contains a complete functional descrip-
tion and includes complete physical and electrical specifications for the
L64005.
Audience This document assumes that you have some familiarity with microproces-
sors and related support devices. The people who benefit from this book
are:
♦Engineers and managers who are evaluating the processor for pos-
sible use in a system
♦Engineers who are designing the processor into a system
Organization This document has the following chapters:
♦Chapter 1 Introduction, describes the system interface and the
architecture of the L64005 MPEG-2 Audio/Video Decoder.
♦Chapter 2 Registers, discusses the L64005 internal registers. It also
provides a description of the internal memory mapping and how the
registers are accessed from the system interface. This chapter is
intended primarily for system programmers who are developing soft-
ware drivers.
♦Chapter 3 Signals, provides detailed information on the L64005 sig-
nals. The signal descriptions are useful for hardware designers who
are interfacing the L64005 with other devices.
♦Chapter 4 Video Data Flow, This chapter describes the MPEG bit-
stream construction, parsing and error handling as well as the oper-
ation of the channel buffer.

iv Preface
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
♦Chapter 5 External Memory Interface, describes the frame mem-
ory interface.
♦Chapter 6 Video Interface and On-Screen Display, describes the
L64005 video interface and video timing characteristics.
♦Chapter 7 Audio Decoder, describes the details of the integrated
two channel Musicam (MPEG) audio decoder.
♦Chapter 8 System Stream Decoding and Synchronization,
describes the resources that the L64005 provides for parsing an
MPEG system stream.
♦Chapter 9 Specifications, specifies the L64005 electrical and
mechanical characteristics.
♦Appendix A Interfacing the L64005 to 5-V Signals, describes how
to interface LSI Logic’s 3.3-V L64005 MPEG-2 Audio/Video Decoder
to 5-V signals.
♦Customer Feedback.
Related
Publications ISO/IEC 13818,
Generic Coding of Moving Pictures and Associated
Audio (MPEG-2), Draft International Standard . ISO/IEC Copyright Office,
Case Postal 56, CH1211 Genève 20, Switzerland.
ISO/IEC 11172 (1993), Information Technology—Coding of Moving Pic-
ture and Associated Audio for Digital Storage Media at up to about
1.5 Mbit/s (MPEG-1).
L64002 MPEG-2 Audio/Video Decoder Technical Manual , LSI Logic
Corp.
L64007 MPEG-2 Transport Demultiplexer , LSI Logic Corp.
Conventions
Used in This
Manual
Unless otherwise specified, MPEG refers to the MPEG-2 standard.
MSB indicates the most-significant bit or byte. LSB indicates the least-
significant bit or byte.The first time a word or phrase is defined in this
manual, it is italicized.
The following signal naming conventions are used throughout this
manual:

L64005 MPEG-2 Audio/Video Decoder Technical Manual v
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
♦A level-significant signal that is true or valid when the signal is LOW
always has an overbar ( ) over its name.
♦An edge-significant signal that initiates actions on a HIGH-to-LOW
transition always has an overbar ( ) over its name.
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x” before the num-
ber—for example, 0x32CF. Binary numbers are indicated by a sub-
scripted “2” following the number—for example, 0011.0010.1100.11112.
Revision
History This section lists the changes in this document from initial release to the current version.
Notice for
L64002 Users This section is for customers using the L64002, and who want to upgrade to the L64005. The following is a brief description of the pertinent
changes, with emphasis on pinout and necessary software changes.
Please note: LSI Logic recommends building new boards to
ensure L64005 to L64002 compatibility. A simple 0 Ω resis-
tor jumper (for pin 69) allows switching between the loop fil-
ter and the CAS signal.
Pinout Changes If the L64005 is used with fast page mode DRAM, then a few changes
are needed. For further information, please refer to Chapter 9: Specifica-
tions.
Version Release Date Comments
L64005.ADV.0 March 4, 1996 Initial release
L64005.ADV.1 August 23, 1996 Major modifications to most chapters.
Changed register map, pinout, and
signal descriptions. Added Section
6.3, “Reduced Memory Mode,” Section
3.6, “PLL Interface,” and Section 5.5,
“Channel Buffer Architecture”.
L64005.Final May 11, 1998 Minor changes to most chapters.
Added corrections from document
review and relevant items from
L64005 Rev. E and F ECNs.

vi Preface
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
♦Pin 64 is CAS for the L64005, not BA9 (BA9 has been removed).
♦For Rev. E and F devices Pin 69 is now not connected (NC) and no
external loop filter is required. The filter may be left in place on any
board that already has it designed in.
For the L64005 Rev. D, Pin 69 is LP2. Regardless of the DRAM
mode used, an external loop filter must be included in the design
(requires one resistor and two capacitors for an off-chip loop filter).
♦The DRAM interface now supports both regular and synchronous
DRAM modes. See Section 5.3.2, “Synchronous DRAM Mode,” for
more information on the SDRAM interface.
♦New AC timing specifications and drawings have been added to Sec-
tion 9.1
♦Pin 68 is Analog VDD (AVDD), and pin 70 is Analog GND (AGND).
These pins must be isolated from other VDD and VSS pins.
♦Please note that the L64005 has an on-chip PLL, so the 27-MHz
input clock must have low jitter (<300ps).
♦The duty cycle for SYSCLK has been specified slightly differently.
Please refer to Chapter 9, Specifications, for details.
Software
Changes A few changes must be made to L64005 supporting software.
♦Bit 0in Group 7, Register 27 must be set for reduced memory mode
(1=RMM, 0=Normal).
♦If reduced memory mode is used, Group 7, Register 27, Bits [7:2]
must be set to determine the number of 8-line segments used for a
B-frame decode.
♦Bits [4:3] of Group 7, Register 1 are no longer used for PMCT (1CAS
enable) or 512-page size select. In the L64005, bits [4:3] are used
to select the DRAM mode. Refer to Chapter 2 for more details.
♦In the L64005 32-bit mode is not supported. Bit 5 of Group 7, Reg-
ister 1 is now reserved.
♦Bit 6 of Group 7, Register 26 controls line doubling for the interlaced
display mode.
♦In the L64005, bits [7:0] in Group 7, Register 28 contains the hori-
zontal word origin of the luma and the chroma.

L64005 MPEG-2 Audio/Video Decoder Technical Manual vii
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
♦Additional field status bits have been added to the register map. Odd
Field First and Last Active Field have been added to Group 6, Reg-
ister 31, Bits [3:2]. Refer to Section 2.8.18, “Group 6 Display Mode
1” for more details.

viii Preface
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.

L64005 MPEG-2 Audio/Video Decoder Technical Manual ix
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
Contents
Chapter 1 Introduction
1.1 Video Compression and Decompression Concepts 1-1
1.1.1 Video Encoding 1-2
1.1.2 Bitstream Syntax 1-5
1.1.3 Video Decoding 1-7
1.2 Audio Compression and Decompression Concepts 1-8
1.2.1 MPEG Audio Encoding 1-8
1.2.2 Audio Decoding 1-11
1.3 Standards Compliance 1-11
1.3.1 MPEG-1 1-12
1.3.2 MPEG-2 1-12
1.4 Terms and Concepts 1-12
1.5 System Overview 1-17
1.5.1 Video Decoding 1-17
1.5.2 Audio Decoding 1-17
1.5.3 Post Processing 1-18
1.5.4 On-Screen Display 1-18
1.5.5 PES Decoding 1-18
1.5.6 Video Output 1-19
1.5.7 Audio Output 1-19
1.5.8 User Interface 1-19
1.5.9 Memory Utilization 1-19
1.5.10 Error Concealment 1-20
1.5.11 Mechanical and Electrical 1-20
1.6 L64005 Overview 1-20
1.6.1 MPEG-2 Video Decoder 1-20
1.6.2 System Layer Decoding 1-21
1.6.3 Video Output Features 1-21
1.6.4 On-Screen Display 1-24
1.6.5 Audio Decoder 1-24

x Contents
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
1.6.6 System Controller Interface 1-25
1.6.7 Channel Interface 1-27
1.6.8 Bitstream Syntax and Grammar 1-27
1.7 Features 1-28
Chapter 2 Registers
2.1 L64005 Register Overview 2-1
2.1.1 Writing a Single Register 2-14
2.1.2 Reading or Writing Multiple Registers
in a Group 2-15
2.2 Group 0 Address Indirection Register 2-15
2.3 Group 1 Status 0 Register 2-16
2.4 Group 2 Status 1 Register 2-18
2.5 Group 3 Interrupt Register 0 2-19
2.6 Group 4 Interrupt Register 1 2-21
2.7 Group 5 Control Register 2-22
2.8 Group 6 Secondary Control Registers 2-23
2.8.1 Group 6 User Data FIFO 2-23
2.8.2 Group 6 Error Status Register 2-24
2.8.3 Group 6 Forward Anchor Luma
Base Address 2-25
2.8.4 Group 6 Forward Anchor Chroma
Base Address 2-26
2.8.5 Group 6 Backward Anchor Luma
Base Address 2-26
2.8.6 Group 6 Backward Anchor Chroma
Base Address 2-27
2.8.7 Group 6 Display Luma Base Address 2-27
2.8.8 Group 6 Display Chroma Base Address 2-27
2.8.9 Group 6 VBI1 Luma Base Address 2-28
2.8.10 Group 6 VBI1 Chroma Base Address 2-28
2.8.11 Group 6 VBI2 Luma Base Address 2-29
2.8.12 Group 6 VBI2 Chroma Base Address 2-29
2.8.13 Group 6 VBI Size 2-30
2.8.14 Group 6 OSD Control Register 2-30
2.8.15 Group 6 OSD Field 1 Pointer 2-31
2.8.16 Group 6 OSD Field 2 Pointer 2-32
2.8.17 Group 6 Display Mode 0 2-32

L64005 MPEG-2 Audio/Video Decoder Technical Manual xi
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
2.8.18 Group 6 Display Mode 1 2-33
2.8.19 Group 6 Raster Mapper Increment 2-34
2.8.20 Group 6 Display Controller Status 2-35
2.8.21 Group 6 Video PES Buffer Start Address 2-36
2.8.22 Group 6 Video PES Buffer End Address 2-37
2.8.23 Group 6 Audio PES Buffer Start Address 2-37
2.8.24 Group 6 Audio PES Buffer End Address 2-38
2.8.25 Group 6 Video Channel Buffer Start Address 2-38
2.8.26 Group 6 Video Channel Buffer End Address 2-39
2.8.27 Group 6 Audio Channel Buffer Start Address 2-39
2.8.28 Group 6 Audio Channel Buffer End Address 2-40
2.8.29 Group 6 Audio Mode Control 2-40
2.8.30 Group 6 Audio Oscillator Frequency Control 2-41
2.8.31 Group 6 Audio Parameter 0 2-42
2.8.32 Group 6 Audio Parameter 1 2-44
2.8.33 Group 6 Audio Trick Modes 2-45
2.8.34 Group 6 Reserved Registers 2-47
2.9 Group 7 Secondary Control Registers 2-47
2.9.1 Group 7 Auxiliary Data FIFO 2-47
2.9.2 Group 7 DRAM Control 2-51
2.9.3 Group 7 DRAM Address 2-52
2.9.4 Group 7 DRAM Data 2-53
2.9.5 Group 7 Horizontal Sync Width 2-54
2.9.6 Group 7 Equalization Pulse Width 2-54
2.9.7 Group 7 Serration Pulse Width 2-54
2.9.8 Group 7 Horizontal Blank Pulse Width 2-55
2.9.9 Group 7 Active Image Done 2-55
2.9.10 Group 7 Half Line Time 2-55
2.9.11 Group 7 Upper Bits 2-55
2.9.12 Group 7 Pre-Blank/Equalization 2-56
2.9.13 Group 7 Post-Blank/Equalization 2-56
2.9.14 Group 7 Main/Serration Lines 2-57
2.9.15 Group 7 Scan Half Lines 2-57
2.9.16 Group 7 Main Reads Per Line 2-57
2.9.17 Group 7 Display Width 2-58
2.9.18 Group 7 Pan and Scan Control 2-58
2.9.19 Group 7 Reduced Memory Mode Control 2-59
2.9.20 Group 7 Reserved Registers 2-60

xii Contents
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
2.9.21 Group 7 Video Output Mode Control 2-60
2.9.22 Group 7 Channel Buffer Read Address 2-61
2.9.23 Group 7 Picture Start Code Read Address 2-62
2.9.24 Group 7 Audio Sync Code Read Address 2-62
2.9.25 Group 7 Reserved Registers 2-62
2.9.26 Group 7 DRAM Source Address Registers 2-63
2.9.27 Group 7 DRAM Transfer Count Registers 2-63
2.9.28 Group 7 DRAM Transfer Mode Register 2-63
2.9.29 Group 7 Revision ID Register 2-64
2.9.30 Group 7 Video Trick Modes 2-64
2.9.31 Group 7 System Clock Reference (SCR) Value 2-66
2.9.32 Group 7 SCR Compare Value 2-66
2.9.33 Group 7 Reserved Registers 2-66
Chapter 3 Signals
3.1 User Interface 3-2
3.2 Channel Interface 3-4
3.2.1 Parallel Channel Writes 3-6
3.2.2 Serial Channel Writes 3-6
3.3 Memory Interface 3-7
3.3.1 Regular DRAM Signals 3-7
3.3.2 Synchronous DRAM Signals 3-8
3.4 Video Interface 3-9
3.5 Audio Interface 3-10
3.6 PLL Interface 3-11
Chapter 4 Video Data Flow
4.1 Overview 4-1
4.2 Channel Data Parsers 4-1
4.2.1 Pre-Parser Operation 4-3
4.2.2 Post-Parser Operation 4-6
4.3 Channel Buffer Operation 4-10
4.3.1 Channel Buffer Hardware 4-10
4.3.2 User Data Buffer 4-11
4.3.3 Auxiliary Data Buffer 4-12
4.4 Elementary Stream Decoding 4-13

L64005 MPEG-2 Audio/Video Decoder Technical Manual xiii
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
Chapter 5 External Memory Interface
5.1 Overview 5-1
5.2 Memory Architecture 5-1
5.3 Memory Interface 5-2
5.3.1 Regular DRAM Mode 5-2
5.3.2 Synchronous DRAM Mode 5-3
5.3.3 DRAM Transfer Modes 5-4
5.3.4 Read/Write 5-12
5.3.5 Refresh Cycles 5-16
5.4 Memory Map 5-17
5.4.1 Luma Frame Organization 5-19
5.4.2 Chroma Frame Organization 5-19
5.4.3 Random Read/Write to Frame Store 5-19
5.5 Channel Buffer Architecture 5-19
5.5.1 Video PES Buffer 5-21
5.5.2 Audio PES Buffer 5-22
5.5.3 Video Channel Buffer 5-22
5.5.4 Audio Channel Buffer 5-22
Chapter 6 Video Interface and On-Screen Display
6.1 Video Output Format 6-1
6.1.1 Post-Processing 480- and 576-Line Images 6-2
6.1.2 Post-Processing 240- and 288-Line Images 6-4
6.1.3 Selecting the Post-Processing Mode 6-5
6.2 Video Resolution 6-6
6.3 Reduced Memory Mode 6-7
6.4 Horizontal Post-Processing Filter 6-8
6.4.1 Filter Specification 6-8
6.4.2 Setting the Filter Raster Mapper Increment 6-10
6.4.3 Setting the Start Phase of the Filter 6-11
6.4.4 Filter Inhibit 6-11
6.4.5 Video Data and OSD 6-11
6.5 Display Control Parameters 6-11
6.5.1 Video Raster Timing (Master Mode 6-12
6.5.2 VCode Delay 6-17
6.5.3 Slave Mode 6-17

xiv Contents
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
6.5.4 Adaptive Modification of Video Raster
for Copy Protection 6-18
6.6 Pan and Scan Operation 6-18
6.7 Display Trick Modes 6-19
6.7.1 Trick Mode Decoding 6-19
6.8 3:2 Pull-Down 6-22
6.9 On-Screen Display 6-23
6.9.1 Color Palette 6-23
6.9.2 Operation of the OSD Controller 6-24
6.9.3 OSD Control Registers 6-25
6.9.4 Alpha Blending 6-31
6.9.5 High Color Operation 6-31
6.9.6 Bitmap Storage 6-31
6.9.7 Use of the OSDA Field 6-31
6.9.8 Alignment of the Bitmap 6-32
6.9.9 OSD Control 6-32
6.9.10 Limitations in the OSD Controller 6-32
6.9.11 OSD Compatibility Mode 6-33
6.9.12 Accessing the Overlay Bitmaps 6-34
6.10 Interrupts from the Display Controller 6-34
Chapter 7 Audio Decoder
7.1 Audio Decoder Overview 7-1
7.2 Decoder Programming 7-1
7.2.1 Reading the Audio Parameters 7-1
7.2.2 Starting, Stopping and Controlling the Rate
of the Decoder 7-2
7.2.3 Setting the DAC Interface Mode 7-3
7.2.4 Setting the Output Sample Rate 7-3
7.2.5 Determining the Presentation Time 7-6
7.2.6 Ancillary Channel Data 7-6
7.2.7 Error Detection 7-6
7.2.8 Output Control 7-8
Chapter 8 System Stream Decoding and Synchronization
8.1 System Parser Basics 8-1

L64005 MPEG-2 Audio/Video Decoder Technical Manual xv
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
8.1.1 Parsing a Program Stream 8-2
8.1.2 Parsing a Transport Stream 8-4
8.2 Reading the System Header Data 8-5
8.2.1 System Parser Control Bits 8-5
8.3 Synchronization Basics 8-7
8.4 L64005 Synchronization Resources 8-10
8.4.1 L64005 Video Skip and Repeat Frame 8-13
8.4.2 Video Decoding and Presentation Schedule 8-15
8.4.3 Audio Decoder Rate Control 8-16
8.5 Audio/Video Synchronization Technique 8-17
8.5.1 Clock Recovery 8-19
8.5.2 Creating Audio and Video PTS list 8-20
8.5.3 Picture Header Interrupt and AUX
FIFO Interrupt 8-23
8.5.4 Vertical Sync Interrupt 8-26
8.5.5 Audio Sync Interrupt 8-26
8.6 Real System Considerations 8-28
Chapter 9 Specifications
9.1 AC Timing 9-2
9.2 Electrical Requirements 9-14
9.3 Pin Summary 9-15
9.4 Packaging 9-18
Appendix A Interfacing the L64005 to 5-V Signals
A.2 JEDEC LVTTL Interface Standards A-1
A.3 L64005 5V-Compatible I/Os A-2
9.4.1 5V-Compatible Input Buffers A-3
9.4.3 Passive Resistor Loads and 5-V
Compatible Outputs A-5
9.4.5 Open Drain Outputs A-7
A.4 Mixed Voltage System Design Considerations A-8
A.5 Engineering Practice for Mixed Voltage Systems A-8
9.4.6 Precautions During Power Sequencing A-8
9.4.7 Precautions to Avoid Bus Contention A-9
9.4.8 Precautions During Power Failure A-9

xvi Contents
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
Appendix B Customer Feedback
List of Figures 1.1 MPEG Macroblock Structure 1-3
1.2 Typical Sequence of Frames in Display Order 1-6
1.3 Typical Sequence of Frames in Bitstream Order 1-6
1.4 Audio Encoding Process (Simplified) 1-9
1.5 ISO System Stream 1-9
1.6 MPEG Audio Packet Structure 1-10
1.7 System Block Diagram 1-18
2.1 Address Indirection Register 2-15
2.2 Status 0 Register 2-16
2.3 Status 1 Register 2-18
2.4 Group 3 Interrupt Register 0 2-20
2.5 Group 4 Interrupt Register 1 2-21
2.6 Group 5 Control Register 2-22
2.7 LAF and ODFF Bit Fields 2-36
2.8 DRAM Control Register 2-51
2.9 Active Image Done Register 2-55
2.10 Scan Half Lines Register 2-57
3.1 L64005 Logic Symbol 3-2
3.2 Parallel Channel Input Timing 3-6
3.3 Serial Channel Input Timing 3-7
3.4 Master Mode 3-10
3.5 External Loop Filter 3-12
4.1 Summary of the Bitstream Parsing Operations 4-2
4.2 Conceptual System Synchronization 4-3
4.3 Synchronization at the System Level 4-4
4.4 Successful and Unsuccessful Frame Skips 4-14
5.1 Regular DRAM Interface 5-3
5.2 Synchronous DRAM Interface 5-4
5.3 The Single Word Write Routine 5-6
5.4 Multiple Word Write Routine 5-7
5.5 Single Word Read Routine 5-8
5.6 Multiple Word Read Routine 5-9
5.7 Regular DRAM Read and Write Timing 5-12

L64005 MPEG-2 Audio/Video Decoder Technical Manual xvii
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
5.8 Synchronous DRAM Read and Write Timing 5-15
5.9 Regular DRAM Refresh Timing 5-16
5.10 Synchronous DRAM Refresh Timing 5-17
5.11 Memory Map of L64005 5-18
5.12 Channel Buffer Organization in L64005 5-21
6.1 Composite Sync and Composite Blank 6-2
6.2 Effect of Vertical Resolution and Blanking 6-6
6.3 Frequency and Phase Response A 6-9
6.4 Impulse Response A 6-9
6.5 Frequency and Phase Response B 6-9
6.6 Impulse Response B 6-10
6.7 Video Timing Chain Nomenclature 6-12
6.8 Horizontal Sync Timing 6-13
6.9 Display Parameters 6-14
6.10 Freeze Frame for One Frame Time 6-20
6.11 Freeze Frame for One Field Time 6-21
6.12 Pull-Down Field Order 6-22
6.13 Pointers to Overlay Display Lists 6-24
6.14 OSD File Organization 6-26
6.15 Region Attribute Bits 6-27
6.16 Color Fields 6-28
6.17 Color Attribute Bits 6-29
6.18 Color Extension Bits 6-29
8.1 MPEG-2 Transport Encoder 8-7
8.2 Audio and Video Sync train 8-8
8.3 Local Counter and Comparator Logic 8-11
8.4 Interrupt at each Vertical Sync 8-11
8.5 Audio and Video Decode Interrupts 8-12
8.6 System Header Interrupt 8-13
8.7 Video Skip 8-14
8.8 Video Repeat 8-14
8.9 Buffer Organization In L64005 Memory 8-21
8.10 PES Header Structure 8-22
8.11 List of Pending PUs for Video and Audio 8-23
8.12 PTS Association with Presentation Unit 8-24
8.13 Picture Type Routine 8-25
8.14 Audio PTS Association 8-27
8.15 Audio Sync Algorithm 8-28

xviii Contents
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
9.1 AC Test Load and Waveform for Standard Outputs 9-3
9.2 AC Test Load and Waveform for 3-State Outputs 9-3
9.3 DRAM Write Cycle 9-7
9.4 DRAM Read Cycle 9-8
9.5 Sync DRAM Write Cycle 9-9
9.6 Sync DRAM Read Cycle 9-10
9.7 Parallel Channel Write Timing 9-11
9.8 Host Write Timing 9-11
9.9 Host Read Timing 9-12
9.10 Serial Data Input 9-12
9.11 Reset 9-13
9.12 Video Timing 9-13
9.13 Serial PCM Data Out Timing 9-13
9.14 L64005 Pinout Diagram for Regular DRAM
160-Pin PQFP 9-21
9.15 L64005 Pinout Diagram for Synchronous
DRAM 160-Pin PQFP 9-22
9.16 160-Pin Copper Lead Frame PQFP
Mechanical Drawing 9-23
A.17 5V Interface Configurations A-3
A.18 5V-Compatible Output Buffer, Open Drain A-7
List of Tables 1.1 MPEG Compressed Bitstream Syntax 1-5
2.1 Register Groups and Function 2-2
2.2 L64005 Register Map 2-2
2.3 User Data FIFO 0 2-23
2.4 VLD Parameters 2-48
5.1 Mapping of Physical Address Bus to BA[8:0] 5-3
5.2 Mapping of Physical Address Bus to SBA[11:0] 5-4
5.3 Word Accesses vs. 81MHz Clock Cycles
in Regular DRAM Mode 5-13
5.4 Word Accesses Vs. 81MHz Clock Cycle
in SDRAM Mode 5-14
5.5 Channel Buffer Architecture 5-20
6.1 Post-processing modes 6-3
6.2 Chroma Line Repeat: Coefficients for Odd
and Even Fields 6-3

L64005 MPEG-2 Audio/Video Decoder Technical Manual xix
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
6.3 Luma Processing: Coefficients for Even
and Odd Fields 6-4
6.4 Chroma Processing: Coefficients for Even
and Odd Fields 6-5
6.5 Memory Mode Specifications 6-8
6.6 Raster Mapper Increment by Source Resolution 6-11
6.7 Horizontal Timing of NTSC TV Systems 6-15
6.8 Horizontal Timing of PAL TV Systems 6-16
6.9 Vertical Timing of Common TV Systems 6-17
6.10 Pull-Down Mode Bits 6-23
6.11 Conversion from 4:4:4 to 4:2:2 6-32
7.1 Typical Values for NCO at 27 MHz fd 7-5
7.2 Location of Maskable Interrupts 7-7
8.1 Levels of Hierarchy in MPEG-1 and MPEG-2
System Syntax 8-2
8.2 DRAM Map of an MPEG-2 Packet Header Structure
in the Elementary Stream with Write Pointer 8-6
8.3 Audio and Video DTSs and PTSs 8-10
8.4 Decode to Display Delay 8-15
8.5 Audio Input Clock is 256 fs 8-17
8.6 Audio Input Clock is 384 fs 8-17
9.1 AC Test Conditions 9-2
9.2 AC Timing Values 9-4
9.3 Absolute Maximum Ratings 9-14
9.4 Recommended Operating Conditions 9-14
9.5 Capacitance 9-14
9.6 DC Characteristics 9-15
9.7 Pin Description Summary 9-16
9.8 L64005 Ordering Information 9-18
9.9 Alphabetical Pin List by Signal Name
for Regular DRAM 160-Pin PQFP 9-19
9.10 Alphabetical Pin List by Signal Name
for Synchronous DRAM 160-Pin PQFP 9-20
A.11 DC Logic Levels A-2
A.12 DC Characteristics A-4
A.13 ibuf (3.3V Input), LVTTL AC Characteristics A-4
A.14 ibuff, LVTTL Input Buffer, Non-inverting,
5V-Compatible A-4

xx Contents
Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
A.15 DC Characteristics without Resistor Load A-6
A.16 3-State Output Buffer, 5 V-Compatible
AC Characteristics A-7