Lumistar LS-3x Series User manual
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Lumistar, Inc. and its logo are trademarks of Lumistar, Inc. All other brand names and product
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©2009 Lumistar, Inc. All rights reserved.
Lumistar,Inc.
5870 El Camino Real
Carlsbad, CA 92008
(760) 431-2181
(760) 431-2665 Fax
www.lumi-star.com
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TABLE OF CONTENTS
1 INTRODUCTION................................................................................................... 11
1.1 GENERAL ........................................................................................................... 11
1.2 LUMISTAR LS-3X-V (VERTICAL SIGNAL INTERFACE) ....................................... 12
1.3 LUMISTAR LS-3X-F (FACEPLATE SIGNAL INTERFACE)...................................... 13
1.4 LUMISTAR LS-3X-ITB (INTERFACE TRANSITION BOARD)................................. 14
1.5 LUMISTAR LS-3X-CTB (CHASSIS TRANSITION BOARD).................................... 15
1.6 MANUAL FORMAT AND CONVENTIONS.............................................................. 15
2 FIRMWARE AND SOFTWARE INSTALLATION.......................................... 19
2.1 STEP ONE – INSTALLING THE LRR SYSTEM SOFTWARE .................................... 19
2.2 STEP TWO – INSTALLING THE FIRMWARE LICENSE FILES .................................. 24
2.3 STEP THREE – INSTALLING THE DEVICE DRIVER FILE INTO MICROSOFT
WINDOWS ...................................................................................................................... 25
3 HARDWARE INSTALLATION........................................................................... 30
3.1 PRODUCT IMAGE................................................................................................ 30
3.2 HARDWARE CONFIGURATION ............................................................................ 30
3.3 INTERCONNECTION ............................................................................................ 30
4 LS-3X CONTROL SOFTWARE .......................................................................... 36
4.1 MAIN CONTROL COMMANDS............................................................................. 37
4.1.1 System Command...................................................................................... 37
4.1.1.1 Directory Sub-Tab ................................................................................ 37
4.1.1.2 Operations Sub-Tab.............................................................................. 38
4.1.1.2.1 Program Operation.......................................................................... 38
4.1.1.2.2 Program Startup.............................................................................. 38
4.1.1.2.3 Program Shutdown.......................................................................... 39
4.1.1.3 Utility Sub-Tab ..................................................................................... 39
4.1.1.4 Unique Card Settings Sub-Tab ............................................................. 40
4.1.1.4.1 FFT Controls................................................................................... 40
4.1.1.4.2 Bitsync Lock Status ........................................................................ 40
4.1.1.4.3 Receiver/Downconverter Swap ...................................................... 40
4.1.1.4.4 Receiver/Downconverter Logic...................................................... 40
4.1.1.4.5 Downconverter IF Factor................................................................ 40
4.1.1.5 Hardware Configuration ....................................................................... 40
4.1.1.6 Force FPGA Load Commands.............................................................. 41
4.1.2 Mission Command .................................................................................... 42
4.1.3 Setup Command........................................................................................ 42
4.1.4 Mode Command........................................................................................ 42
4.1.5 View, Tools, & About Commands............................................................. 43
4.2 THE LS-25 DOWNCONVERTER TAB (DCVTN)................................................... 44
4.2.1 Downconverter Status Display ................................................................. 44
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4.2.2 Downconverter Configuration Display..................................................... 45
4.2.3 Downconverter Setup Parameters (LS-25)............................................... 45
4.2.3.1 Tuner Frequency................................................................................... 45
4.2.3.2 IF Anti-Alias Bandwidth....................................................................... 46
4.2.3.3 Output Gain Controls............................................................................ 46
4.2.3.4 AM Controls ......................................................................................... 46
4.2.3.5 RSSI/AGC Controls.............................................................................. 47
4.2.3.5.1 AGC Time Constant ....................................................................... 47
4.2.3.5.2 Delta RSSI Mode & Set Delta RSSI Point ..................................... 47
4.2.3.5.3 Linear Out Enabled......................................................................... 47
4.2.3.5.4 Force Fresh RF Compression Reading........................................... 47
4.3 THE PSK RECEIVER TAB (RCRVN)................................................................... 48
4.3.1 PSK Receiver Status.................................................................................. 48
4.3.2 PSK Receiver Primary Sub-Tab................................................................ 49
4.3.2.1 PSK Receiver Parameters..................................................................... 50
4.3.2.1.1 Input Source.................................................................................... 50
4.3.2.1.2 Demodulation Mode ....................................................................... 50
4.3.2.1.3 Carrier Frequency ........................................................................... 50
4.3.2.1.4 Carrier Acquisition Mode............................................................... 50
4.3.2.1.5 Carrier Acquisition Range .............................................................. 51
4.3.2.1.6 Carrier Acquisition Loop Bandwidth.............................................. 51
4.3.2.1.7 Carrier Tracking Loop Bandwidth.................................................. 51
4.3.2.1.8 Carrier IF Filter Bandwidth ............................................................ 52
4.3.2.1.9 Carrier Threshold Level.................................................................. 52
4.3.2.1.10 Carrier Loop Discriminator........................................................... 52
4.3.2.1.11 Carrier PM Modulation Index....................................................... 52
4.3.2.1.12 Restart Acquisition Button............................................................ 53
4.3.2.2 Bit Sync Parameters.............................................................................. 53
4.3.2.2.1 Bit Rate ........................................................................................... 53
4.3.2.2.2 Bit Sync Acquisition Loop Bandwidth........................................... 54
4.3.2.2.3 Bit Sync Tracking Loop Bandwidth............................................... 54
4.3.2.2.4 PCM Input Code............................................................................. 54
4.3.2.2.5 PCM Output Code........................................................................... 54
4.3.2.3 Viterbi Parameters ................................................................................ 54
4.3.2.3.1 Decoder Enable Checkbox.............................................................. 55
4.3.2.3.2 Viterbi Rate Mode........................................................................... 55
4.3.2.3.3 Viterbi Symbol Order ..................................................................... 55
4.3.2.3.4 Invert G1/ G2.................................................................................. 56
4.3.3 PSK Receiver Secondary Sub-Tab............................................................ 56
4.3.3.1 Stream Control...................................................................................... 57
4.3.3.2 Recombine Location............................................................................. 57
4.3.3.3 Stream Swap Location.......................................................................... 58
4.3.3.4 Invert Location...................................................................................... 58
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4.3.3.5 Output Clock Polarity........................................................................... 59
4.3.3.6 Output Invert Enable............................................................................. 59
4.4 THE FM RECEIVER TAB (RCRVN).................................................................... 60
4.4.1 FM Receiver Status................................................................................... 61
4.4.2 FM Receiver Primary Sub-Tab................................................................. 61
4.4.2.1 FM Receiver Parameters....................................................................... 62
4.4.2.1.1 Input Source.................................................................................... 62
4.4.2.1.2 Deviation Detect Mode................................................................... 62
4.4.2.1.3 Carrier Frequency ........................................................................... 62
4.4.2.1.4 Manual Peak Deviation................................................................... 62
4.4.2.1.5 Carrier Acquisition Range .............................................................. 63
4.4.2.1.6 Carrier Acquisition Loop Bandwidth.............................................. 63
4.4.2.1.7 Carrier Tracking Loop Bandwidth.................................................. 63
4.4.2.1.8 Carrier IF Filter Bandwidth ............................................................ 63
4.4.2.1.9 Carrier Threshold Level.................................................................. 64
4.4.2.1.10 Restart Acquisition Button............................................................ 64
4.4.2.2 Bit Sync Parameters.............................................................................. 64
4.4.2.2.1 Bit Rate ........................................................................................... 65
4.4.2.2.2 Bit Sync Acquisition Loop Bandwidth........................................... 65
4.4.2.2.3 Bit Sync Tracking Loop Bandwidth............................................... 65
4.4.2.2.4 PCM Input Code............................................................................. 66
4.4.2.2.5 PCM Output Code........................................................................... 66
4.4.3 FM Receiver Secondary Sub-Tab ............................................................. 66
4.4.3.1 Output Clock Polarity........................................................................... 66
4.4.3.2 Output Invert Enable............................................................................. 66
4.5 THE BIT ERROR RATE TEST TAB (BERTN) ....................................................... 67
4.5.1 Bit Sync Status Display............................................................................. 67
4.5.2 Bit Sync Configuration Display................................................................ 67
4.6 THE MODULATOR TAB (MOD).......................................................................... 69
4.6.1 Modulator Primary Sub-Tab..................................................................... 70
4.6.1.1 Modulator Parameters........................................................................... 70
4.6.1.1.1 Input Source.................................................................................... 71
4.6.1.1.2 Carrier Frequency ........................................................................... 71
4.6.1.1.3 Carrier Amplitude........................................................................... 71
4.6.1.1.4 Modulation Mode............................................................................ 71
4.6.1.1.5 Modulation Type............................................................................. 71
4.6.1.1.6 I & Q Data Source........................................................................... 72
4.6.1.1.7 I & Q Data routing.......................................................................... 72
4.6.1.1.8 Carrier Enable Checkbox................................................................ 72
4.6.1.1.9 Modulation Enable Checkbox......................................................... 72
4.6.1.1.10 Noise Enable Checkbox................................................................ 72
4.6.1.1.11 C/N0Level .................................................................................... 73
4.6.1.1.12 FM Peak Deviation Factor............................................................ 74
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4.6.1.1.13 PSK PM Modulation Index........................................................... 74
4.6.1.1.14 Subcarrier Modulation Parameters ............................................... 74
4.6.1.1.14.1 Subcarrier Input Source ......................................................... 74
4.6.1.1.14.2 Subcarrier Modulation Mode................................................. 74
4.6.1.1.14.3 Subcarrier Rate....................................................................... 74
4.6.1.1.14.4 Subcarrier Modulation Index................................................. 75
4.6.1.2 PCM Encoder Parameters..................................................................... 75
4.6.1.2.1 Bit Rate ........................................................................................... 75
4.6.1.2.2 Data Source..................................................................................... 75
4.6.1.2.3 Output Code.................................................................................... 76
4.6.1.2.4 Test Data Type................................................................................ 76
4.6.2 Modulator Secondary Sub-Tab................................................................. 76
4.6.2.1 QPSK Conjugate................................................................................... 77
4.6.2.2 Maximum Output Calibration............................................................... 77
4.6.2.3 Symbol Routing.................................................................................... 77
4.6.2.4 Input Preprocessing............................................................................... 77
4.6.2.5 PCM Encoder Parameters..................................................................... 77
4.6.2.5.1 Convolutional Encoding On Checkbox.......................................... 77
4.6.2.5.2 Swap G1 & G2 Checkbox............................................................... 77
4.6.2.5.3 Invert G2 Checkbox........................................................................ 78
4.6.2.5.4 Invert Data Checkbox..................................................................... 78
4.6.2.5.5 Falling Clock Edge Checkbox ........................................................ 78
4.7 THE COMBINER TAB (COMB)........................................................................... 79
4.7.1 Pre-D Status Display ................................................................................ 81
4.7.2 Pre-D Configuration Display ................................................................... 81
4.7.2.1 Pre-D Combiner Parameters................................................................. 81
4.7.2.1.1 Noise Estimation Mode................................................................... 81
4.7.2.1.2 Pre-D Combiner Mode.................................................................... 82
4.7.2.1.3 Signal Bandwidth............................................................................ 82
4.7.2.1.4 Time Constant................................................................................. 82
4.7.2.1.5 Signal Bandwidth Ratio Constant................................................... 83
4.7.2.1.6 Center Frequency (Ch1 & Ch2)...................................................... 83
4.7.2.1.7 Fixed Noise (Ch1 & Ch2)............................................................... 83
4.7.2.1.8 Calibrate Fixed Noise Button.......................................................... 83
4.7.2.1.9 Reset Button.................................................................................... 83
4.8 THE BASEBAND OUTPUT TAB (BBOUT)........................................................... 84
5 APPENDIX.............................................................................................................. 85
5.1 PSK-PSK MODE................................................................................................ 85
5.2 FM-FM MODE................................................................................................... 86
5.3 PSK-FM MODE ................................................................................................. 87
5.4 DOPPLER FREQUENCY SHIFT.............................................................................. 88
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5.5 ERROR DETECTION & CORRECTION USING CONVOLUTIONAL CODES AND THE
VITERBI DECODER ......................................................................................................... 89
5.5.1 Convolutional Code Parameters............................................................... 89
5.5.2 Eb/N0and the Fundamentals of Bit Error Rate Testing (BERT)............... 91
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LIST OF FIGURES
Figure 1-1 LS-3x-V with Vertical Signal Interface......................................................... 12
Figure 1-2 LS-3x-F with Faceplate Signal Interface ....................................................... 13
Figure 1-3 LS-3x-ITB Optional Interface Transition Board............................................ 14
Figure 1-4 LS-3x-CTB Chassis Transition Board ........................................................... 15
Figure 1-5 LS-3x Block Diagram.................................................................................... 18
Figure 3-1 LS-3x Interconnection Block Diagram.......................................................... 31
Figure 3-2 LS-3x Front & Rear Views ............................................................................ 32
Figure 3-3 LS-3x-F Faceplate Connectors....................................................................... 33
Figure 3-4 LS-3x Very High Density Cable Interconnect (VHDCI-68) J17 Pin-out...... 34
Figure 3-5 LS-3x-ITB Optional Interface Transition Board Pin-outs ............................. 35
Figure 4-1 LS-3x Main Application Window.................................................................. 36
Figure 4-2 System Options - Directory Sub-Tab............................................................. 37
Figure 4-3 System Options - Operations Sub-Tab........................................................... 38
Figure 4-4 System Options - Utility Sub-Tab.................................................................. 39
Figure 4-5 Display Colors Setup...................................................................................... 39
Figure 4-6 System Options - Unique Card Settings Sub-Tab.......................................... 40
Figure 4-7 LS-3x Hardware Configuration Primary Setup.............................................. 41
Figure 4-8 Firmware Mode Selection Window............................................................... 42
Figure 4-9 The Downconverter Tab (LS-25) With Optional Controls............................ 44
Figure 4-10 Downconverter Status Display..................................................................... 45
Figure 4-11 Downconverter Configuration Display........................................................ 45
Figure 4-12 The Receiver Tab (Primary & Secondary) - PSK-PSK Mode..................... 48
Figure 4-13 PSK Receiver Status Display....................................................................... 49
Figure 4-14 PSK Receiver Primary Sub-Tab................................................................... 49
Figure 4-15 Bit Sync Parameters..................................................................................... 53
Figure 4-16 Viterbi Decoder Parameters......................................................................... 55
Figure 4-17 Post Demodulation Stream Routing............................................................. 56
Figure 4-18 PSK Receiver Secondary Sub-Tab............................................................... 57
Figure 4-19 Stream Control Configurations.................................................................... 58
Figure 4-20 The Receiver Tab (Primary & Secondary) – FM-FM Mode ....................... 60
Figure 4-21 FM Receiver Status Display......................................................................... 61
Figure 4-22 FM Receiver Primary Sub-Tab.................................................................... 61
Figure 4-23 Bit Sync Parameters..................................................................................... 65
Figure 4-24 FM Receiver Secondary Sub-Tab................................................................ 66
Figure 4-25 The Bit Error Rate Test (BERT) Tab........................................................... 67
Figure 4-26 The Modulator Tab (Primary & Secondary) – All Mode ............................ 69
Figure 4-27 Modulator Primary Sub-Tab........................................................................ 70
Figure 4-28 Examples of Spectra With /Without Noise Added (SOQPSK) ................... 73
Figure 4-29 Examples of Constellation With /Without Noise Added (SOQPSK).......... 73
Figure 4-30 Modulator Secondary Sub-Tab.................................................................... 76
Figure 4-31 Pre-Detection Diversity Combiner Block Diagram..................................... 80
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Figure 4-32 The Pre-Detection ........................................................................................ 80
Figure 4-33 Pre-D Status Display.................................................................................... 81
Figure 4-34 Pre-D Configuration Display ....................................................................... 81
Figure 4-35 The Baseband Output Tab (BBOUT) .......................................................... 84
Figure 5-1 LS-3x PSK-PSK Mode Simplified FPGA Block Diagram (IF & Baseband
Signals) ..................................................................................................................... 85
Figure 5-2 LS-3x FM-FM mode Simplified FPGA Block Diagram (IF & Baseband
Signals) ..................................................................................................................... 86
Figure 5-3 LS-3x PSK-FM Mode Simplified FPGA Block Diagram (IF & Baseband
Signals) ..................................................................................................................... 87
Figure 5-4 Convolutional Encoder, K=7, Rate 1/2.......................................................... 90
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1 Introduction
1.1 General
The Lumistar LS-3x Multi-Mode IF Processing
Engine is part of the Lumistar family of digital
processing boards used to build programmable
telemetry systems. As shown in Figure 1-5 on
page 18, the LS-3x consists of an analog front
end and a 10 million gate FPGA based digital
processing engine. The LS-3x can be firmware
configured to perform the functions of an IF1
receiver with multi-mode demodulator, a pre-
detection diversity combiner, a bit synchronizer,
and a multi-mode modulator for self-test and checkout. The analog front end performs
pre-conditioning of the 70 MHz IF input signal prior to acquisition. Signal conditioning
of the receiver and bit synchronizer outputs are also performed in the analog front end.
The digital processing engine is implemented in two large FPGAs and performs the
functions of IF reception, multi-mode demodulation, pre-detection combing, bit
synchronization, as well as the multi-mode test modulator. The all-digital design and
implementation assures a consistent product with high reliability and long-term stability.
The overall performance specification of the LS-3x is summarized in Table 1-1 on page
17.
Like the Chameleon, the LS-3x can take on multiple functional personalities via different
firmware loads. The respective functional capabilities within a personality are
individually enabled or disabled via a firmware license created at the factory at the time
of order. The addition of new functions and capabilities after the product is delivered is a
simple matter of updating the firmware license files installed on the target machine where
the LS-3x card is installed. Currently, there are three functional personalities defined for
the LS-3x. They are respectively designated as; FM-FM,PSK-FM, and PSK-PSK. This
document will focus on the PSK-PSK functional personality. Quick start guides for the
other functional personalities are also available.
In addition to multiple functional personalities implemented via firmware license, the LS-
3x hardware also has two different flavors. Each hardware variant is functionally
identical to the other, but the manner in which the cards I/O signals are made available to
the user are different. Both hardware variants are described in more detail in the
following paragraphs. When the LS-3x is ordered, the customer must specify which
hardware variant is required.
1Typically 70 MHz, although other IF frequencies are possible. Contact the factory for more information.
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1.2 Lumistar LS-3x-V (Vertical Signal Interface)
The LS-3x-V is shown in Figure 1-1 below. In this variant, the primary IF signals are not
brought out on the cards front panel, but instead are made available via vertically
mounted SMB connectors on the left edge of the card. This variant of the LS-3x allows
the system designer to keep all of the critical baseband and IF signals of the card within
the chassis. This makes for cleaner and less cluttered cabling when interconnecting the
LS-3x with other cards in the system.
Figure 1-1 LS-3x-V with Vertical Signal Interface
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1.3 Lumistar LS-3x-F (Faceplate Signal Interface)
The LS-3x-F is shown in Figure 1-2 below. In this variant, the primary IF signals are
brought out on the cards faceplate and are made available via horizontally mounted SMB
connectors on the left edge of the card. This variant of the LS-3x allows the system
designer to connect all of the critical baseband and IF signals of the card to other cards in
the same chassis, or cards in other chassis, via the faceplate.
Figure 1-2 LS-3x-F with Faceplate Signal Interface
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1.4 Lumistar LS-3x-ITB (Interface Transition Board)
The optional LS-3x-ITB, Interface Transition Board allows the system designer to have
access to many of the signals (TTL, RS-422, LVTTL, baseband and IF) coming from and
going to the LS-3x. The LS-3x-ITB plugs into the very high density (VHDCI-68)
connector on the right card edge of the LS-3x as shown in Figure 1-3 below. The ITB
provides both SMB and ribbon cable connectors and is primarily intended to be used in
concert with the LS-3x-CTB chassis transition board described in paragraph 1.5 on page
15.
DDR
DDR
VHDCI - Receptical
VHDCI - Plug
P1
Figure 1-3 LS-3x-ITB Optional Interface Transition Board
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1.5 Lumistar LS-3x-CTB (Chassis Transition Board)
The optional LS-3x-CTB chassis transition board, when used in concert with the LS-3x-
ITB (see paragraph 1.4 on page 14), allows the system designer to bring the large number
of signals associated with the LS-3x to a single chassis mounted connector panel. Three
variants of the LS-3x-CTB are available and are summarized in the table below left. The
CTB gives the system designer the flexibility to configure a system with the appropriate
number of BNC and/or Twinax connectors, while at the same time minimizing the
typical, “rats nest” of interconnecting cables.
Part Number BNC Twinax
LS-3x-CTB-BB 8 -
LS-3x-CTB-BT 4 4
LS-3x-CTB-TT - 8
Figure 1-4 LS-3x-CTB Chassis Transition Board
1.6 Manual Format and Conventions
This manual contains the following sections:
Chapter 1 provides a brief product overview and technical specifications
Chapter 2 provides software installation setup instructions
Chapter 3 provides hardware installation and configuration instructions
Chapter 4 provides initial setup and checkout instructions
Chapter 5 provides additional setup instructions when using Lumistar
downconverter boards
Throughout this document, several document flags will be utilized to emphasis warnings
or other important data. These flags come in three different formats: Warnings, Cautions,
and Information. Examples of these flags appear below.
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Table 1-1 LS-3x Performance Specification
Category: Specifications: Details:
Mechanical Envelope Dimensions – Main Board 8.36”(L) x 3.875”(W) x 0.62” (H)
Envelope including ITB 10.275”(L) x 3.875”(W) x 0.62” (H)
Form Factor > Half-length PCI ; Custom
Weight ~ 8oz.
Electrical Individual power requirements +3.3VDC @ 2.78 A
+5VDC @ 1.68A
+12VDC @ 167mA
-12VDC @ 56mA
Total Power ~ 20.25 Watts
Performance/Limits
IF Input Stage Input Levels +10/-60dBm
Input Frequency Range 50-90 MHz (other options available)
Impedance 50 Ohms
Input P1dB TBD
Noise Figure TBD
Tuner Resolution 1 Hz
Frequency Accuracy 3ppm (Internal Reference)
Demodulation Types PCM FM, OQPSK, QPSK, BPSK, SOQPSK ,
AQPSK, UQPSK
Rates supported 30kbps-25Mbps Tier 0 (typical)
100kbps – 30Mbps Tier 1 (typical)
Viterbi Decoding Rates Supported ½, 1/3, ¾
Baseband Outs Maximum Voltage 3.86Vp-p
Output Filtering 35MHz Low-pass
Output impedance 50 ohms
Modulator Out Output Frequency Range 50-90MHz (other options available)
Impedance 50 Ohms
Output Levels 0 to -80 dBm
Baseband In (Future) (Future)
Connectors 10MHz Reference Input/Output MMCX Jack (J7)
IF Signal Input SMB Jack, Ch. 1 (J4), Ch. 2 (J5)
Baseband Outputs SMB Jack, Ch. 1 (J3), Ch. 2 (J2)
Modulator Output SMB Jack (J1)
Baseband Input SMB Jack (J6)
HD26 Female Clock and data signals, IRIG Input (J8)
Environmental Temperature, Operational 0oto 70oC (Commercial)
Temperature, Storage -20o to 70 oC
Humidity, non-condensing <40 oC 0-90%, >40oC 0-75%
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1
10
19
Local Bus
FPGA Bus
PCI Bus
Figure 1-5 LS-3x Block Diagram
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2 Firmware and Software Installation
The software/firmware installation for the LS-3x is simple and consists of two steps. Two
CD-ROM disks are provided with each LS-3x card when it is shipped. The first CD
contains the install shield wizard program that installs the LRR system software onto the
hard disk drive where the LS-3x card is physically installed. The second CD contains the
unique firmware license files that enable the various LS-3x features and functionality
purchased by the user. Both the LRR system software and the firmware license files must
be installed onto the machine where the LS-3x card is physically installed. If the LS-3x
card is moved to a new machine, the firmware license files must also be moved to the
new machine and installed.
2.1 Step One – Installing the LRR System Software
Place the LRR system software CD into the CD-ROM drive of the computer where the
LS-3x card is installed. From the file browser, navigate to the CD and run the LRR
system software install shield wizard. The file name for the install wizard will be
Setup_LS35_[Version Number]. Depending on the operating system version, one may
see a security warning dialog box like the one shown below. Click “Run” to start the
install.
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When the LRR system installer starts running, the user will see a splash screen like the
one shown below. Click on the “Next” button to proceed with the installation.
Table of contents
