NXP Semiconductors QorIQ LS1028A User manual

QorIQ LS1028A Reference Design Board
Reference Manual
Supports LS1028ARDB Revision C
NXP Semiconductors Document identifier: LS1028ARDBRM
Reference Manual Rev. 3, 07 February 2022

Contents
Chapter 1 LS1028ARDB overview.........................................................................5
1.1 Acronyms and abbreviations..................................................................................................... 5
1.2 Related documentation..............................................................................................................7
1.3 Block diagram............................................................................................................................8
1.4 Board features...........................................................................................................................9
Chapter 2 LS1028ARDB functional description................................................... 13
2.1 Processor................................................................................................................................ 13
2.2 Power supplies........................................................................................................................ 13
2.2.1 Primary power supply................................................................................................................16
2.2.2 Secondary power supplies........................................................................................................ 16
2.2.3 Power supply sequence............................................................................................................ 18
2.2.4 Current and power measurement............................................................................................. 20
2.3 Clocks......................................................................................................................................20
2.4 DDR interface..........................................................................................................................22
2.5 USB interface ......................................................................................................................... 23
2.6 DisplayPort.............................................................................................................................. 25
2.7 SerDes interface......................................................................................................................25
2.8 Ethernet controller interface.................................................................................................... 26
2.8.1 SGMII Ethernet......................................................................................................................... 26
2.8.2 QSGMII Ethernet.......................................................................................................................27
2.8.3 IEEE 1588 interface.................................................................................................................. 28
2.9 Synchronous audio interface (SAI)..........................................................................................29
2.10 M.2 connectors......................................................................................................................30
2.10.1 Adapters..................................................................................................................................31
2.11 DUART interface................................................................................................................... 31
2.12 CAN interface........................................................................................................................ 32
2.13 I2C interface.......................................................................................................................... 33
2.14 XSPI interface........................................................................................................................37
2.15 JTAG port.............................................................................................................................. 38
2.16 eSDHC interface....................................................................................................................39
2.17 MikroBUS click modules........................................................................................................40
2.18 GPIOs....................................................................................................................................42
2.19 Interrupt handling...................................................................................................................42
2.20 Temperature measurement...................................................................................................42
2.21 DIP switches..........................................................................................................................43
2.22 LEDs......................................................................................................................................46
2.22.1 Multi-status LEDs.................................................................................................................... 48
2.23 System controller ..................................................................................................................49
2.23.1 System configuration ..............................................................................................................51
2.23.2 Reset sequencing................................................................................................................... 53
Chapter 3 Qixis Programming Model...................................................................56
3.1 Register Conventions.............................................................................................................. 58
3.2 Resets..................................................................................................................................... 59
3.3 Identification Registers............................................................................................................ 59
3.4 Identification (ID)..................................................................................................................... 59
3.5 Board Version (VER)...............................................................................................................60
3.6 Qixis Version (QVER)..............................................................................................................61
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3.7 Programming Model (MODEL)................................................................................................ 61
3.8 Minor Revision (MINOR)......................................................................................................... 62
3.9 Control and Status Registers...................................................................................................64
3.10 General Control (CTL)...........................................................................................................64
3.11 Auxiliary (AUX)...................................................................................................................... 65
3.12 System Status (STAT_SYS)..................................................................................................65
3.13 Alarm (ALARM)..................................................................................................................... 66
3.14 Presence Detect 1 (STAT_PRES1).......................................................................................67
3.15 Presence Detect 2 (STAT_PRES2).......................................................................................68
3.16 LED Control (LED).................................................................................................................69
3.17 Reconfiguration Registers..................................................................................................... 70
3.18 Reconfiguration Control (RCFG)........................................................................................... 70
3.19 USB Control (USB_STAT).....................................................................................................71
3.20 USB Control (USB_CTL)....................................................................................................... 72
3.21 Watchdog (WATCH)..............................................................................................................73
3.22 Power Control/Status Registers............................................................................................ 74
3.23 Power Control 2 (PWR_CTL2).............................................................................................. 74
3.24 Power Status 0 (PWR_MSTAT)............................................................................................ 75
3.25 Power Status 1 (PWR_STAT1)............................................................................................. 76
3.26 Clock Control Registers.........................................................................................................77
3.27 Clock Speed 1 (CLK_SPD1)..................................................................................................78
3.28 Clock ID/Status (CLK_ID)......................................................................................................78
3.29 Reset Control Registers........................................................................................................ 79
3.30 Reset Control (RST_CTL)..................................................................................................... 79
3.31 Reset Status (RST_STAT).................................................................................................... 80
3.32 Reset Event Trace (RST_REASON)..................................................................................... 81
3.33 Reset Force 1 (RST_FORCE1)............................................................................................. 82
3.34 Reset Force 2 (RST_FORCE2)............................................................................................. 83
3.35 Reset Force 3 (RST_FORCE3)............................................................................................. 84
3.36 Reset Mask 1 (RST_MASK1)................................................................................................ 85
3.37 Reset Mask 2 (RST_MASK2)................................................................................................ 86
3.38 Reset Mask 2 (RST_MASK3)................................................................................................ 87
3.39 Board Configuration Registers.............................................................................................. 88
3.40 Board Configuration 0 (BRDCFG0)....................................................................................... 88
3.41 Board Configuration 1 (BRDCFG1)....................................................................................... 89
3.42 Board Configuration 2 (BRDCFG2)....................................................................................... 90
3.43 Board Configuration 3 (BRDCFG3)....................................................................................... 91
3.44 Board Configuration 4 (BRDCFG4)....................................................................................... 92
3.45 Board Configuration 5 (BRDCFG5)....................................................................................... 93
3.46 Board Configuration 6 (BRDCFG6)....................................................................................... 94
3.47 DUT Configuration Registers.................................................................................................95
3.48 DUT Configuration 0 (DUTCFG0)......................................................................................... 96
3.49 DUT Configuration 1 (DUTCFG1)......................................................................................... 96
3.50 DUT Configuration 2 (DUTCFG2)......................................................................................... 97
3.51 DUT Configuration 11 (DUTCFG11)..................................................................................... 98
3.52 GPIO Registers..................................................................................................................... 98
3.53 GPIO I/O (GPIO_IO)..............................................................................................................99
3.54 GPIO Direction (GPIO_DIR)................................................................................................ 100
3.55 IRQ Status Registers...........................................................................................................101
3.56 Interrupt Status 0 (IRQSTAT0)............................................................................................101
3.57 Interrupt Status 1 (IRQSTAT1)............................................................................................102
3.58 Interrupt Status 2 (IRQSTAT2)............................................................................................102
3.59 Interrupt Drive 5 (IRQDRV5)............................................................................................... 103
3.60 Programmable Interrupt Controller...................................................................................... 104
3.61 PIC Edge (PIC_EDGE)........................................................................................................104
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3.62 PIC Polarity (PIC_POL)....................................................................................................... 105
3.63 PIC Mask (PIC_MASK)........................................................................................................106
3.64 PIC Mask (PIC_PEND)........................................................................................................107
3.65 PIC Status (PIC_STAT).......................................................................................................108
3.66 PIC Control (PIC_CTL)........................................................................................................109
3.67 Core Management Space Registers................................................................................... 110
3.68 Core Management Address (CMSA)...................................................................................111
3.69 Core Management Data (CMSD)........................................................................................ 111
Appendix A How to use LS1027A device on LS1028ARDB.............................. 113
Appendix B Revision History..............................................................................114
NXP Semiconductors
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Chapter 1
LS1028ARDB overview
The QorIQ LS1028A reference design board (LS1028ARDB) provides a comprehensive platform that enables design and
evaluation of the LS1028A processor, which is a dual-core Arm Cortex-v8 A72 processor with frequency up to 1.3 GHz. The board
is lead-free and RoHS-compliant.
The LS1028ARDB can be used to develop and demonstrate human machine interface systems, industrial control systems such as
robotics controllers and motion controllers, and PLCs. The reference design also provides the functionality needed for Industrial
IoT gateways, edge computing, industrial PCs, and wireless or wired networking gateways.
This document provides detailed information about LS1028ARDB interfaces, power supplies, clocks, DIP switches, LEDs, and
CPLD system controller.
1.1 Acronyms and abbreviations
The table below lists and explains the acronyms and abbreviations used in this document.
Table 1. Acronyms and abbreviations
Term Description
CAN Controller area network
CCI Cache coherency interconnect
CPLD Complex programmable logic device
CTS Clear to send
DCM Development system control monitor
DDR SDRAM Double data rate synchronous dynamic random-access memory
DIP Dual inline package
DPAA Data path acceleration architecture
DQS Data strobe
DUART Dual universal asynchronous receiver/transmitter
DUT Device under test
EC Ethernet controller
ECC Error correcting code
eDP Embedded DisplayPort
EMI Ethernet management interface
ENETC Ethernet controller
eMMC Embedded multimedia card
eSDHC Enhanced secure digital host controller
FET Field-effect transistor
FPGA Field-programmable gate array
Table continues on the next page...
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Table 1. Acronyms and abbreviations (continued)
Term Description
GbE Gigabit Ethernet
GPIO General purpose input/output
GT/s GigaTransfers/second
HDLC High-level data link control
HSSI High-speed serial interface
I2C Inter-integrated circuit
JTAG Joint Test Action Group (IEEE Standard 1149.1)
LOS Loss of signal
OCM Offline configuration manager
OTG On-The-Go
PBL Pre-boot loader
PLL Phase-locked loop
PMIC Power management multi-channel IC
POR Power-on reset
PSU Power supply unit
PTP Precision time protocol
PWM Pulse width modulation
QSGMII Quad serial gigabit media independent interface
QSPI Quad serial peripheral interface
RCW Reset configuration word
RTC Real time clock
RTS Request to send
SATA Serial advanced technology attachment
SDRAM Synchronous dynamic random-access memory
SerDes Serializer/deserializer
SGMII Serial gigabit media independent interface
SPD Serial presence detect
SPI Serial peripheral interface
SS Spread spectrum
SSC Spread spectrum clocking
TCXO Temperature compensated crystal (Xtal) oscillator
UART Universal asynchronous receiver/transmitter
Table continues on the next page...
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Table 1. Acronyms and abbreviations (continued)
Term Description
UDIMM Unbuffered dual inline memory module
UFT Universal frequency translator
USB Universal serial bus
XSPI Octal serial peripheral interface
1.2 Related documentation
The table below lists and explains the additional documents and resources that you can refer to for more information on
the LS1028ARDB.
Some of the documents listed below may be available only under a non-disclosure agreement (NDA). To request access to these
documents, contact your local field applications engineer or sales representative.
Table 2. Related documentation
Document Description Link/how to access
QorIQ LS1028A Product
Brief
Provides a brief overview of the LS1028A processor Contact FAE / sales
representative
QorIQ LS1028A Data Sheet Provides information about electrical characteristics, hardware
design considerations, and ordering information
Contact FAE / sales
representative
QorIQ LS1028A Reference
Manual
Provides a detailed description about the LS1028A QorIQ
multicore processor and its features, such as memory map,
serial interfaces, power supply, chip features, and clock
information
Contact FAE / sales
representative
QorIQ LS1028A Chip Errata Lists the details of all known silicon errata for the LS1028A Contact FAE / sales
representative
QorIQ LS1028A Reference
Design Board Getting
Started Guide
Explains the LS1028ARDB settings and physical connections
needed to boot the board
QorIQ LS1028A Reference
Design Board Getting
Started Guide
QorIQ LS1028A Design
Checklist, AN12028
This document provides recommendations for new designs
based on the LS1028A SoC. This document can also be used to
debug newly designed systems by highlighting those aspects of
a design that merit special attention during initial system start-up
Contact FAE / sales
representative
Layerscape Software
Development Kit
Documentation
This document describes how to work with LSDK, which is a
complete Linux kit for NXP QorIQ Arm-based SoCs and the
reference and evaluation boards available for them.
Refer to the section LSDK Quick Start Guide for LS1028ARDB ,
which describes the procedure to program LSDK composite
firmware for LS1028ARDB.
Layerscape Software
Development Kit
CodeWarrior Development
Studio for QorIQ LS series
- Arm V8 ISA, Targeting
Manual
This manual explains how to use the CodeWarrior Development
Studio for QorIQ LS series - Arm V8 ISA product
CodeWarrior Development
Studio for QorIQ LS series
- Arm V8 ISA, Targeting
Manual
Table continues on the next page...
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Table 2. Related documentation (continued)
Document Description Link/how to access
CodeWarrior TAP Probe
User Guide
Provides details of CodeWarrior TAP, which enables target
system debugging through a standard debug port (usually JTAG)
while connected to a developer workstation through Ethernet or
USB
CodeWarrior TAP Probe
User Guide
1.3 Block diagram
The following figure shows the LS1028ARDB block diagram.
QSGMII PHY F104
LS1028A
POWER SUPPLIES
(VDD, GVDD, etc.)
1600 MT/s
DDR4 4GB
SDHC1
JTAG
RS232 IO
USB
3.0
Port 2
I2C
SPD, INA220, TEMP, RTC etc.
DUART
DB9
DB9
JTAG
x1
DDR4
PWR
12V
FANS
12V
RST
Cadence
eDP
QIXMin
CPLD
(EPM2210F256C5N)
PCIe3.0 m.2
Slot
PCIe3.0 m.2
Slot
SATA 3.0
m.2
x1
x1
Display port
connector
47272-0001
Molex
CFG
C
L
O
C
K
S
DC
Switches
USB 3.0
type C
S
E
R
D
E
S
DIFF_
SYSCLK
DPCLK
5P49V5907
25 MHz
M.2 Slot
Clocks
USB
3.0
Port 1
USB 3.0
Type A
uCliq Module (x2)
BLE, BEE, NFC on
SPI/UART/I2C
ENETC
(muxed
with
SAI )
SGMII PHY
AR8033 RJ-45 with
Trans forme r
RJ-4 5 with
Trans forme r
SD1CLK
x2
CAN2 Standard
Display
CAN1 Standard
Display
CAN
Transciever
TJA1051
CAN
Transciever
TJA1051
x4 RJ-45 with
Trans form
er
RJ-4 5 with
Trans form
er
Rmux
A
B
C
D
eMMC-8GB
(MTFC8GAKAJCN-
1M WT)
MuxMux XSPI
A
SPI
Emulator
I2C
Micron xSPI NAND
512MB
(MT29F4G01ABBFD12-ITES:F)
SDHC2
MuxMux
SD Connector
SPI3 }Type-E
WiFi
Type-B
SATA
IEEE1588
Connector &
1PPS SMA
Micron xSPI x8 NOR
256MB
(MT35XU02GCBA1G12)
MuxMux 1010
1111
88
66
99
77
55
33
44
22 11
1212
8
6
9
7
5
3
4
21
12
Audio Codec
SGTL5000 &
LINE OUT Audio LINEOUT
(for Speakers)
IEEE1588
SAI4 TX
RGMII
Figure 1. LS1028ARDB block diagram
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1.4 Board features
The table below lists the features of the LS1028ARDB.
Table 3. LS1028ARDB features
LS1028ARDB feature Specification Description
Processor Two-core processor Two Arm Cortex - A72 processor cores:
• Based on 64-bit ARMv8 architecture
• Up to 1.3 GHz operation
• Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
data cache
• Arranged as a single cluster of two cores sharing a single 1 MB L2
cache
For more details on the LS1028A processor, see QorIQ
LS1028A Family Reference Manual .
NOTE
DDR memory DDR4 • Five onboard 1G x8 discrete memory modules (Four data byte lanes
+ ECC)
• 32-bit data and 4-bit ECC
• One chip select
• Data transfer rates of up to 1.6 GT/s
• Single-bit error correction and double-bit error detection ECC (4-bit
check word across 32-bit data)
High-speed serial ports
(SerDes)
One four-lane SerDes • Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
Qualcomm AR8033 PHY
• Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
through the NXP F104S8A PHY
• Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
(8 Gbit/s) cards
• Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2
Key-B slot through a register mux to support either PCIe Gen 3 (8
Gbit/s) or SATA Gen 3 cards (6 Gbit/s) at a time
eSDHC eSDHC1 Supports a secure digital (SD) connector for connecting an external SD
3.0 card
eSDHC2 • Onboard 8 GB eMMC memory (MTFC8GAKAJCN) supporting
— x1, x4, and x8 I/Os
— SDR/DDR modes up to 52 MHz clock speed
— HS200/HS400 modes
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Table 3. LS1028ARDB features (continued)
LS1028ARDB feature Specification Description
SPI SPI3 Connects to two mikroBUS sockets to support mikro-click modules, such
as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near field
communications (NFC) controller
Octal SPI (XSPI) One XSPI (XSPI A) • One 256 MB onboard XSPI serial NOR flash memory
• One 512 MB onboard XSPI serial NAND flash memory
• Supports a QSPI emulator for offboard QSPI emulation
I2C Six I2C interfaces • All system devices are accessed via I2C1, which is multiplexed on
I2C multiplexer PCA9848 to isolate address conflicts and reduce
capacitive load
• I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules
1 and 2
Serial ports Two UART ports
(UART1 and UART2)
• UART1 supports RS-232 levels of up to 1 Mbit/s data rate on a DB9
male connector. LTC8204 RS-232 transceiver is used for interface
conversion. Hardware handshaking is not supported.
• UART2 can be used to interface with either mikro-click modules or
RS-232 transceiver LTC2804 (similar to UART1). The selection can
be controlled from FPGA.
CAN Two CAN ports
(CAN1 and CAN2)
The two CAN DB9 ports can support CAN FD fast phase at data rates of
up to 5 Mbit/s.
Ethernet SGMII (1 GB
Ethernet port)
QSGMII (four 1 GB
Ethernet ports)
IEEE 1588
• Five 1G/100M/10BaseT Ethernet ports supported. One port is
supported on SGMII ENET MAC and the other four through the TSN
switch.
• Five RJ45 connectors with link and activity status are used with the
SGMII and QSGMII interfaces
• IEEE 1588 precision time protocol (PTP) is supported through
an onboard header (J11) and SMA connector (J12) on the
PULSE_OUT1 signal for 1PPS timing signal generation
USB 3.0 Two high-speed USB
3.0 ports with
integrated PHYs
• Supports super-speed (5 Gbit/s) operations
• USB 3.0 port 1 is configured as host with a Type A connector
• USB 3.0 port 2 is configured as downstream facing port (DFP) or
upstream facing port (UFP) with a Type C connector
Serial audio interface
(SAI)
Audio transceiver
(used only on TX
signals)
• Audio codec SGTL5000 provides headphone and audio LINEOUT for
stereo speakers
• IEEE1588 interface to support audio on SAI4
Display DisplayPort • Supports display resolution of up to 4Kp60
• Supports link transfer rates of up to HBR2 (5.4 Gbit/s)
Table continues on the next page...
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Table 3. LS1028ARDB features (continued)
LS1028ARDB feature Specification Description
Clocks Differential system
clock (DIFF_SYSCLK)
100 MHz
SerDes clocks REF_CLK1 and REF_CLK2 of 100 MHz
Ethernet clocks 125 MHz clock to Ethernet controller either from the IEEE 1588 port or an
onboard oscillator
Display Port clock
(DP_REFCLK)
27 MHz
FPGA CLK 25 MHz clock to CPLD
Power supplies • 12 V input power from DC input adapter
• 5.0 V for USB1, USB2, CAN1, CAN2, and mikro-click modules
• 1.0 V (VDD) for core and platforms
• Filtered 1.0 V / 0.9 V USB_SDVDD, USB_SVDD, DP_SVDD, SVDD
• 3.3 V for board components (SGMII PHY, M.2 connectors, SD card,
eMMC, CAN transceivers, mikroBUS connectors, LEDs, DP port,
CPLD IO and VDD, clockgen VDDO)
• Filtered 3.3 V for USB_HVDD
• 1.8 V for board components (UART transceivers, XSPI memories,
eMMC memory IO VDD, CPLD IO bank3)
• 1.8 V clockgen VDD and VDDA
• 1.8 V OVDD, TH_VDD
• Filtered 1.35 V X1VDD, AVDD_SD1_PLL1, AVDD_SD1_PLL2
• 2.5 V QSGMII PHY VDD25, VDD25A, and DDR4 memory VPP
• 1.0 V QSGMII PHY VDD, VDDA
• 1.2 V DRAM VDD
• 0.6 V DRAM VTT, VREF
• 3.3 V / 1.8 V EVDD for eSDHC
• 0.9 V / 1.0 V TA_BB_VDD
Debug interface • Arm Cortex 10-pin JTAG connector
• CPLD programming header
Package • Package type is Flip Chip, Plastic-ball, Grid Array (FC-PBGA), 17 mm
x 17 mm
• Socket and heat sink are included
System logic CPLD • Manages the following:
— System reset sequencing
Table continues on the next page...
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Table 3. LS1028ARDB features (continued)
LS1028ARDB feature Specification Description
— SoC POR configuration at reset
• Implements registers for system control and monitoring
• General fault monitoring and logging
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Chapter 2
LS1028ARDB functional description
This chapter explains all major functional components of the LS1028ARDB. The chapter is divided into the following sections:
•Processor
•Power supplies
•Clocks
•DDR interface
•USB interface
•DisplayPort
•SerDes interface
•Ethernet controller interface
•M.2 connectors
•DUART interface
•CAN interface
•I2C interface
•XSPI interface
•JTAG port
•eSDHC interface
•MikroBUS click modules
•GPIOs
•Interrupt handling
•Temperature measurement
•DIP switches
•LEDs
•System controller
2.1 Processor
The LS1028ARDB board is based on the QorIQ LS1028A processor having two Arm® Cortex®- A72 processor cores. The
LS1028ARDB board supports as many features of the LS1028A as possible.
For more details about the LS1028A processor, see QorIQ LS1028A Reference Manual . The QorIQ LS1028A
Reference Manual is available only under a non-disclosure agreement (NDA). To request access, contact your
local NXP field applications engineer or sales representative.
NOTE
2.2 Power supplies
The LS1028ARDB generates all the voltages necessary for the correct operation of the LS1028A processor, DDR4, PHYs, and
numerous other peripherals. All power is derived from an external 12 V DC power supply.
The following figures show the block diagram of LS1028ARDB power supplies:
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DDR3/2 PS
1.35/1.5V/1.8V
USB_SDVDD
0.9V/1.0V@ 0.2A
USB_SVDD
0.9V/1.0V@ 0.2A
SVDD
0.9/1.0 @ 5A
LPFx2
LPF
LPF
LS1028 USB_SDVDD
LS1028 USB_SVDD
LS1028 SVDD
CORE & PLAT
Current
Measuring
INA220
I2C1_CH2
VDD=1V0
Est 7A
VDD_CORE_PL
1mOHm
WSL27261L000FEA 3W
VDD
1/0.9 V@ 11A
DP_SVDD
0.9V/1.0V@ 0.1A
LPF LS1028 DP_SVDD
12V0
J5
12V, 5A
Adaptor CHASSIS FAN1
LTC7151S
VIN
PS_VDD_PG
LED
LTC7151S
VIN
PS_3V3_PG
LED
3.3V
3.3V @ 15A
VDD
3V3
PS_3V3_PG LT8609SEV
VIN
PS_5V0_PG
5.0V
5V @ 2A
5V0
LPF x2 LS1028 USB_HVDD
USB_HVDD
3.3V @ .45 A
POWER
SWITCH
LTC2955-2 PWR_EN
12V0_IN
J3
J4
CHASSIS FAN2
DUT SOCKET FAN
PS_VDD_EN
BOARD COMPONENTS
CLOCKGEN VDDO
CPLD IO & VDD
DP PORT DP_PWR
SGMII PHY
M.2 CONNECTORS
SD CA RD
eMMC MEMORY
I2C EEPROMs
CURRENT MONITOR INA220
TEMPERATURE MONITOR SA56004ED
RTC PCF2129AT
CAN TRANSCEIVERS
MIKROBUS CONNECTORS
LEDs
MISC PARTS (BUFFERS & TRANSLATORS
BOARD COMPONENTS
USB 1 (TYPE C) AND 2 (TYPE A)
CAN TRANSCEIVERS
MIKROCLICK MODULES
Figure 2. Power supplies - Part 1
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LS1028 EVDD
to CPLD
PS_DDR_EN
VR500
PS_VDD_EN
LPFx6
to regulators
LS1028 PROG_MTR
HDR 1x2
LS1028 TA_PROG_SFP
HDR 1x2 1K
1K
2.5V @0.8A
POR_OUT_VR500_B
PS_3V3_EN
EVDD SWITCH
FPF1321UCX
3.3V/1.8V
VOUT2
VOUT1
LS1028 AVDD_CGA1
LS1028 AVDD_CGA2
LS1028 AVDD_PLAT
LS1028 DP_SAVDD
LS1028 AVDD_D1
LS1028 AVDD_PIXEL
1V0
1.0V @ 1.1A QSGMII PHY VDD, VDDA
VOUT3
VOUT4
QSGMII PHY VDD25, VDD25A
DDR4 MEMORY VPP
LPFx2
X1VDD
1.35V LS1028 X1VDD
1.35V @0.4A AVDD_SD
1.35
LPFx4
LS1028 AVDD_SD1_PLL1
LS1028 AVDD_SD1_PLL2
2V5
1V35
BOARD COMPONENTS
CLOCKGEN VDD & VDDA
CPLD IO BANK3
UART TRANSCEIVER
XSPI MEMORIES
eMMC MEMORY IO VDD
MISC PARTS (BUFFERS & TRANSLATORS)
LS1028 OVDD, TH_VDD
1.8V
@2.5A
{
EN
PORB
LDO2
LDO4
1V8
3.3V
1.8V
SD_VSEL
from LS1028
SD_VSEL: EVDD
0 : 3.3V
1 : 1.8V
GVDD
1.2V @ 5A
MC34716EP/R2
DDR4 VDDQ,
VTT, VREF
VDDQ,SINK/SOURCE
DDR TERMINATION
REGULATOR
PS_DDR_EN
PS_DDRREG_PG_B
VTT
0.60V @ 3A
VREFCA_S
0.60V @ 3A
To CPLD
3V3
DRAM VTT
DRAM VREFCA_S
LS1028 VCC_GVDD
VCC_GVDD_S DRAM VDD
SD_B
3V3 PVIN1:4
VLDOIN
1V2
VTT-0V6
MVREF-0V6
EVDD
LS1028 TA_BB_VDD
TA_BB_VDD
0.9V/1.0V @ .15A
MAX8902B
3.3V
BAT
3V_STBY
TA_BB_VDD
Figure 3. Power supplies - Part 2
Note that several power supplies have onboard low-pass filters, to prevent board switching noise from coupling into sensitive
analog supplies. The figure below shows the filters used.
2.2uF 2.2uF
2.2uF =NFM18PC22 5B1A3
2.2uF =GRM155R60J225KE95
LPF
LPF
47uF 3nF
4.7uF
0.33OHm
LPF
10uF 1uF
5.1OHm
0.22uF
Figure 4. Passive low pass filters
NXP Semiconductors
LS1028ARDB functional description
QorIQ LS1028A Reference Design Board Reference Manual, Rev. 3, 07 February 2022
Reference Manual 15 / 116

2.2.1 Primary power supply
The LS1028ARDB is powered up through an external 12 V DC power adapter. The specifications of the DC adapter are as follows:
• Input: 100 - 240 VAC, 50 - 60 Hz
• Output: 12 V, 0 - 5 A DC power supply adapter (160 W) - Standard
• DC Jack (2 pin, 2.5 mm x 5.5 mm x 11 mm)
2.2.2 Secondary power supplies
The following table lists different power supply components used to generate various LS1028ARDB power supplies.
Table 4. Secondary power supplies
Part
identifier
Manufacturing
part number
Part
manufacturer
Power
supply
Specifications Description
U1 LT8609SEV Linear
Technology
5V0 5 V at 2 A Supplies power to the board components:
• USB 1 and USB 2 connectors
• CAN transceivers
• Mikro-click modules
U2 LTC7151S Linear
Technology
VDD 1.0 V / 0.9 V at 20
A1
Supplies power to the LS1028A core
supplies.
Filtered VDD
also powers USB
(USB_SDVDD,
USB_SVDD),
Display Port
(DP_SVDD), and
SerDes (SVDD)
power supplies
of LS1028A.
NOTE
U3 LTC7151S Linear
Technology
3V3 3.3 V at 15 A Supplies power to board components:
CPLD IO and VDD, Display Port,
SGMII PHY, M.2 connectors, SD
card, eMMC memory, I2C EEPROMs,
current monitor (INA220), Temperature
monitor (SA56004ED), CAN transceivers,
mikroBUS connectors, misc components
(buffers and translators).
Filtered 3V3
also powers
USB (USB_HVDD
of LS1028A).
NOTE
U4 MC34716EP NXP
Semiconductors
1V2 1.2 V at 4 A DDR4 DRAM memories
LS1028A DRAM controller core and I/O
Table continues on the next page...
NXP Semiconductors
LS1028ARDB functional description
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Table 4. Secondary power supplies (continued)
Part
identifier
Manufacturing
part number
Part
manufacturer
Power
supply
Specifications Description
VTT_0V6 0.6 V at 3 A Address and control bus termination
supply
MVREF 0.6 V at 3 A Reference voltage for DDR4 DRAM
memories
U6 MC34VR500V9
ES
NXP
Semiconductors
1V0, 2V5,
1V35, 1V8
• 1.0 V at 1.1 A
• 2.5 V at 0.8 A
• 1.35 V at 0.4 A
• 1.8 V at 2.5 A
Multi-output DC-DC regulator with four
switched outputs, two LDO outputs
(VDD and DDR enable), and one reset
control output to CPLD (RST_OUT). Four
switched outputs are:
• SW1LX: 1.0 V for the QSGMII PHY
VDD and VDDA
• SW2LX: 2.5 V for QSGMII PHY
VDD25, VDD25A, and DDR4 memory
VPP
• SW3LX: 1.35 V; Filtered 1.35
V is supplied to LS1028A
X1VDD, AVDD_SD1_PLL1, and
AVDD_SD1_PLL2
• SW4LX: 1.8 V for board components:
UART transceiver, XSPI memories,
eMMC memory IO, CPLD IO bank3,
clockgen VDD and VDDA
Filtered 1V8 also
powers LS1028A
power supplies:
AVDD_CGA1,
AVDD_CGA2,
AVDD_PLAT,
DP_SAVDD,
AVDD_D1,
and AVDD_PIXEL.
NOTE
Jumper-enabled
1V8 also powers
PROG_MTR
and PROG_SFP.
NOTE
U7 FPF1321UCX ON
Semiconductor
EVDD 3.3 V
1.8 V
eSDHC IO Power.
Table continues on the next page...
NXP Semiconductors
LS1028ARDB functional description
QorIQ LS1028A Reference Design Board Reference Manual, Rev. 3, 07 February 2022
Reference Manual 17 / 116

Table 4. Secondary power supplies (continued)
Part
identifier
Manufacturing
part number
Part
manufacturer
Power
supply
Specifications Description
EVDD boots up to
3.3 V and can be
changed to 1.8 V
depending upon the
SD_VSEL pin state
that is controlled
from the LS1028A
SDHC IP block.
NOTE
The FPF1321UCX
is a power switch,
not a power supply.
NOTE
.
U8 MAX8902B Maxim
Integrated
TA_BB_V
DD
0.9 V / 1.0 V at 0.15
A
Power supply for TA_BB_VDD.
1. VDD is 1.0 V or 0.9 V depending upon the state of GPIO1_DAT24 GPIO pin of LS1028A.
2.2.3 Power supply sequence
The LS1028ARDB board is configured to switch ON automatically when the 12 V power supply is switched ON and is connected
to jack (J1) on the board.
The 12 V input can be subsequently power cycled using the following events:
• The power switch (push button) is pressed
• The register bit, PWR_CTL2[PWR], is set to ‘1’ using the I2C or JTAG/CCS communication paths
On the availability of 12 V supply to the power regulators, the orderly enable of all power supplies are sequenced using powergood
of the regulators, as shown in the following figure.
NXP Semiconductors
LS1028ARDB functional description
QorIQ LS1028A Reference Design Board Reference Manual, Rev. 3, 07 February 2022
Reference Manual 18 / 116

LTC7151S
(12V => 3.3V)
VIN 3.3V
12V
12V
EN PG
LT8609SEV
(12V => 5V)
VIN
12V
EN
5V
VR500 V9
VIN
3.3V
EN
SW1 1V
SW2 2.5V
SW4 1.35V
SW3 1.8V
RST_OUT
LDO2
LDO4 PS_DDR_EN
PS_VDD_EN
To CPLD
LTC7151S
(12V => 1V/
0.9V)
VIN
12V
EN
VDD
MC34716EP/R2
(12V => 1.2V
=> VTT, VREF)
VIN
3.3V
EN
VDD
PG
PG_B
12V
3.3V
soft-start from 12V
5V
soft-start from 3.3V PG
2.5V VR500 SEQ2 internally programmed
1ms VR500 SEQ3 internally programmed
1.8V
VR500 SW3
VIN
LTC7151S 3V3
LT8609S 3V3
VR500 SW2
1ms VR500 SEQ4 internally programmed
1.35V
VR500 SW4
1ms
VR500 SEQ5 internally programmed
1.0V, LDO2
LTC7151S VDD
VDD (0.9/1V)
VR500 SW1, LDO2
soft-start after LDO2 (PS_VDD_EN)
tss
MC34716
DDR4 (1.2V, VTT, VREF)
VR500 SEQ8 internally programmed
VR500 LDO4
LDO4
soft-start after LDO4 (PS_DDR_EN)
To CPLD
To CPLD
To CPLD
PS_3V3_PG
PS_VDD_PG
PS_V5V0_PG
PS_DDR_PG_B
PS_3V3_PG RST_POR_B
PG
From DC jack
1ms
RST_OUT (to CPLD)
VR500 RST_OUT
Internal delay from last SEQ EVENT
3.87ms
1.8ms
2ms
3ms
6ms + 2.5ms +
3.2ms
2ms
Figure 5. Power up voltage sequence
The LS1028ARDB follows the power supply sequencing requirements as detailed in QorIQ LS1028A Data Sheet .
NOTE
NXP Semiconductors
LS1028ARDB functional description
QorIQ LS1028A Reference Design Board Reference Manual, Rev. 3, 07 February 2022
Reference Manual 19 / 116

2.2.4 Current and power measurement
The LS1028ARDB implements onboard current and power measurements only for the VDD supply. The table below lists all
measurable supplies.
Table 5. Power monitoring
Power Measurement device Shunt resistor value Notes
VDD INA220 0.001 The VDD supply powers the
LS1028A core (0.9 V / 1 V),
USB (USB_SDVDD, USB_SVDD),
DisplayPort (DP_SVDD) and
SerDes (SVDD) power supplies.
Power supplies not listed in the above table are considered as low-current/incidental supplies and are not instrumented for
power measurement.
2.3 Clocks
The LS1028ARDB provides all the clocks required for the processor and peripheral interfaces. The figure below shows the
LS1028ARDB clock architecture.
LS1028A
TSEC_1588_CLK_IN
(EC1_RX_CLK)
DP_REFCLK_P/N
DIFF _SYSCLK_(P/N)
27 MHz LVDS
PEx Conn.
100 MHz
LP-HCSL
3SLOTn_REFCLK_[P,N]
SD1_REF_CLK[1:2]
Differential
Single-ended
1588 Header
125.00 MHz
1.8V LVCMOS
3
SLOT[1:2]_CLK_REQ SLOT[1:2]_PRESENT_B
OE_B
100 MHz LP-HCSL 2
VDDO_2
VDDO_4
VDDO_0
VDDO_1
VDDA/VDD/VDD_CORE
3V3
OTP and
Control
Logic
I2C1_CH1
0x6A
1V8
VDDO
25 MHz
XOUT
XIN
PLL
~
FOD1
FOD2
FOD3
FOD4
OE
OE_Buffer
OE(3,5)_B
OE(6,7)_B
No Spread Support
in Design
OUT1
OUT2
OUT3,5
OUT(6,7)
OUT4
5P49V5907B520NDGI
OUT0_SEL_I2CB 25 MHz
1.8V LVCMOS
HOT_CLK
to CPLD
10K
100 MHz HCSL
CLKGEN_OE67_B
To CPLD
*Device doesn t support switching power
rails off, even if outputs are unused.
TSEC_1588_CLK_IN
F104
(QSGMII PHY)
125MHz
XO
125 MHz LVDS
3V3
1V8
X
From CPLD
27MHz
XO
Figure 6. LS1028ARDB clock architecture
The 5P49V5907B520NDGI is a programmable clock generator that generates most of the clocks. Clock configurations are stored
in its one-time programmable (OTP) memory. The configuration in volatile memory can be changed through the I2C1_CH1
NXP Semiconductors
LS1028ARDB functional description
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Reference Manual 20 / 116