Macronix MX25L4006E User manual

1
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
MX25L4006E
3V, 4M-BIT [x 1/x 2]
CMOS SERIAL FLASH MEMORY
Key Features
• Hold Feature
• Low Power Consumption
• Auto Erase and Auto Program Algorithms
• Provides sequential read operation on whole chip

2
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
Contents
FEATURES .................................................................................................................................................................. 4
GENERAL DESCRIPTION ......................................................................................................................................... 5
PIN CONFIGURATIONS .............................................................................................................................................. 5
PIN DESCRIPTION...................................................................................................................................................... 5
BLOCK DIAGRAM....................................................................................................................................................... 6
MEMORY ORGANIZATION ......................................................................................................................................... 7
Table 1. Memory Organization ............................................................................................................................. 7
DEVICE OPERATION .................................................................................................................................................. 8
Figure 1. Serial Peripheral Interface Modes Supported ....................................................................................... 8
DATA PROTECTION.................................................................................................................................................... 9
Table 2. Protected Area Sizes .............................................................................................................................. 9
HOLD FEATURE........................................................................................................................................................ 10
Figure 2. Hold Condition Operation ........................................................................................................ 10
Table 3. Command Denition ............................................................................................................................. 12
COMMAND DESCRIPTION....................................................................................................................................... 13
(1) Write Enable (WREN) ................................................................................................................................... 13
(2) Write Disable (WRDI).................................................................................................................................... 13
(3) Read Status Register (RDSR) ...................................................................................................................... 14
(4) Write Status Register (WRSR)...................................................................................................................... 15
Table 4. Protection Modes.................................................................................................................................. 15
(5) Read Data Bytes (READ) ............................................................................................................................. 16
(6) Read Data Bytes at Higher Speed (FAST_READ) ....................................................................................... 16
(7) Dual Output Mode (DREAD)......................................................................................................................... 16
(8) Sector Erase (SE) ......................................................................................................................................... 16
(9) Block Erase (BE)........................................................................................................................................... 17
(10) Chip Erase (CE).......................................................................................................................................... 17
(11) Page Program (PP)..................................................................................................................................... 17
(12) Deep Power-down (DP) .............................................................................................................................. 18
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ............................................. 18
(14) Read Identication (RDID) .......................................................................................................................... 19
(15) Read Electronic Manufacturer ID & Device ID (REMS) .............................................................................. 19
Table 5. ID Denitions ........................................................................................................................................ 19
(16) Read SFDP Mode (RDSFDP)..................................................................................................................... 20
Read Serial Flash Discoverable Parameter (RDSFDP) Sequence.................................................................... 20
Table 6. Signature and Parameter Identication Data Values ........................................................................... 21
Table 7. Parameter Table (0): JEDEC Flash Parameter Tables ......................................................................... 22
Table 8. Parameter Table (1): Macronix Flash Parameter Tables ...................................................................... 24
POWER-ON STATE ................................................................................................................................................... 26
ELECTRICAL SPECIFICATIONS.............................................................................................................................. 27
Absolute Maximum Ratings................................................................................................................................ 27

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
Figure 3. Maximum Negative Overshoot Waveform .......................................................................................... 27
Capacitance TA = 25°C, f = 1.0 MHz.................................................................................................................. 27
Figure 4. Maximum Positive Overshoot Waveform ............................................................................................ 27
Figure 5. Input Test Waveforms and Measurement Level.................................................................................. 28
Figure 6. Output Loading.................................................................................................................................... 28
Table 9. DC Characteristics (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V) ........................................... 29
Table 10. AC Characteristics (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V) .......................................... 30
Table 11. Power-Up Timing ................................................................................................................................ 31
Timing Analysis ........................................................................................................................................................ 32
Figure 7. Serial Input Timing .............................................................................................................................. 32
Figure 8. Output Timing...................................................................................................................................... 32
Figure 9. Hold Timing ......................................................................................................................................... 33
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 ............................................... 33
Figure 11. Write Enable (WREN) Sequence (Command 06) ............................................................................. 34
Figure 12. Write Disable (WRDI) Sequence (Command 04).............................................................................. 34
Figure 13. Read Status Register (RDSR) Sequence (Command 05) ................................................................ 34
Figure 14. Write Status Register (WRSR) Sequence (Command 01)............................................................... 35
Figure 15. Read Data Bytes (READ) Sequence (Command 03) ...................................................................... 35
Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................... 36
Figure 17. Dual Output Read Mode Sequence (Command 3B)......................................................................... 36
Figure 18. Sector Erase (SE) Sequence (Command 20) .................................................................................. 37
Figure 19. Block Erase (BE) Sequence (Command 52 or D8).......................................................................... 37
Figure 20. Chip Erase (CE) Sequence (Command 60 or C7) ........................................................................... 37
Figure 21. Page Program (PP) Sequence (Command 02)................................................................................ 38
Figure 22. Deep Power-down (DP) Sequence (Command B9)......................................................................... 38
Figure 23. Read Electronic Signature (RES) Sequence (Command AB).......................................................... 39
Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB) ............................................... 39
Figure 25. Read Identication (RDID) Sequence (Command 9F)...................................................................... 40
Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90).............................. 40
Figure 27. Power-up Timing ............................................................................................................................... 41
OPERATING CONDITIONS....................................................................................................................................... 42
Figure 28. AC Timing at Device Power-Up......................................................................................................... 42
Figure 29. Power-Down Sequence .................................................................................................................... 43
ERASE AND PROGRAMMING PERFORMANCE .................................................................................................... 44
DATA RETENTION ................................................................................................................................................... 44
LATCH-UP CHARACTERISTICS .............................................................................................................................. 44
ORDERING INFORMATION ...................................................................................................................................... 45
PART NAME DESCRIPTION..................................................................................................................................... 46
PACKAGE INFORMATION........................................................................................................................................ 47
REVISION HISTORY ................................................................................................................................................. 52

4
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
4M-BIT [x 1/x 2] CMOS SERIAL FLASH
FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• 4,194,304 x 1 bit structure or 2,097,152 x 2 bits (Dual Output mode) structure
• 128 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 8 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 86MHz serial clock
- Serial clock of Dual Output mode: 80MHz
- Fast program time: 0.6ms(typ.) and 3ms(max.)/page (256-byte per page)
- Byte program time: 9us (typ.)
- Fast erase time: 40ms(typ.)/sector (4K-byte per sector) ; 0.4s(typ.)/block (64K-byte per block)
• Low Power Consumption
- Low active read current: 12mA(max.) at 86MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (typ.)
- Low active sector erase current: 9mA (typ.)
- Low standby current: 15uA (typ.)
- Deep power-down mode 2uA (typ.)
• Minimum 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP2 status bit denes the size of the area to be software protected against Program and Erase in-
structions
• Auto Erase and Auto Program Algorithms
-
Automatically erases and veries data at selected sector
-
Automatically programs and veries data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state rst)
• Status Register Feature
• Electronic Identication
- JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• PACKAGE
- 8-pin SOP (150mil)
-
8-pin SOP (200mil)
- 8-pin PDIP (300mil)
- 8-land WSON (6x5mm, 0.8mm package height)
- 8-land USON (2x3x0.6mm)
-
All devices are RoHS Compliant and Halogen-free

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
GENERAL DESCRIPTION
The device features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data output (SO), and a chip select (CS#).
Serial access to the device is enabled by CS# input.
When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.
The device provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
ed page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or
word basis for erase command is executes on sector, or block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000
program and erase cycles.
PIN CONFIGURATIONS
SYMBOL DESCRIPTION
CS# Chip Select
SI/SIO0 Serial Data Input (for 1 x I/O) / Serial Data
Input & Output (for Dual Output mode)
SO/SIO1 Serial Data Output (for 1 x I/O) / Serial
Data Output (for Dual Output mode)
SCLK Clock Input
WP# Write Protection
HOLD# Hold, to pause the device without
deselecting the device
VCC + 3.3V Power Supply
GND Ground
PIN DESCRIPTION
8-PIN SOP (150/200mil)
8-LAND, WSON (6x5mm)
8-PIN PDIP (300mil)
1
2
3
4
CS#
SO/SIO1
WP#
GND
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
1
2
3
4
CS#
SO/SIO1
WP#
GND
VCC
HOLD#
SCLK
SI/SIO0
8
7
6
5
8-LAND USON (2x3mm)
1
2
3
4
CS#
SO/SIO1
WP#
GND
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
1
2
3
4
CS#
SO/SIO1
WP#
GND
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Y-Decoder
X-Decoder
Data
Register
SRAM
Buffer
SI/SIO0
SCLK Clock Generator
State
Machine
Mode
Logic
Sense
Amplifier
HV
Generator
Output
Buffer
SO/SIO1
CS#,
WP#,
HOLD#

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
Table 1. Memory Organization
Block Sector Address Range
7
127 07F000h 07FFFFh
:::
112 070000h 070FFFh
6
111 06F000h 06FFFFh
:::
96 060000h 060FFFh
5
95 05F000h 05FFFFh
:::
80 050000h 050FFFh
4
79 04F000h 04FFFFh
:::
64 040000h 040FFFh
3
63 03F000h 03FFFFh
:::
48 030000h 030FFFh
2
47 02F000h 02FFFFh
:::
32 020000h 020FFFh
1
31 01F000h 01FFFFh
:::
16 010000h 010FFFh
0
15 00F000h 00FFFFh
:::
3 003000h 003FFFh
2 002000h 002FFFh
1 001000h 001FFFh
0 000000h 000FFFh
MEMORY ORGANIZATION

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. The CS# falling time needs to
follow tCHCL spec.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge. The CS# rising time needs to follow tCLCH spec.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of serial peripheral interface mode 0 and mode 3 is shown as Figure 1.
5. For the following instructions: RDID, RDSR, READ, FAST_READ, RDSFDP, DREAD, RES and REMS the shift-
ed-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS#
can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must
go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Peripheral Interface Modes Supported
SCLK
MSB
CPHA
SI
0
1
CPOL
0(Serial mode 0)
(Serial mode 3) 1
SO
SCLK
MSB
shift in shift out
Note:
CPOL indicates clock polarity of serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which serial mode is
supported.

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specic command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Deep Power Down Mode: By entering deep power down mode, the ash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-
nature command (RES).
I. Block lock protection
- Software Protection Mode (SPM): by using BP0-BP2 bits to set the part of Flash protected from data change.
- Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP2 bits and SRWD bit from
data change.
Table 2. Protected Area Sizes
Status bit Protect level 4Mb
BP2 BP1 BP0
0 0 0 0 (none) None
0 0 1 1 (1 block) Block 7
0 1 0 2 (2 blocks) Block 6-7
0 1 1 3 (4 blocks) Block 4-7
1 0 0 4 (8 blocks) All
1 0 1 5 (All) All
1 1 0 6 (All) All
1 1 1 7 (All) All

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start
until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial
Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial
Clock being low).
Figure 2. Hold Condition Operation
Valid Data Valid Data Valid DataDon’t care
High_Z High_Z
Don’t care
Bit 7 Bit 6 Bit 5
Bit 5
Bit 7
Bit 7 Bit 6
Bit 6
HOLD#
CS#
SCLK
SI/SIO0
SO/SIO1
(internal)
SO/SIO1
(External)
≈ ≈ ≈ ≈ ≈ ≈ ≈≈
Valid Data Valid Data Valid DataDon’t care
High_Z High_Z
Don’t care
Bit 7 Bit 6 Bit 5 Bit 3Bit 4
Bit 7 Bit 6 Bit 4
Bit 5 Bit 3
HOLD#
CS#
SCLK
SI/SIO0
SO/SIO1
(internal)
SO/SIO1
(External)
≈ ≈ ≈ ≈ ≈ ≈ ≈≈

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will
keep high impedance until Hold# pin goes high and SCLK goes low. The Serial Data Input (SI) is don't care if
both Serial Clock (SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin
goes high. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To
re-start communication with chip, the HOLD# must be at high and CS# must be at low.
Note: The HOLD feature is disabled during Quad I/O mode.

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
Table 3. Command Denition
COMMAND
(byte)
WREN
(write
Enable)
WRDI
(write disable)
WRSR
(write status
register)
RDID
(read
identication)
RDSR
(read status
register)
READ
(read data)
Fast Read
(fast read
data)
1st 06 Hex 04 Hex 01 Hex 9F Hex 05 Hex 03 Hex 0B Hex
2nd AD1 AD1
3rd AD2 AD2
4th AD3 AD3
5th Dummy
Action
sets the
(WEL) write
enable latch
bit
reset the
(WEL) write
enable latch
bit
to write new
status register
output the
manufacturer
ID and 2-byte
device ID
to read out
the status
register
n bytes read
out until CS#
goes high
n bytes read
out until CS#
goes high
COMMAND
(byte)
RDSFDP
(Read SFDP)
RES (Read
Electronic ID)
REMS (Read
Electronic
Manufacturer
& Device ID)
DREAD
(Double
Output Mode
command)
SE
(Sector
Erase)
BE
(Block Erase)
CE
(Chip Erase)
1st 5A Hex AB Hex 90 Hex 3B Hex 20 Hex 52 or D8 Hex 60 or C7 Hex
2nd AD1 x x AD1 AD1 AD1
3rd AD2 x x AD2 AD2 AD2
4th AD3 x ADD(1) AD3 AD3 AD3
5th Dummy Dummy
Action
Read SFDP
mode
to read out
1-byte Device
ID
Output the
manufacturer
ID and device
ID
n bytes read
out by Dual
Output until
CS# goes
high
to erase the
selected
sector
to erase the
selected
block
to erase
whole chip
(1) ADD=00H will output the manufacturer's ID rst and ADD=01H will output device ID rst.
(2) It is not recommended to adopt any other code which is not in the above command denition table.
COMMAND
(byte)
PP
(Page
Program)
DP
(Deep Power
Down)
RDP (Release
from Deep
Power-down)
1st 02 Hex B9 Hex AB Hex
2nd AD1
3rd AD2
4th AD3
5th
Action
to program
the selected
page
enters deep
power down
mode
release from
deep power
down mode

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
COMMAND DESCRIPTION
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE,
BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN in-
struction setting the WEL bit.
The sequence is shown as Figure 11.
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence is shown as Figure 12.
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
(3) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence is shown as Figure 13.
The denition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as de-
ned in table 2) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be
executed. Those bits dene the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be
executed)
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protec-
tion (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1
and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SRWD Status
Register
Write Protect
0 0
BP2
(the level of
protected
block)
BP1
(the level
of protected
block)
BP0
(the level
of protected
block)
WEL (write
enable latch)
WIP (write in
progress bit)
1= status
register write
disable
0 0 (note 1) (note 1) (note 1)
1=write
enable
0=not write
enable
1=write
operation
0=not in write
operation
Note:
1. See the table "Protected Area Sizes".

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
(4) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP2, BP1, BP0) bits to dene the protected
area of memory (as shown in table 2). The WRSR also can set or reset the Status Register Write Disable (SRWD)
bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hard-
ware Protected Mode (HPM) is entered.
The sequence is shown as Figure 14.
The WRSR instruction has no effect on b6, b5, b1, b0 of the status register.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 4. Protection Modes
Note:
1. As dened by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change
the values of SRWD, BP2, BP1, BP0. The protected area, which is dened by BP2, BP1, BP0, is at software
protected mode (SPM).
- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP2, BP1, BP0. The protected area, which is dened by BP2, BP1, BP0, is at software protected mode
(SPM).
Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected
mode (HPM). The data of the protected area is protected by software protected mode by BP2, BP1, BP0 and
hardware protected mode by the WP# to against data modication.
Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered.
If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP2, BP1, BP0.
Mode Status register condition WP# and SRWD bit status Memory
Software protection
mode (SPM)
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP2-BP0
bits can be changed
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
Hardware protection
mode (HPM)
The SRWD, BP2-BP0 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area
cannot
be program or erase.

16
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
(5) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The rst address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence is shown as Figure 15.
(6) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The rst address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence is shown as Figure 16.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
(7) Dual Output Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits(interleave on 1I/2O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The rst address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc-
tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence is shown as Figure 17.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
The DREAD only perform read operation. Program/Erase /Read ID/Read status....operation do not support DREAD
throughputs.
(8) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) in-
struction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address
of the sector (see table 1) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the
byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
Address bits [Am-A12] (Am is the most signicant address) select the sector address.

17
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
The sequence is shown as Figure 18.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(9) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) in-
struction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address
of the block (see table 1) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the
byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
The sequence is shown as Figure 19.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.
(10) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the
sector (see table 1) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte
boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex-
ecuted.
The sequence is shown as Figure 20.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip
is protected by BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed
when BP2, BP1, BP0 all set to "0".
(11) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. The last address byte (the 8 least signicant address
bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed
page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected
page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page
and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be
programmed at the request address of the page. There will be no effort on the other data bytes of the same page.

18
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
(12) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-
ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-
tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence is shown as Figure 22.
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power-
down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specied in Table 7.Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Denitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng,
please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed,
only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/
write cycle in progress.
The sequence is shown as Figure 23 and Figure 24.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
The sequence is shown as Figure 21.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be ex-
ecuted.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.

19
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
The RDP instruction is for releasing from Deep Power Down Mode.
(14) Read Identication (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix
Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the rst-byte device ID, and the individual device ID of
second-byte ID is as followings: 13(hex) for MX25L4006E.
The sequence is shown as Figure 25.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
(15) Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the
JEDEC assigned manufacturer ID and the specic device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initi-
ated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes ad-
dress (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling
edge of SCLK with most signicant bit (MSB) rst as shown in Figure 26. The Device ID values are listed in Table 5.
ID Denitions. If the one-byte address is initially set to 01h, then the device ID will be read rst and then followed by
the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other.
The instruction is completed by driving CS# high.
Table 5. ID Denitions
Command Type MX25L4006E
RDID Command manufacturer ID memory type memory density
C2 20 13
RES Command electronic ID
12
REMS Command manufacturer ID device ID
C2 12

20
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
(16) Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial ash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address
bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#
to high at any time during data out.
SFDP is a JEDEC Standard, JESD216.
Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
23
21 3456789 10 28 29 30 31
22 21 3210
High-Z
24 BIT ADDRESS
0
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Cycle
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
SCLK
SI
CS#
SO
SCLK
SI
CS#
SO
5Ah
Command