Macronix MX25L4006E User manual

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
MX25L4006E
3V, 4M-BIT [x 1/x 2]
CMOS SERIAL FLASH MEMORY
Key Features
• Hold Feature
• Low Power Consumption
• Auto Erase and Auto Program Algorithms
• Provides sequential read operation on whole chip

2
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
Contents
FEATURES .................................................................................................................................................................. 4
GENERAL DESCRIPTION ......................................................................................................................................... 5
PIN CONFIGURATIONS .............................................................................................................................................. 5
PIN DESCRIPTION...................................................................................................................................................... 5
BLOCK DIAGRAM....................................................................................................................................................... 6
MEMORY ORGANIZATION ......................................................................................................................................... 7
Table 1. Memory Organization ............................................................................................................................. 7
DEVICE OPERATION .................................................................................................................................................. 8
Figure 1. Serial Peripheral Interface Modes Supported ....................................................................................... 8
DATA PROTECTION.................................................................................................................................................... 9
Table 2. Protected Area Sizes .............................................................................................................................. 9
HOLD FEATURE........................................................................................................................................................ 10
Figure 2. Hold Condition Operation ........................................................................................................ 10
Table 3. Command Denition ............................................................................................................................. 12
COMMAND DESCRIPTION....................................................................................................................................... 13
(1) Write Enable (WREN) ................................................................................................................................... 13
(2) Write Disable (WRDI).................................................................................................................................... 13
(3) Read Status Register (RDSR) ...................................................................................................................... 14
(4) Write Status Register (WRSR)...................................................................................................................... 15
Table 4. Protection Modes.................................................................................................................................. 15
(5) Read Data Bytes (READ) ............................................................................................................................. 16
(6) Read Data Bytes at Higher Speed (FAST_READ) ....................................................................................... 16
(7) Dual Output Mode (DREAD)......................................................................................................................... 16
(8) Sector Erase (SE) ......................................................................................................................................... 16
(9) Block Erase (BE)........................................................................................................................................... 17
(10) Chip Erase (CE).......................................................................................................................................... 17
(11) Page Program (PP)..................................................................................................................................... 17
(12) Deep Power-down (DP) .............................................................................................................................. 18
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ............................................. 18
(14) Read Identication (RDID) .......................................................................................................................... 19
(15) Read Electronic Manufacturer ID & Device ID (REMS) .............................................................................. 19
Table 5. ID Denitions ........................................................................................................................................ 19
(16) Read SFDP Mode (RDSFDP)..................................................................................................................... 20
Read Serial Flash Discoverable Parameter (RDSFDP) Sequence.................................................................... 20
Table 6. Signature and Parameter Identication Data Values ........................................................................... 21
Table 7. Parameter Table (0): JEDEC Flash Parameter Tables ......................................................................... 22
Table 8. Parameter Table (1): Macronix Flash Parameter Tables ...................................................................... 24
POWER-ON STATE ................................................................................................................................................... 26
ELECTRICAL SPECIFICATIONS.............................................................................................................................. 27
Absolute Maximum Ratings................................................................................................................................ 27

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
Figure 3. Maximum Negative Overshoot Waveform .......................................................................................... 27
Capacitance TA = 25°C, f = 1.0 MHz.................................................................................................................. 27
Figure 4. Maximum Positive Overshoot Waveform ............................................................................................ 27
Figure 5. Input Test Waveforms and Measurement Level.................................................................................. 28
Figure 6. Output Loading.................................................................................................................................... 28
Table 9. DC Characteristics (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V) ........................................... 29
Table 10. AC Characteristics (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V) .......................................... 30
Table 11. Power-Up Timing ................................................................................................................................ 31
Timing Analysis ........................................................................................................................................................ 32
Figure 7. Serial Input Timing .............................................................................................................................. 32
Figure 8. Output Timing...................................................................................................................................... 32
Figure 9. Hold Timing ......................................................................................................................................... 33
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 ............................................... 33
Figure 11. Write Enable (WREN) Sequence (Command 06) ............................................................................. 34
Figure 12. Write Disable (WRDI) Sequence (Command 04).............................................................................. 34
Figure 13. Read Status Register (RDSR) Sequence (Command 05) ................................................................ 34
Figure 14. Write Status Register (WRSR) Sequence (Command 01)............................................................... 35
Figure 15. Read Data Bytes (READ) Sequence (Command 03) ...................................................................... 35
Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................... 36
Figure 17. Dual Output Read Mode Sequence (Command 3B)......................................................................... 36
Figure 18. Sector Erase (SE) Sequence (Command 20) .................................................................................. 37
Figure 19. Block Erase (BE) Sequence (Command 52 or D8).......................................................................... 37
Figure 20. Chip Erase (CE) Sequence (Command 60 or C7) ........................................................................... 37
Figure 21. Page Program (PP) Sequence (Command 02)................................................................................ 38
Figure 22. Deep Power-down (DP) Sequence (Command B9)......................................................................... 38
Figure 23. Read Electronic Signature (RES) Sequence (Command AB).......................................................... 39
Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB) ............................................... 39
Figure 25. Read Identication (RDID) Sequence (Command 9F)...................................................................... 40
Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90).............................. 40
Figure 27. Power-up Timing ............................................................................................................................... 41
OPERATING CONDITIONS....................................................................................................................................... 42
Figure 28. AC Timing at Device Power-Up......................................................................................................... 42
Figure 29. Power-Down Sequence .................................................................................................................... 43
ERASE AND PROGRAMMING PERFORMANCE .................................................................................................... 44
DATA RETENTION ................................................................................................................................................... 44
LATCH-UP CHARACTERISTICS .............................................................................................................................. 44
ORDERING INFORMATION ...................................................................................................................................... 45
PART NAME DESCRIPTION..................................................................................................................................... 46
PACKAGE INFORMATION........................................................................................................................................ 47
REVISION HISTORY ................................................................................................................................................. 52

4
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
4M-BIT [x 1/x 2] CMOS SERIAL FLASH
FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• 4,194,304 x 1 bit structure or 2,097,152 x 2 bits (Dual Output mode) structure
• 128 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 8 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 86MHz serial clock
- Serial clock of Dual Output mode: 80MHz
- Fast program time: 0.6ms(typ.) and 3ms(max.)/page (256-byte per page)
- Byte program time: 9us (typ.)
- Fast erase time: 40ms(typ.)/sector (4K-byte per sector) ; 0.4s(typ.)/block (64K-byte per block)
• Low Power Consumption
- Low active read current: 12mA(max.) at 86MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (typ.)
- Low active sector erase current: 9mA (typ.)
- Low standby current: 15uA (typ.)
- Deep power-down mode 2uA (typ.)
• Minimum 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP2 status bit denes the size of the area to be software protected against Program and Erase in-
structions
• Auto Erase and Auto Program Algorithms
-
Automatically erases and veries data at selected sector
-
Automatically programs and veries data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state rst)
• Status Register Feature
• Electronic Identication
- JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• PACKAGE
- 8-pin SOP (150mil)
-
8-pin SOP (200mil)
- 8-pin PDIP (300mil)
- 8-land WSON (6x5mm, 0.8mm package height)
- 8-land USON (2x3x0.6mm)
-
All devices are RoHS Compliant and Halogen-free

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
GENERAL DESCRIPTION
The device features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data output (SO), and a chip select (CS#).
Serial access to the device is enabled by CS# input.
When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.
The device provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
ed page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or
word basis for erase command is executes on sector, or block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000
program and erase cycles.
PIN CONFIGURATIONS
SYMBOL DESCRIPTION
CS# Chip Select
SI/SIO0 Serial Data Input (for 1 x I/O) / Serial Data
Input & Output (for Dual Output mode)
SO/SIO1 Serial Data Output (for 1 x I/O) / Serial
Data Output (for Dual Output mode)
SCLK Clock Input
WP# Write Protection
HOLD# Hold, to pause the device without
deselecting the device
VCC + 3.3V Power Supply
GND Ground
PIN DESCRIPTION
8-PIN SOP (150/200mil)
8-LAND, WSON (6x5mm)
8-PIN PDIP (300mil)
1
2
3
4
CS#
SO/SIO1
WP#
GND
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
1
2
3
4
CS#
SO/SIO1
WP#
GND
VCC
HOLD#
SCLK
SI/SIO0
8
7
6
5
8-LAND USON (2x3mm)
1
2
3
4
CS#
SO/SIO1
WP#
GND
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
1
2
3
4
CS#
SO/SIO1
WP#
GND
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Y-Decoder
X-Decoder
Data
Register
SRAM
Buffer
SI/SIO0
SCLK Clock Generator
State
Machine
Mode
Logic
Sense
Amplifier
HV
Generator
Output
Buffer
SO/SIO1
CS#,
WP#,
HOLD#

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
Table 1. Memory Organization
Block Sector Address Range
7
127 07F000h 07FFFFh
:::
112 070000h 070FFFh
6
111 06F000h 06FFFFh
:::
96 060000h 060FFFh
5
95 05F000h 05FFFFh
:::
80 050000h 050FFFh
4
79 04F000h 04FFFFh
:::
64 040000h 040FFFh
3
63 03F000h 03FFFFh
:::
48 030000h 030FFFh
2
47 02F000h 02FFFFh
:::
32 020000h 020FFFh
1
31 01F000h 01FFFFh
:::
16 010000h 010FFFh
0
15 00F000h 00FFFFh
:::
3 003000h 003FFFh
2 002000h 002FFFh
1 001000h 001FFFh
0 000000h 000FFFh
MEMORY ORGANIZATION

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. The CS# falling time needs to
follow tCHCL spec.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge. The CS# rising time needs to follow tCLCH spec.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of serial peripheral interface mode 0 and mode 3 is shown as Figure 1.
5. For the following instructions: RDID, RDSR, READ, FAST_READ, RDSFDP, DREAD, RES and REMS the shift-
ed-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS#
can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must
go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Peripheral Interface Modes Supported
SCLK
MSB
CPHA
SI
0
1
CPOL
0(Serial mode 0)
(Serial mode 3) 1
SO
SCLK
MSB
shift in shift out
Note:
CPOL indicates clock polarity of serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which serial mode is
supported.

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specic command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Deep Power Down Mode: By entering deep power down mode, the ash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-
nature command (RES).
I. Block lock protection
- Software Protection Mode (SPM): by using BP0-BP2 bits to set the part of Flash protected from data change.
- Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP2 bits and SRWD bit from
data change.
Table 2. Protected Area Sizes
Status bit Protect level 4Mb
BP2 BP1 BP0
0 0 0 0 (none) None
0 0 1 1 (1 block) Block 7
0 1 0 2 (2 blocks) Block 6-7
0 1 1 3 (4 blocks) Block 4-7
1 0 0 4 (8 blocks) All
1 0 1 5 (All) All
1 1 0 6 (All) All
1 1 1 7 (All) All

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P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start
until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial
Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial
Clock being low).
Figure 2. Hold Condition Operation
Valid Data Valid Data Valid DataDon’t care
High_Z High_Z
Don’t care
Bit 7 Bit 6 Bit 5
Bit 5
Bit 7
Bit 7 Bit 6
Bit 6
HOLD#
CS#
SCLK
SI/SIO0
SO/SIO1
(internal)
SO/SIO1
(External)
≈ ≈ ≈ ≈ ≈ ≈ ≈≈
Valid Data Valid Data Valid DataDon’t care
High_Z High_Z
Don’t care
Bit 7 Bit 6 Bit 5 Bit 3Bit 4
Bit 7 Bit 6 Bit 4
Bit 5 Bit 3
HOLD#
CS#
SCLK
SI/SIO0
SO/SIO1
(internal)
SO/SIO1
(External)
≈ ≈ ≈ ≈ ≈ ≈ ≈≈