Marvell Alaska Ultra 88E1111 Reference guide

Marvell. Moving Forward Faster
Doc. No. MV-S105540-00, Rev. --
March 4, 2009
Document Classification: Proprietary Information
88E1111 Product Brief
Integrated 10/100/1000 Ultra
Gigabit Ethernet Transceiver

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Copyright © 2009. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas,
Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell.
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88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Doc. No. MV-S105540-00 Rev. -- Copyright © 2009 Marvell
Page 2 Document Classification: Proprietary Information March 4, 2009, Advance

88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Document Classification: Proprietary Information Page 3
OVERVIEW
The Alaska®Ultra 88E1111 Gigabit Ethernet Trans-
ceiver is a physical layer device for Ethernet
1000BASE-T, 100BASE-TX, and 10BASE-T applica-
tions. It is manufactured using standard digital CMOS
process and contains all the active circuitry required to
implement the physical layer functions to transmit and
receive data on standard CAT 5 unshielded twisted pair.
The 88E1111 device incorporates the Marvell Virtual
Cable Tester®(VCT™) feature, which uses Time
Domain Reflectometry (TDR) technology for the remote
identification of potential cable malfunctions, thus
reducing equipment returns and service calls. Using
VCT, the Alaska 88E1111 device detects and reports
potential cabling issues such as pair swaps, pair polar-
ity and excessive pair skew. The device will also detect
cable opens, shorts or any impedance mismatch in the
cable and report accurately within one meter the dis-
tance to the fault.
The 88E1111 device supports the Gigabit Media Inde-
pendent Interface (GMII), Reduced GMII (RGMII),
Serial Gigabit Media Independent Interface (SGMII),
the Ten-Bit Interface (TBI), and Reduced TBI (RTBI) for
direct connection to a MAC/Switch port.
The 88E1111 device incorporates an optional 1.25 GHz
SERDES (Serializer/Deserializer). The serial interface
may be connected directly to a fiber-optic transceiver
for 1000BASE-T/1000BASE-X media conversion appli-
cations. Additionally, the 88E1111 device may be used
to implement 1000BASE-T Gigabit Interface Converter
(GBIC) or Small Form Factor Pluggable (SFP) modules.
The 88E1111 device uses advanced mixed-signal pro-
cessing to perform equalization, echo and crosstalk
cancellation, data recovery, and error correction at a
gigabit per second data rate. The device achieves
robust performance in noisy environments with very low
power dissipation.
The 88E1111 device is offered in three different pack-
age options including a 117-Pin TFBGA, a 96-pin BCC
featuring a body size of only 9 x 9 mm, and a 128 PQFP
package.
FEATURES
•10/100/1000BASE-T IEEE 802.3 compliant
•Supports GMII, TBI, reduced pin count GMII
(RGMII), reduced pin count TBI (RTBI), and serial
GMII (SGMII) interfaces
•Integrated 1.25 GHz SERDES for 1000BASE-X
fiber applications
•Four RGMII timing modes
•Energy Detect and Energy Detect+ low power
modes
•Three loopback modes for diagnostics
•“Downshift” mode for two-pair cable installations
•Fully integrated digital adaptive equalizers, echo
cancellers, and crosstalk cancellers
•Advanced digital baseline wander correction
•Automatic MDI/MDIX crossover at all speeds of
operation
•Automatic polarity correction
•IEEE 802.3u compliant Auto-Negotiation
•Software programmable LED modes including LED
testing
•Automatic detection of fiber or copper operation
•Supports IEEE 1149.1 JTAG
•Two-Wire Serial Interface (TWSI) and MDC/MDIO
•CRC checker, packet counter
•Packet generation
•Virtual Cable Tester (VCT)
•Auto-Calibration for MAC Interface outputs
•Requires only two supplies: 2.5V and 1.0V (with
1.2V option for the 1.0V supply)
•I/Os are 3.3V tolerant
•Low power dissipation Pave = 0.75W
•117-Pin TFBGA, 96-Pin BCC, and 128 PQFP
package options
•117-Pin TFBGA and 96-Pin BCC packages avail-
able in Commercial or Industrial grade
•RoHS 6/6 compliant packages available

88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Doc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell
Page 4 Document Classification: Proprietary Information March 4, 2009, Advance
88E1111 Device used in Copper Application
88E1111 Device used in Fiber Application
88E1111 RGMII/GMII MAC to SGMII MAC Conversion
M
a
g
n
e
t
i
c
s
MAC Interface Options
- GMII/MII
- TBI
- RGMII
- RTBI
- SGMII
- Serial Interface
Media Types:
- 10BASE-T
- 100BASE-TX
- 1000BASE-T
RJ-45
10/100/1000 Mbps
Ethernet MAC
88E1111
Device
Serial
Interface
MAC Interface Options
- GMII/MII
- RGMII
Media Types:
- 1000BASE-X
Fiber
Optics
10/100/1000 Mbps
Ethernet MAC
88E1111
Device
Serial Interface
- 4-pin SGMIII
MAC Interface Options
- GMII
- RGMII
3-Speed
SFP
Gigabit Ethernet
MAC
88E1111
Device
(Effective SGMII MAC)

Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Document Classification: Proprietary Information Page 5
Table of Contents
1.1 117-Pin TFBGA Package................................................................................................6
1.2 96-Pin BCC Package .....................................................................................................7
1.3 128-Pin PQFP Package ..................................................................................................8
1.4 Pin Description ...............................................................................................................9
1.4.1 Pin Type Definitions............................................................................................................ 9
1.5 I/O State at Various Test or Reset Modes ..................................................................33
1.6 117-Pin TFBGA Pin Assignment List - Alphabetical by Signal Name .....................34
1.7 96-Pin BCC Pin Assignment List - Alphabetical by Signal Name............................ 36
1.8 128-Pin PQFP Pin Assignment List - Alphabetical by Signal Name........................38
2.1 117-pin TFBGA Package..............................................................................................40
2.2 96-pin BCC Package - Top View .................................................................................42
2.3 96-Pin BCC Package - Bottom View ...........................................................................43
2.4 128-Pin PQFP Package ................................................................................................ 44
3.1 Ordering Part Numbers and Package Markings........................................................45
3.1.1 RoHS 5/6 Compliant Marking Examples .......................................................................... 46
3.1.2 RoHS 6/6 Compliant Marking Examples .......................................................................... 49

88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Doc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell
Page 6 Document Classification: Proprietary Information March 4, 2009, Advance
Section 1. Signal Description
The 88E1111 device is a 10/100/1000BASE-T/1000BASE-X Gigabit Ethernet transceiver.
1.1 117-Pin TFBGA Package
Figure 1: 88E1111 Device 117-Pin TFBGA Package (Top View)
Figure 2: Pin A1 Location
123456789
A RXD5 RXD6 S_IN+ S_IN- S_CLK+ S_CLK- S_OUT+ S_OUT- LED_
LINK1000 A
B RX_DV RXD0 RXD3 VDDO CRS COL AVDD LED_
LINK100 VDDOH B
C RX_CLK VDDO RXD2 RXD4 RXD7 DVDD DVDD LED_
LINK10 LED_RX C
D TX_CLK RX_ER RXD1 VSS VSS VSS DVDD CONFIG[0] LED_TX D
E TX_EN GTX_CLK DVDD VSS VSS VSS DVDD LED_
DUPLEX CONFIG[1] E
F TXD0 TX_ER DVDD VSS VSS VSS VDDOH CONFIG[2] CONFIG[4] F
G NC TXD1 TXD2 VSS VSS VSS CONFIG[3] CONFIG[6] CONFIG[5] G
H TXD4 TXD3 TXD5 VSS VSS VSS VSSC SEL_
FREQ XTAL1 H
J TXD6 TXD7 DVDD VSS VSS VSS DVDD VDDOH XTAL2 J
K VDDO 125CLK RESETn VSS VSS VSS NC TDO VDDOX K
L INTn VDDOX MDC COMA VSS VSS TDI TMS TCK L
M MDIO RSET AVDD AVDD HSDAC+ HSDAC- AVDD AVDD TRSTn M
N MDI[0]+ MDI[0]- MDI[1]+ MDI[1]- AVDD MDI[2]+ MDI[2]- MDI[3]+ MDI[3]- N
123456789
Pin A1 location
88E1111-BAB

Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Document Classification: Proprietary Information Page 7
Signal Description
96-Pin BCC Package
1.2 96-Pin BCC Package
Figure 3: 88E1111 Device 96-Pin BCC Package (Top View)
RX_CLK
RX_ER
TX_CLK
VDDO
DVDD
TX_ER
GTX_CLK
TX_EN
DVDD
TXD0
TXD1
NC
TXD2
DVDD
TXD3
TXD4
TXD5
TXD6
MDIO
INTn
VDDO
TXD7
125CLK
VDDOX
MDC
COMA
RESETn
MDI[0]+
RSET
MDI[0]-
AVDD
MDI[1]+
MDI[1]-
AVDD
AVDD
HSDAC+
HSDAC-
MDI[2]+
AVDD
MDI[2]-
MDI[3]+
MDI[3]-
TDI
AVDD
TMS
TRSTn
VDDOX
TCK
TDO
VDDOH
VSSC
XTAL2
XTAL1
SEL_
FREQ
DVDD
CONFIG[6]
CONFIG[5]
CONFIG[4]
CONFIG[3]
DVDD
CONFIG[2]
CONFIG[1]
CONFIG[0]
VDDOH
DVDD
LED_TX
LED_RX
LED_DUPL
EX
DVDD
VDDOH
LED_LINK
1000
VDDO
RXD0
RX_DV
RXD2
RXD1
RXD3
RXD4
RXD5
RXD6
DVDD
COL
S_IN-
S_CLK+
S_OUT+
S_OUT-
LED_LINK
100
VDDO
RXD7
CRS
S_IN+
S_CLK-
AVDD
LED_LINK
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 24
25
26
27
28
29
30
31
32
33
34
35
36
38
40
37
39
42
44
46
48
41
43
45
47
49
50 51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
DVDD
88E1111 - CAA
0VSS

88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Doc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell
Page 8 Document Classification: Proprietary Information March 4, 2009, Advance
1.3 128-Pin PQFP Package
Figure 4: 88E1111 Device 128-Pin PQFP Package (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
88E1111 - RCJ
Top View
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64VSS
AVDD
VSS
S_OUT+
VSS
S_CLK-
S_CLK+
VSS
S_IN-
S_IN+
COL
CRS
VSS
DVDD
DVDD
VSS
RXD7
RXD6
VDDO
RXD5
RXD4
RXD3
RXD2
VSS
RXD1
AVDD
VSS
MDI[3]-
MDI[3]+
VSS
AVDD
VSS
MDI[2]-
MDI[2]+
VSS
HSDAC-
HSDAC+
AVDD
VSS
NC
AVDD
VSS
MDI[1]-
MDI[1]+
VSS
AVDD
VSS
MDI[0]-
MDI[0]+
VSS
RSET
VSS VSS LED_LINK10 LED_LINK100 LED_LINK1000 VDDOH DVDD LED_DUPLEX VSS VSS LED_RX LED_TX DVDD VDDOH CONFIG[0] CONFIG[1] CONFIG[2] DVDD VSS VSS CONFIG[3] CONFIG[4] CONFIG[5] CONFIG[6] DVDD SEL_FREQ XTAL1 XTAL2 VSSC VDDOH TDO VDDOX TCK TMS TRSTn TDI VSS VSS
VSS
DVDD
RXD0
RX_DV
VDDO
DVDD
RX_CLK
RX_ER
VSS
TX_CLK
VDDO
DVDD
TX_ER
GTX_CLK
VSS
TX_EN
DVDD
TXD0 TXD1 TXD2
VSS VSS
DVDD
TXD3 TXD4 TXD5
DVDD
TXD6 TXD7
VDDO
125CLK
INTn
MDIO
VDDOX
MDC
RESETn
COMA
VSS
S_OUT-

Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Document Classification: Proprietary Information Page 9
Signal Description
Pin Description
1.4 Pin Description
1.4.1 Pin Type Definitions
Pin Type Definition
H Input with hysteresis
I/O Input and output
I Input only
O Output only
PU Internal pull up
PD Internal pull down
D Open drain output
Z Tri-state output
mA DC sink capability

88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Doc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell
Page 10 Document Classification: Proprietary Information March 4, 2009, Advance
Table 1: Media Dependent Interface
117-TFBGA
Pin #
96-BCC
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description
N1
N2
29
31
41
42
MDI[0]+
MDI[0]-
I/O, D Media Dependent Interface[0].
In 1000BASE-T mode in MDI configuration,
MDI[0]± correspond to BI_DA±.
In MDIX configuration, MDI[0]± correspond
to BI_DB±.
In 100BASE-TX and 10BASE-T modes in
MDI configuration, MDI[0]± are used for the
transmit pair. In MDIX configuration,
MDI[0]± are used for the receive pair.
MDI[0]± should be tied to ground if not used.
N3
N4
33
34
46
47
MDI[1]+
MDI[1]-
I/O, D Media Dependent Interface[1].
In 1000BASE-T mode in MDI configuration,
MDI[1]± correspond to BI_DB±.
In MDIX configuration, MDI[1]± correspond
to BI_DA±.
In 100BASE-TX and 10BASE-T modes in
MDI configuration, MDI[1]± are used for the
receive pair. In MDIX configuration, MDI[1]±
are used for the transmit pair.
MDI[1]± should be tied to ground if not used.

Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Document Classification: Proprietary Information Page 11
Signal Description
Pin Description
N6
N7
39
41
56
57
MDI[2]+
MDI[2]-
I/O, D Media Dependent Interface[2].
In 1000BASE-T mode in MDI configuration,
MDI[2]± correspond to BI_DC±.
In MDIX configuration, MDI[2]± corresponds
to BI_DD±.
In 100BASE-TX and 10BASE-T modes,
MDI[2]± are not used.
MDI[2]± should be tied to ground if not used.
N8
N9
42
43
61
62
MDI[3]+
MDI[3]-
I/O, D Media Dependent Interface[3].
In 1000BASE-T mode in MDI configuration,
MDI[3]± correspond to BI_DD±.
In MDIX configuration, MDI[3]± correspond
to BI_DC±.
In 100BASE-TX and 10BASE-T modes,
MDI[3]± are not used.
MDI[3]± should be tied to ground if not used.
Table 1: Media Dependent Interface (Continued)
117-TFBGA
Pin #
96-BCC
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description

88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Doc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell
Page 12 Document Classification: Proprietary Information March 4, 2009, Advance
The GMII interface supports both 1000BASE-T and 1000BASE-X modes of operation. The GMII interface pins are
also used for the TBI interface. See Ta bl e 3 for TBI pin definitions. The MAC interface pins are 3.3V tolerant.
Table 2: GMII/MII Interfaces
117-TFBGA
Pin #
96-BCC
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description
E2 8 14 GTX_CLK I GMII Transmit Clock. GTX_CLK provides a
125 MHz clock reference for TX_EN,
TX_ER, and TXD[7:0]. This clock can be
stopped when the device is in 10/100BASE-
T modes, and also during Auto-Negotiation.
D1 4 10 TX_CLK O, Z MII Transmit Clock. TX_CLK provides a 25
MHz clock reference for TX_EN, TX_ER,
and TXD[3:0] in 100BASE-TX mode, and a
2.5 MHz clock reference in 10BASE-T
mode.
TX_CLK provides a 25 MHz, 2.5 MHz, or 0
MHz clock during 1000 Mbps Good Link,
Auto-Negotiation, and Link Lost states
depending on the setting of register 20.6:4.
The 2.5 MHz clock is the default rate, which
may be programmed to another frequency
by writing to register 20.6:4.
E1 9 16 TX_EN I GMII and MII Transmit Enable. In GMII/MII
mode when TX_EN is asserted, data on
TXD[7:0] along with TX_ER is encoded and
transmitted onto the cable.
TX_EN is synchronous to GTX_CLK, and
synchronous to TX_CLK in 100BASE-TX
and 10BASE-T modes.
F2 7 13 TX_ER I GMII and MII Transmit Error. In GMII/MII
mode when TX_ER and TX_EN are both
asserted, the transmit error symbol is trans-
mitted onto the cable. When TX_ER is
asserted with TX_EN de-asserted, carrier
extension symbol is transmitted onto the
cable.
TX_ER is synchronous to GTX_CLK, and
synchronous to TX_CLK in 100BASE-TX
and 10BASE-T modes.

Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Document Classification: Proprietary Information Page 13
Signal Description
Pin Description
J2
J1
H3
H1
H2
G3
G2
F1
20
19
18
17
16
14
12
11
29
28
26
25
24
20
19
18
TXD[7]
TXD[6]
TXD[5]
TXD[4]
TXD[3]/TXD[3]
TXD[2]/TXD[2]
TXD[1]/TXD[1]
TXD[0]/TXD[0]
I GMII and MII Transmit Data. In GMII mode,
TXD[7:0] present the data byte to be trans-
mitted onto the cable in 1000BASE-T mode.
In MII mode, TXD[3:0] present the data nib-
ble to be transmitted onto the cable in
100BASE-TX and 10BASE-T modes.
TXD[7:4] are ignored in these modes, but
should be driven either high or low. These
pins must not float.
TXD[7:0] are synchronous to GTX_CLK, and
synchronous to TX_CLK in 100BASE-TX
and 10BASE-T modes.
Inputs TXD[7:4] should be tied low if not
used (e.g., RGMII mode).
C1 2 7 RX_CLK O, Z GMII and MII Receive Clock. RX_CLK pro-
vides a 125 MHz clock reference for RX_DV,
RX_ER, and RXD[7:0] in 1000BASE-T
mode, a 25 MHz clock reference in
100BASE-TX mode, and a 2.5 MHz clock
reference in 10BASE-T mode.
TX_TCLK comes from the RX_CLK pins
used in jitter testing. Refer to Register 9 for
jitter test modes.
B1 94 4 RX_DV O, Z GMII and MII Receive Data Valid. When
RX_DV is asserted, data received on the
cable is decoded and presented on
RXD[7:0] and RX_ER.
RX_DV is synchronous to RX_CLK.
D2 3 8 RX_ER O, Z GMII and MII Receive Error. When RX_ER
and RX_DV are both asserted, the signals
indicate an error symbol is detected on the
cable.
When RX_ER is asserted with RX_DV de-
asserted, a false carrier or carrier extension
symbol is detected on the cable.
RX_ER is synchronous to RX_CLK.
Table 2: GMII/MII Interfaces (Continued)
117-TFBGA
Pin #
96-BCC
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description

88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Doc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell
Page 14 Document Classification: Proprietary Information March 4, 2009, Advance
C5
A2
A1
C4
B3
C3
D3
B2
86
87
89
90
91
93
92
95
120
121
123
124
125
126
128
3
RXD[7]
RXD[6]
RXD[5]
RXD[4]
RXD[3]/RXD[3]
RXD[2]/RXD[2]
RXD[1]/RXD[1]
RXD[0]/RXD[0]
O, Z GMII and MII Receive Data. Symbols
received on the cable are decoded and pre-
sented on RXD[7:0] in 1000BASE-T mode.
In MII mode, RXD[3:0] are used in
100BASE-TX and 10BASE-T modes. In MII
mode, RXD[7:4] are driven low.
RXD[7:0] is synchronous to RX_CLK.
B5 84 115 CRS O, Z GMII and MII Carrier Sense. CRS asserts
when the receive medium is non-idle. In half-
duplex mode, CRS is also asserted during
transmission. CRS assertion during half-
duplex transmit can be disabled by program-
ming register 16.11 to 0.
CRS is asynchronous to RX_CLK,
GTX_CLK, and TX_CLK.
B6 83 114 COL O, Z GMII and MII Collision. In 10/100/
1000BASE-T full-duplex modes, COL is
always low. In 10/100/1000BASE-T half-
duplex modes, COL asserts only when both
the transmit and receive media are non-idle.
In 10BASE-T half-duplex mode, COL is
asserted to indicate signal quality error
(SQE). SQE can be disabled by clearing reg-
ister 16.2 to zero.
COL is asynchronous to RX_CLK,
GTX_CLK, and TX_CLK.
Table 2: GMII/MII Interfaces (Continued)
117-TFBGA
Pin #
96-BCC
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description

Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Document Classification: Proprietary Information Page 15
Signal Description
Pin Description
The TBI interface supports 1000BASE-T mode of operation. The TBI interface uses the same pins as the GMII
interface. The MAC interface pins are 3.3V tolerant.
Table 3: TBI Interface
117-TFBGA
Pin #
96-BCC
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description
E2 8 14 GTX_CLK/
TBI_TXCLK
I TBI Transmit Clock. In TBI mode, GTX_CLK
is used as TBI_TXCLK. TBI_TXCLK is a 125
MHz transmit clock.
TBI_TXCLK provides a 125 MHz clock refer-
ence for TX_EN, TX_ER, and TXD[7:0].
D1 4 10 TX_CLK/RCLK1 O, Z TBI 62.5 MHz Receive Clock- even code
group. In TBI mode, TX_CLK is used as
RCLK1.
J2
J1
H3
H1
H2
G3
G2
F1
20
19
18
17
16
14
12
11
29
28
26
25
24
20
19
18
TXD[7]
TXD[6]
TXD[5]
TXD[4]
TXD[3]
TXD[2]
TXD[1]
TXD[0]
I TBI Transmit Data. TXD[7:0] presents the
data byte to be transmitted onto the cable.
TXD[9:0] are synchronous to GTX_CLK.
Inputs TXD[7:4] should be tied low if not
used (e.g., RTBI mode).
E1 9 16 TX_EN/
TXD8
I TBI Transmit Data. In TBI mode, TX_EN is
used as TXD8.
TXD[9:0] are synchronous to GTX_CLK.
F2 7 13 TX_ER/
TXD9
I TBI Transmit Data. In TBI mode, TX_ER is
used as TXD9.
TXD[9:0] are synchronous to GTX_CLK.
TX_ER should be tied low if not used (e.g.,
RTBI mode).
C1 2 7 RX_CLK/
RCLK0
O, Z TBI 62.5 MHz Receive Clock- odd code
group. In the TBI mode, RX_CLK is used
as RCLK0.
C5
A2
A1
C4
B3
C3
D3
B2
86
87
89
90
91
93
92
95
120
121
123
124
125
126
128
3
RXD[7]
RXD[6]
RXD[5]
RXD[4]
RXD[3]
RXD[2]
RXD[1]
RXD[0]
O, Z TBI Receive Data code group [7:0]. In the
TBI mode, RXD[7:0] present the data byte to
be transmitted to the MAC. Symbols
received on the cable are decoded and pre-
sented on RXD[7:0].
RXD[7:0] are synchronous to RCLK0 and
RCLK1.
B1 94 4 RX_DV/
RXD8
O, Z TBI Receive Data code group bit 8. In the
TBI mode, RX_DV is used as RXD8.
RXD[9:0] are synchronous to RCLK0 and
RCLK1.

88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Doc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell
Page 16 Document Classification: Proprietary Information March 4, 2009, Advance
D2 3 8 RX_ER/
RXD9
O, Z TBI Receive Data code group bit 9. In the
TBI mode, RX_ER is used as RXD9.
RXD[9:0] are synchronous to RCLK0 and
RCLK1.
B5 84 115 CRS/
COMMA
O, Z TBI Valid Comma Detect. In the TBI mode,
CRS is used as COMMA.
B6 83 114 COL/LPBK I TBI Mode Loopback. In the TBI mode, COL
is used to indicate loopback on the TBI.
When a “0 - 1" transition is sampled on this
pin, bit 0.14 is set to 1.
When a “1 - 0" is sampled on this pin, bit
0.14 is reset to 0.
If this feature is not used, the COL pin
should be driven low on the board. This pin
should not be left floating in TBI mode.
Table 3: TBI Interface (Continued)
117-TFBGA
Pin #
96-BCC
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description

Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Document Classification: Proprietary Information Page 17
Signal Description
Pin Description
The RGMII interface supports 10/100/1000BASE-T and 1000BASE-X modes of operation.The RGMII interface
pins are also used for the RTBI interface. See Tab l e 5 for RTBI pin definitions. The MAC interface pins are 3.3V
tolerant.
Table 4: RGMII Interface
117-TFBGA
Pin #
96-BCC
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description
E2 8 14 GTX_CLK/
TXC
I RGMII Transmit Clock provides a 125 MHz,
25 MHz, or 2.5 MHz reference clock with ±
50 ppm tolerance depending on speed. In
RGMII mode, GTX_CLK is used as TXC.
H2
G3
G2
F1
16
14
12
11
24
20
19
18
TXD[3]/TD[3]
TXD[2]/TD[2]
TXD[1]/TD[1]
TXD[0]/TD[0]
I RGMII Transmit Data. In RGMII mode,
TXD[3:0] are used as TD[3:0].
In RGMII mode, TXD[3:0] run at double data
rate with bits [3:0] presented on the rising
edge of GTX_CLK, and bits [7:4] presented
on the falling edge of GTX_CLK. In this
mode, TXD[7:4] are ignored.
In RGMII 10/100BASE-T modes, the trans-
mit data nibble is presented on TXD[3:0] on
the rising edge of GTX_CLK.
E1 9 16 TX_EN/
TX_CTL
I RGMII Transmit Control. In RGMII mode,
TX_EN is used as TX_CTL. TX_EN is pre-
sented on the rising edge of GTX_CLK.
A logical derivative of TX_EN and TX_ER is
presented on the falling edge of GTX_CLK.
C1 2 7 RX_CLK/
RXC
O, Z RGMII Receive Clock provides a 125 MHz,
25 MHz, or 2.5 MHz reference clock with ±
50 ppm tolerance derived from the received
data stream depending on speed. In RGMII
mode, RX_CLK is used as RXC.
B1 94 4 RX_DV/
RX_CTL
O, Z RGMII Receive Control. In RGMII mode,
RX_DV is used as RX_CTL. RX_DV is pre-
sented on the rising edge of RX_CLK.
A logical derivative of RX_DV and RX_ER is
presented on the falling edge of RX_CLK.
B3
C3
D3
B2
91
93
92
95
125
126
128
3
RXD[3]/RD[3]
RXD[2]/RD[2]
RXD[1]/RD[1]
RXD[0]/RD[0]
O, Z RGMII Receive Data. In RGMII mode,
RXD[3:0] are used as RD[3:0]. In RGMII
mode, RXD[3:0] run at double data rate with
bits [3:0] presented on the rising edge of
RX_CLK, and bits [7:4] presented on the fall-
ing edge of RX_CLK. In this mode, RXD[7:4]
are ignored.
In RGMII 10/100BASE-T modes, the receive
data nibble is presented on RXD[3:0] on the
rising edge of RX_CLK.
RXD[3:0] are synchronous to RX_CLK.

88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Doc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell
Page 18 Document Classification: Proprietary Information March 4, 2009, Advance
The RTBI interface supports 1000BASE-T mode of operation. The RTBI interface uses the same pins as the
RGMII interface. The MAC interface pins are 3.3V tolerant.
Table 5: RTBI Interface
117-TFBGA
Pin #
96-BCC
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description
E2 8 14 GTX_CLK/
TXC
I RGMII Transmit Clock provides a 125 MHz
reference clock with ± 50 ppm tolerance. In
RTBI mode, GTX_CLK is used as TXC.
H2
G3
G2
F1
16
14
12
11
24
20
19
18
TXD[3]/TD[3]
TXD[2]/TD[2]
TXD[1]/TD[1]
TXD[0]/TD[0]
I RTBI Transmit Data.
In RTBI mode, TXD[3:0] are used as
TD[3:0]. TD[3:0] run at double data rate with
bits [3:0] presented on the rising edge of
GTX_CLK, and bits [8:5] presented on the
falling edge of GTX_CLK. In this mode,
TXD[7:4] are ignored.
E1 9 16 TX_EN/
TD4_TD9
IRTBITransmitData.
In RTBI mode, TX_EN is used as TD4_TD9.
TD4_TD9 runs at a double data rate with bit
4 presented on the rising edge of GTX_CLK,
and bit 9 presented on the falling edge of
GTX_CLK.
C1 2 7 RX_CLK/
RXC
O, Z RTBI Receive Clock provides a 125 MHz ref-
erence clock with ± 50 ppm tolerance
derived from the received data stream. In
RTBI mode, RX_CLK is used as RXC.
B3
C3
D3
B2
91
93
92
95
125
126
128
3
RXD[3]/RD[3]
RXD[2]/RD[2]
RXD[1]/RD[1]
RXD[0]/RD[0]
O, Z RTBI Receive Data.
In RTBI mode, RXD[3:0] are used as
RD[3:0]. RD[3:0] runs at double data rate
with bits [3:0] presented on the rising edge of
RX_CLK, and bits [8:5] presented on the fall-
ing edge of RX_CLK. In this mode, RXD[7:4]
are ignored.
B1 94 4 RX_DV/
RD4_RD9
O, Z RTBI Receive Data.
In RTBI mode, RX_DV is used as
RD4_RD9. RD4_RD9 runs at a double data
rate with bit 4 presented on the rising edge
of RX_CLK, and bit 9 presented on the fall-
ing edge of RX_CLK.

Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Document Classification: Proprietary Information Page 19
Signal Description
Pin Description
Table 6: SGMII Interface
117-TFBGA
Pin #
96-BCC
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description
A3
A4
82
81
113
112
S_IN+
S_IN-
I SGMII Transmit Data. 1.25 GBaud input -
Positive and Negative.
Input impedance on the S_IN± pins may be
programmed for 50 ohm or 75 ohm imped-
ance by setting register 26.6. The input
impedance default setting is determined by
the 75/50 OHM configuration pin.
A5
A6
79
80
110
109
S_CLK+
S_CLK-
I/O SGMII 625 MHz Receive Clock.
For Serial Interface modes
(HWCFG_MODE[3:0] = 1x00) the S_CLK±
pins become Signal Detect± (SD±) inputs.
A7
A8
77
75
107
105
S_OUT+
S_OUT-
O, Z SGMII Receive Data. 1.25 GBaud output -
Positive and Negative.
Output impedance on the S_OUT± pins may
be programmed for 50 ohm or 75 ohm
impedance by setting register 26.5. Output
amplitude can be adjusted via register
26.2:0. The output impedance default setting
is determined by the 75/50 OHM configura-
tion pin.

88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Doc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell
Page 20 Document Classification: Proprietary Information March 4, 2009, Advance
Table 7: 1.25 GHz Serial High Speed Interface
117-TFBGA
Pin #
96-BCC
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description
A3
A4
82
81
113
112
S_IN+
S_IN-
I 1.25 GHz input - Positive and Negative.
When this interface is used as a MAC inter-
face, the MAC transmitter’s positive output
connects to the S_IN+. The MAC transmit-
ter’s negative output connects to the S_IN-.
When this interface is used as a fiber inter-
face, the fiber-optic transceiver’s positive
output connects to the S_IN+. The fiber-optic
transceiver’s negative output connects to the
S_IN-.
Input impedance on the S_IN± pins may be
programmed for 50 ohm or 75 ohm imped-
ance by setting register 26.6. The input
impedance default setting is determined by
the 75/50 OHM configuration pin.
A5
A6
79
80
110
109
S_CLK+/SD+
S_CLK-/SD-
I Signal Detect input.
For Serial Interface modes the S_CLK± pins
become Signal Detect± (SD±) inputs.
A7
A8
77
75
107
105
S_OUT+
S_OUT-
O, Z 1.25 GHz output −Positive and Negative.
When this interface is used as a MAC inter-
face, S_OUT+ connects to the MAC
receiver’s positive input. S_OUT- connects
to the MAC receiver’s negative input.
When this interface is used as a fiber inter-
face, S_OUT+ connects to the fiber-optic
transceiver’s positive input. S_OUT- con-
nects to the fiber-optic transceiver’s negative
input.
Output impedance on the S_OUT± pins may
be programmed for 50 ohm or 75 ohm
impedance by setting register 26.5. Output
amplitude can be adjusted via register
26.2:0. The output impedance default setting
is determined by the 75/50 OHM configura-
tion pin.
B3 91 125 RXD[3] O, Z Serial MAC interface Copper Link Status[1]
connection.
1 = Copper link up
0 = Copper link down