Marvell 88E3015 User manual

Marvell. Moving Forward Faster
Doc. No. MV-S103657-00, Rev. D
January 4, 2008
Document Classification: Proprietary Information
88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver

Document Status
Advance
Information
This document contains design specifications for initial product development. Specifications may
change without notice. Contact Marvell Field Application Engineers for more information.
Preliminary
Information
This document contains preliminary data, and a revision of this document will be published at a later
date. Specifications may change without notice. Contact Marvell Field Application Engineers for
more information.
Final
Information
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change without notice. Contact Marvell Field Application Engineers for more information.
Revision Code: Rev. D
Advance Technical Publication: 1.40
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88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Doc. No. MV-S103657-00 Rev. D Copyright © 2008 Marvell
Page 2 Document Classification: Proprietary Information January 4, 2008, Advance

88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Copyright © 2008 Marvell Doc. No. MV-S103657-00, Rev. D
January 4, 2008, Advance Document Classification: Proprietary Information Page 3
OVERVIEW
The Marvell® 88E3015/88E3018 devices are the fourth
generation Marvell®DSP-based physical layer trans-
ceivers for Fast Ethernet applications. The devices con-
tain all the active circuitry to convert data streams to
and from a Media Access Controller (MAC) and the
physical media. The 88E3015/88E3018 devices incor-
porate IEEE 802.3u Auto-Negotiation in support of both
100BASE-TX and 10BASE-T networks over twisted-
pair cable in full-duplex or half-duplex mode.
The 88E3015/88E3018 devices both support the
Reduced Gigabit Media Independent Interface (RGMII),
and the Media Independent Interface (MII).
The 88E3015/88E3018 devices feature a mode of oper-
ation supporting IEEE compliant 100BASE-FX fiber-
optic networks. Additionally, the 88E3015/88E3018
devices implement Far-End Fault Indication (FEFI) in
order to provide a mechanism for transferring informa-
tion from the local station to the link partner that indi-
cates a remote fault has occurred in 100BASE-FX
mode.
The 88E3015/88E3018 devices feature the Marvell Vir-
tual Cable Tester®(VCT™) technology, which enables
IT managers and networking equipment manufacturers
to remotely analyze the quality and characteristics of
the attached cable plant.
The 88E3015/88E3018 devices use advanced mixed-
signal processing and power management techniques
for extremely low power dissipation and high port count
system integration. The 88E3015/88E3018 devices are
manufactured in an all CMOS process.
88E3015/88E3018 SPECIFIC
FEATURES
The 88E3018 device, housed in a 64-pin QFN package,
offers a pin-upgradeable path toward future Gigabit
Ethernet PHY designs. The 88E3018 device includes
support for IEEE 1149.1 JTAG Standard Test Access
Port and Boundary Scan. The 88E3108 device is avail-
able in Industrial grade (RoHS 6/6 compliant package
only)
The 88E3015 device, housed in a 56-pin QFN package,
provides a cost-efficient, increased board savings
option to the 88E3018.
FEATURES
•IEEE 802.3 compliant 100BASE-TX and 10BASE-
T ports
•Reduced Gigabit Media Independent Interface
(RGMII)
•Media Independent Interface (MII) support
•Source Synchronous MII support
•Virtual Cable Tester®(VCT™) Technology
•PECL interface supporting 100BASE-FX applica-
tions
•Automatic MDI/MDIX crossover for 10BASE-T and
100BASE-TX
•Jumbo frame support to 10 Kbytes with up to
±150 ppm clock frequency difference
•IEEE 802.3u Auto-Negotiation support for auto-
matic speed and duplex selection
•Far-End Fault Indication (FEFI) support for
100BASE-FX applications
•Supports 802.3ah Unidirectional Enable
•Energy detect feature
•Baseline wander correction
•Auto-Calibration for MAC Interface outputs
•COMA Mode support
•Flexible serial management interface (MDC/MDIO)
for register access
•Programmable interrupt to minimize polling
•IEEE 1149.1 Standard Test Access Port and
boundary scan compatible (88E3018 only)
•Supports three (3) LEDs per port
•0.15 μm standard digital CMOS process
•56-pin QFN 8 mm x 8 mm package (88E3015
device)
•64-pin QFN 9 mm x 9 mm package (88E3018
device)
•Available in Industrial grade (88E3018 device,
RoHS 6/6 package only)

88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Doc. No. MV-S103657-00, Rev. D Copyright © 2008 Marvell
Page 4 Document Classification: Proprietary Information January 4, 2008, Advance
88E3015 Device Functional Block Diagram
88E3018 Device Functional Block Diagram
Table 1: 88E3015/88E3018 Devices Feature Differences
88E3015 88E3018
Package 56-pin QFN 64-pin QFN
MII Yes Yes
RGMII Yes Yes
Virtual Cable Tester®Yes Yes
Fiber Support Yes Yes
Parallel LEDs Yes Yes
Power Management Yes Yes
JTAG Support No Yes
Industrial Grade No RoHS 6/6 Package Only
MDIP/N[1]
MDIP/N[0]
SIGDET
XTAL_IN
Auto MDIX
Crossover
DAC
ADC
Digital
Adaptive
Equalizer
Baseline
Wander
Canceller
10 Mbps
Receiver 10/100
Receive
PCS
10/100
Transmit
PCS
FX Link
& Auto
Negotiation
RGMII
or MII
RXD[3:0]
RX_CTRL
TX_CTRL
TXD[3:0]
Clock/
Reset Management
Interface
MDC
MDIO
XTAL_OUT
LED/
Configuration
LED[2:0]
TX_CLK
RX_CLK
CONFIG[3:0]
CRS
COL
VREF
RX_ER
RESETn
COMAn
2.5V
Regulator
1.2V
Regulator
CTRL25
DIS_REG12
MDIP/N[1]
MDIP/N[0]
SIGDET
Auto MDIX
Crossover
DAC
ADC
Digital
Adaptive
Equalizer
Baseline
Wander
Canceller
10 Mbps
Receiver 10/100
Mbps
Receive
PCS
10/100
Mbps
Transmit
PCS
FX Link
& Auto
Negotiation
RGMII
or MII
Management
Interface
MDC
MDIO
LED/
Configuration
LED[2:0]
CONFIG[3:0]
JTAG Boundary
Scan
XTAL_IN
Clock/
Reset
XTAL_OUT
RESETn
COMAn
2.5V
Regulator
1.2V
Regulator
CTRL25
DIS_REG12
RXD[3:0]
RX_CTRL
TX_CTRL
TXD[3:0]
TX_CLK
RX_CLK
CRS
COL
VREF
RX_ER

Copyright © 2008 Marvell Doc. No. MV-S103657-00, Rev. D
January 4, 2008, Advance Document Classification: Proprietary Information Page 5
Table of Contents
SECTION 1. SIGNAL DESCRIPTION ................................................................... 9
1.1 88E3015 Device 56-Pin QFN Pinout ............................................................................. 9
1.2 88E3018 Device 64-Pin QFN Pinout ........................................................................... 10
1.3 Pin Description ............................................................................................................ 11
1.3.1 Pin Type Definitions .......................................................................................................... 11
1.3.2 88E3015 56-Pin QFN Assignments - Alphabetical by Signal Name ................................. 21
1.3.3 88E3018 64-Pin QFN Assignments - Alphabetical by Signal Name ................................. 22
SECTION 2. FUNCTIONAL DESCRIPTION ......................................................... 23
2.1 MAC Interface............................................................................................................... 24
2.1.1 Reduced Gigabit Media Independent Interface (RGMII)................................................... 24
2.1.2 Media Independent Interface (MII).................................................................................... 25
2.1.3 Source Synchronous MII................................................................................................... 26
2.2 Serial Management Interface...................................................................................... 27
2.2.1 MDC/MDIO Read and Write Operations........................................................................... 27
2.2.2 Preamble Suppression......................................................................................................28
2.2.3 Programming Interrupts ....................................................................................................28
2.3 Transmit and Receive Functions ............................................................................... 29
2.3.1 Transmit Side Network Interface....................................................................................... 29
2.3.2 Encoder............................................................................................................................. 29
2.3.3 Receive Side Network Interface........................................................................................ 29
2.3.4 Decoder ............................................................................................................................ 30
2.3.5 Auto-Negotiation ............................................................................................................... 31
2.4 Power Management ..................................................................................................... 32
2.4.1 IEEE Power Down Mode .................................................................................................. 32
2.4.2 Energy Detect +TM........................................................................................................... 32
2.4.3 Normal 10/100 Mbps Operation........................................................................................32
2.4.4 COMA Mode ..................................................................................................................... 33
2.5 Regulators and Power Supplies................................................................................. 34
2.5.1 AVDD ................................................................................................................................ 34
2.5.2 AVDDC ............................................................................................................................. 34
2.5.3 AVDDR ............................................................................................................................. 34
2.5.4 AVDDX.............................................................................................................................. 35
2.5.5 DVDD................................................................................................................................ 35
2.5.6 VDDO................................................................................................................................ 35
2.5.7 VDDOR ............................................................................................................................. 35
2.6 Hardware Configuration.............................................................................................. 36

Doc. No. MV-S103657-00, Rev. D Copyright © 2008 Marvell
Page 6 Document Classification: Proprietary Information January 4, 2008, Advance
88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
2.7 Far End Fault Indication (FEFI) ...................................................................................38
2.8 802.3ah Unidirectional Enable ....................................................................................38
2.9 Virtual Cable Tester® Feature .....................................................................................39
2.10 Auto MDI/MDIX Crossover...........................................................................................40
2.11 LED Interface ................................................................................................................41
2.11.1 Manual Override............................................................................................................... 41
2.11.2 PHY Control ..................................................................................................................... 42
2.11.3 LED Polarity ..................................................................................................................... 46
2.11.4 Stretching and Blinking..................................................................................................... 46
2.12 Automatic and Manual Impedance Calibration .........................................................47
2.12.1 MAC Interface Calibration Circuit ..................................................................................... 47
2.12.2 MAC Interface Calibration Register Definitions ................................................................ 47
2.12.3 Changing Auto Calibration Targets .................................................................................. 48
2.12.4 Manual Settings to The Calibration Registers .................................................................. 48
2.13 CRC Error Counter .......................................................................................................52
2.13.1 Enabling The CRC Error Counter..................................................................................... 52
2.14 IEEE 1149.1 Controller ................................................................................................53
2.14.1 Bypass Instruction ............................................................................................................ 53
2.14.2 Sample/Preload Instruction .............................................................................................. 53
2.14.3 Extest Instruction.............................................................................................................. 55
2.14.4 The Clamp Instruction ...................................................................................................... 55
2.14.5 The HIGH-Z Instruction ....................................................................................................55
2.14.6 ID CODE Instruction......................................................................................................... 55
SECTION 3. REGISTER DESCRIPTION ............................................................. 56
SECTION 4. ELECTRICAL SPECIFICATIONS ..................................................... 87
4.1. Absolute Maximum Ratings ........................................................................................87
4.2. Recommended Operating Conditions........................................................................88
4.3 Package Thermal Information .....................................................................................89
4.3.1 88E3015 Device 56-Pin QFN package ............................................................................ 89
4.3.2 88E3018 Device 64-Pin QFN package ............................................................................ 90
4.4 Current Consumption ..................................................................................................91
4.4.1 Current Consumption AVDD + Center Tap ...................................................................... 91
4.4.2 Current Consumption AVDDC.......................................................................................... 91
4.4.3 Current Consumption DVDD ............................................................................................ 92
4.4.4 Current Consumption VDDO + VDDOR........................................................................... 92
4.5. DC Operating Conditions ............................................................................................93
4.5.1 Non-MAC Interface Digital Pins........................................................................................ 93
4.5.2 Stub-Series Transceiver Logic (SSTL_2)......................................................................... 94

Copyright © 2008 Marvell Doc. No. MV-S103657-00, Rev. D
January 4, 2008, Advance Document Classification: Proprietary Information Page 7
4.5.3 IEEE DC Transceiver Parameters .................................................................................... 96
4.6 AC Electrical Specifications ........................................................................................97
4.6.1 Reset and Configuration Timing ....................................................................................... 97
4.6.2 XTAL_IN Input Clock Timing ............................................................................................ 98
4.7 MII Interface Timing......................................................................................................99
4.7.1 100 Mbps MII Transmit Timing - Non Source Synchronous ............................................. 99
4.7.2 10 Mbps MII Transmit Timing - Non Source Synchronous ............................................... 99
4.7.3 100 Mbps MII Transmit Timing - Source Synchronous................................................... 100
4.7.4 10 Mbps MII Transmit Timing - Source Synchronous..................................................... 100
4.7.5 100 Mbps MII Receive Timing ........................................................................................ 101
4.7.6 10 Mbps MII Receive Timing .......................................................................................... 101
4.8 RGMII Interface Timing ..............................................................................................102
4.8.1 RGMII Transmit Timing................................................................................................... 102
4.8.2 RGMII Receive Timing.................................................................................................... 103
4.9 Latency Timing ...........................................................................................................105
4.9.1 MII to 100BASE-TX Transmit Latency Timing ................................................................ 105
4.9.2 MII to 10BASE-T Transmit Latency Timing .................................................................... 105
4.9.3 100BASE-TX to MII Receive Latency Timing ................................................................. 107
4.9.4 10BASE-T to MII Receive Latency Timing ..................................................................... 107
4.9.5 RGMII to 100BASE-TX Transmit Latency Timing........................................................... 109
4.9.6 RGMII to 10BASE-T Transmit Latency Timing ............................................................... 109
4.9.7 100BASE-TX to RGMII Receive Latency Timing........................................................... 110
4.9.8 10BASE-T to RGMII Receive Latency Timing ............................................................... 110
4.10 Serial Management Timing ........................................................................................111
4.11 JTAG Timing ...............................................................................................................112
SECTION 5. PACKAGE MECHANICAL DIMENSIONS ........................................ 113
5.1 88E3015 Package Mechanical Dimensions..............................................................113
5.2 88E3018 Package Mechanical Dimensions..............................................................115
SECTION 6. APPLICATION EXAMPLES .......................................................... 117
6.1 10BASE-T/100BASE-TX Circuit Application ............................................................117
6.2 FX Interface to 3.3V Fiber Transceiver .....................................................................118
6.3 Transmitter - Receiver Diagram ................................................................................119
6.4 88E3018 to 88E3015 Backplane Connection - 100BASE-FX Interface...................120
6.5 88E3018 to Another Vendor’s PHY - 100BASE-FX Interface through a Backplane121
6.6 Marvell® PHY to Marvell PHY Direct Connection....................................................122

Doc. No. MV-S103657-00, Rev. D Copyright © 2008 Marvell
Page 8 Document Classification: Proprietary Information January 4, 2008, Advance
88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
SECTION 7. ORDER INFORMATION ............................................................... 123
7.1 Ordering Part Numbers and Package Markings......................................................123

Copyright © 2008 Marvell Doc. No. MV-S103657-00, Rev. D
January 4, 2008, Advance Document Classification: Proprietary Information Page 9
Signal Description
88E3015 Device 56-Pin QFN Pinout
Section 1. Signal Description
1.1 88E3015 Device 56-Pin QFN Pinout
The 88E3015 is manufactured in a 56-pin QFN.
Figure 1: 88E3015 Integrated 10BASE-T/100BASE-TX Fast Ethernet Transceiver 56-Pin QFN
Package
CONFIG[1] CONFIG[2] CONFIG[3]
DVDD
LED[0]
VDDO
LED[1] LED[2]
RESETn
DIS_REG12
DVDD
AVDDR
CTRL25
SIGDET
RX_ER
CRS
COL
VDDO
NC
MDIN[1]
MDIP[1]
AVDD
MDIN[0]
MDIP[0]
CONFIG[0]
TX_CTRL
TXD[3]
TXD[2]
TX_CLK
TXD[1]
TXD[0]
VREF
VDDOR
RXD[3]
RXD[2]
RX_CLK
RXD[0] RX_CTRL NC COMAn MDC NC VDDO MDIO DVDD XTAL_OUT XTAL_IN HSDACP
15
16
17
18
19
20
21
22
23
24
25
26
1 2 3 4 5 6 7 8 9
10 11 12
42 41 40 39 38 37 36 35 34 33 32 31
56
55
54
53
52
51
50
49
48
47
46
45
44
43
88E3015
13AVDDR
14
AVDDX
27 TSTPT
28 RSET
30 HSDACN
29 AVDDC
VDDOR
RXD[1]
EPAD - VSS

Doc. No. MV-S103657-00, Rev. D Copyright © 2008 Marvell
Page 10 Document Classification: Proprietary Information January 4, 2008, Advance
88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
1.2 88E3018 Device 64-Pin QFN Pinout
The 88E3018 is manufactured in a 64-pin QFN.
Figure 2: 88E3018 Integrated 10BASE-T/100BASE-TX Fast Ethernet Transceiver 64-Pin QFN
Package
1 2
3
4
5 6 7
8
9
10 11 12
13 14
15 16
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
NC
AVDD
NC
MDIP[1]
MDIN[1]
COL
NC
NC
CRS
RX_ER
SIGDET
CTRL25
VDDO
MDIN[0]
MDIP[0]
TSTPT
VDDOR
RX_CLK
RXD[2]
RXD[3]
VDDOR
TXD[1]
TXD[2]
TXD[3]
TX_CTRL
CONFIG[0]
VREF
RXD[1]
RXD[0]
RX_CTRL
17
18
19
20
21
22
23
24
25
26
30
31
32
27
28
29
64
63
62
61
60
59
58
57
56
55
51
50
49
54
53
52
CONFIG[1] CONFIG[2] CONFIG[3]
COMAn
LED[0]
VDDO
LED[1] LED[2]
RESETn
AVDDR
AVDDR
AVDDX
DVDD
TRSTn
DIS_REG12
DVDD
MDC NC VDDO MDIO TDI TCK TMS DVDD XTAL_OUT HSDACN AVDDC RSET TDO XTAL_IN NC HSDACP
TX_CLK
TXD[0]
EPAD - VSS
Top View
88E3018

Copyright © 2008 Marvell Doc. No. MV-S103657-00, Rev. D
January 4, 2008, Advance Document Classification: Proprietary Information Page 11
Signal Description
Pin Description
1.3 Pin Description
1.3.1 Pin Type Definitions
Pin Type Definition
H Input with hysteresis
I/O Input and output
I Input only
O Output only
PU Internal pull up
PD Internal pull down
D Open drain output
Z Tri-state output
mA DC sink capability

Doc. No. MV-S103657-00, Rev. D Copyright © 2008 Marvell
Page 12 Document Classification: Proprietary Information January 4, 2008, Advance
88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Table 2: RGMII Interface
88E3015 88E3018 Pin Name Type Description
52 60 TX_CLK/TXC I RGMII Transmit Clock provides a 25 MHz or 2.5
MHz reference clock with ± 50 ppm tolerance
depending on speed. In RGMII mode, TX_CLK is
used as TXC.
55 63 TX_CTRL/TX_CTL I RGMII Transmit Control. TX_EN is presented on
the rising edge of TX_CLK. In RGMII mode,
TX_CTRL is used as TX_CTL.
A logical derivative of TX_EN and TX_ER is pre-
sented on the falling edge of TX_CLK.
54
53
51
50
62
61
59
58
TXD[3]/TD[3]
TXD[2]/TD[2]
TXD[1]/TD[1]
TXD[0]/TD[0]
I RGMII Transmit Data. In RGMII mode, TXD[3:0]
are used as TD[3:0].
The transmit data nibble is presented on TXD[3:0]
on the rising edge of TX_CLK.
45 53 RX_CLK/RXC O RGMII Receive Clock provides a 25 MHz or 2.5
MHz reference clock with ± 50 ppm tolerance
derived from the received data stream depending
on speed. In RGMII mode, RX_CLK is used as
RXC.
41 49 RX_CTRL/
RX_CTL
O RGMII Receive Control. RX_DV is presented on
the rising edge of RX_CLK. In RGMII mode,
RX_CTRL is used as RX_CTL.
A logical derivative of RX_DV and RX_ER is pre-
sented on the falling edge of RX_CLK.
47
46
43
42
55
54
51
50
RXD[3]/RD[3]
RXD[2]/RD[2]
RXD[1]/RD[1]
RXD[0]/RD[0]
O RGMII Receive Data. In RGMII mode, RXD[3:0]
are used as RD[3:0].
The receive data nibble is presented on RXD[3:0]
on the rising edge of RX_CLK.

Copyright © 2008 Marvell Doc. No. MV-S103657-00, Rev. D
January 4, 2008, Advance Document Classification: Proprietary Information Page 13
Signal Description
Pin Description
Table 3: MII Interface
88E3015 88E3018 Pin Name Type Description
52 60 TX_CLK I/O, Z MII Transmit Clock. TX_CLK provides a 25 MHz
and 2.5 MHz clock reference for TX_CTRL,
TX_ER, and TXD[3:0], depending on the speed.
TX_CLK is an output when in normal MII mode,
and is an input in source synchronous MII mode.
54
53
51
50
62
61
59
58
TXD[3]
TXD[2]
TXD[1]
TXD[0]
I MII Transmit Data. TXD[3:0] presents the data nib-
ble to be transmitted onto the cable.
TXD[3:0] is synchronous to TX_CLK.
55 63 TX_CTRL/TX_EN MII Transmit Enable. In MII mode, TX_CTRL is
used as TX_EN. When TX_CTRL is asserted, data
on TXD[3:0] along with TX_ER is encoded and
transmitted onto the cable.
TX_EN is synchronous to TX_CLK.
45 53 RX_CLK O, Z MII Receive Clock. RX_CLK provides a 25 MHz
and 2.5 MHz clock reference for RX_CTRL,
RX_ER, and RXD[3:0] depending on the speed.
47
46
43
42
55
54
51
50
RXD[3]
RXD[2]
RXD[1]
RXD[0]
O, Z MII Receive Data. Symbols received on the cable
are decoded and presented on RXD[3:0].
RXD[3:0] is synchronous to RX_CLK.
41 49 RX_CTRL/RX_DV MII Receive Data Valid. Data received on the cable
is decoded and presented on RXD[3:0] and
RX_ER. In MII mode, RX_CTRL is used as
RX_DV.
RX_CTRL is synchronous to RX_CLK.
17 19 RX_ER I/O, Z MII Receive Error. When RX_ER and RX_CTRL
are both asserted, the signals indicate an error
symbol is detected on the cable.
When RX_ER is asserted with RX_CTRL de-
asserted, a false carrier is detected on the cable.
RX_ER is synchronous to RX_CLK.

Doc. No. MV-S103657-00, Rev. D Copyright © 2008 Marvell
Page 14 Document Classification: Proprietary Information January 4, 2008, Advance
88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
18 20 CRS O, Z MII Carrier Sense. CRS asserts when the receive
medium is non-idle.
CRS is asynchronous to RX_CLK, and TX_CLK.
19 23 COL O, Z MII Collision. In full-duplex modes, COL is always
low. In 10BASE-T/100BASE-TX half-duplex
modes, COL asserts only when both the transmit
and receive media are non-idle.
In 10BASE-T half-duplex mode, COL is asserted to
indicate signal quality error (SQE). Disable SQE by
clearing register 16.2 to zero.
COL is asynchronous to RX_CLK, and TX_CLK.
Table 3: MII Interface (Continued)
88E3015 88E3018 Pin Name Type Description

Copyright © 2008 Marvell Doc. No. MV-S103657-00, Rev. D
January 4, 2008, Advance Document Classification: Proprietary Information Page 15
Signal Description
Pin Description
Table 4: Network Interface
88E3015 88E3018 Pin Name Type Description
26
25
31
30
MDIP[0]
MDIN[0]
I/O Media Dependent Interface[0].
In MDI configuration, MDI[0]± is used for the trans-
mit pair. In MDIX configuration, MDI[0]± is used for
the receive pair.
23
22
26
25
MDIP[1]
MDIN[1]
I/O Media Dependent Interface[1].
In MDI configuration, MDI[1]± is used for the
receive pair. In MDIX configuration, MDI[1]± is used
for the transmit pair.
16 18 SIGDET I In 100BASE-FX mode, SIGDET indicates whether
a signal is detected by the fiber optic transceiver.
In 100BASE-TX/10BASE-T modes, this pin should
not be left floating. It should be tied either high or
low.
Table 5: Serial Management Interface
88E3015 88E3018 Pin Name Type Description
38 48 MDC I MDC is the clock reference for the serial manage-
ment interface. A continuous clock stream is not
required (i.e., MDC can be stopped when the MDC/
MDIO master is not sending a command). The
maximum frequency supported is 8.33 MHz.
35 45 MDIO I/O MDIO is the management data. MDIO is used to
transfer management data in and out of the device
synchronously to MDC. This pin requires a pull-up
resistor in a range from 1.5 kohm to 10 kohm.

Doc. No. MV-S103657-00, Rev. D Copyright © 2008 Marvell
Page 16 Document Classification: Proprietary Information January 4, 2008, Advance
88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Table 6: LED
88E3015 88E3018 Pin Name Type Description
8 9 LED[2]/Interrupt O Parallel LED outputs. See Section 2.11 "LED Inter-
face" on page 41 for LED interface details. See
Section 2.2.3 "Programming Interrupts" on page
28 for interrupt details.
7 8 LED[1] O Parallel LED outputs. See Section 2.11 "LED Inter-
face" on page 41 for details.
5 6 LED[0] O Parallel LED outputs. See Section 2.11 "LED Inter-
face" on page 41 for details.
Table 7: JTAG
88E3015 88E3018 Pin Name Type Description
-- 43 TDI I Boundary scan test data input. TDI contains an
internal 150 kohm pull-up resistor.
-- 41 TMS I Boundary scan test mode select input. TMS con-
tains an internal 150 kohm pull-up resistor.
-- 42 TCK I Boundary scan test clock input. TCK contains an
internal 150 kohm pull-up resistor.
-- 11 TRSTn I Boundary scan test reset input. Active low. TRSTn
contains an internal 150 kohm pull-up resistor as
per the 1149.1 specification. After power up, the
JTAG state machine should be reset by applying a
low signal on this pin, or by keeping TMS high and
applying 5 TCK pulses, or by pulling this pin low by
a 4.7 kohm resistor.
-- 44 TDO O Boundary scan test data output.

Copyright © 2008 Marvell Doc. No. MV-S103657-00, Rev. D
January 4, 2008, Advance Document Classification: Proprietary Information Page 17
Signal Description
Pin Description
Table 8: Clock/Configuration/Reset
88E3015 88E3018 Pin Name Type Description
32 38 XTAL_IN I Reference Clock. 25 MHz ± 50 ppm tolerance crys-
tal reference or oscillator input.
33 39 XTAL_OUT O Reference Clock. 25 MHz ± 50 ppm tolerance crys-
tal reference. When the XTAL_OUT pin is not con-
nected, it should be left floating. XTAL_OUT is
used for crystal only. This pin should be left floating
when an oscillator input is connected to XTAL_IN.
3
2
1
56
3
2
1
64
CONFIG[3]
CONFIG[2]
CONFIG[1]
CONFIG[0]
I Hardware Configuration.
See Section 2.6 "Hardware Configuration" on page
36 for details.
9 10 RESETn I Hardware reset. Active low.
XTAL_IN/XTAL_OUT must be active for a minimum
of 10 clock cycles before the rising edge of
RESETn.
RESETn must be pulled high for normal operation.
49 57 VREF I MAC Interface input voltage reference.
Must be set to VDDOR/2 when used as 2.5V
SSTL_2.
Set to VDDOR when used as 2.5V/3.3V LV CMOS.
39 4 COMAn I COMA Control. Active low. If RESETn is low then
COMAn has no effect. COMAn contains an internal
150 kohm pull-up resistor.
0 = In power saving mode
1 = Normal operation

Doc. No. MV-S103657-00, Rev. D Copyright © 2008 Marvell
Page 18 Document Classification: Proprietary Information January 4, 2008, Advance
88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Table 9: Regulator & Reference
88E3015 88E3018 Pin Name Type Description
28 33 RSET I Constant voltage reference.
External 2 kohm 1% resistor connection to VSS is
required for this pin.
10 12 DIS_REG12 I 1.2V Regulator Disable.
Tie to VDDO to disable, Tie to VSS to enable.
15 17 CTRL25 O 2.5V Regulator Control.
This signal ties to the base of the BJT. If the 2.5V
regulator is not used it can be left floating.
Table 10: Test
88E3015 88E3018 Pin Name Type Description
31 36 HSDACP O Test Pin.
These pins have 49.9 ohm internal termination.
They should be brought out to a via or pad to facili-
tate debug. If debug is not important and there are
board space constraints, this pin can be left float-
ing.
30 35 HSDACN O Test Pin.
These pins have 49.9 ohm internal termination.
They should be brought out to a via or pad to facili-
tate debug. If debug is not important and there are
board space constraints, this pin can be left float-
ing.
27 32 TSTPT O Test point. Leave unconnected.

Copyright © 2008 Marvell Doc. No. MV-S103657-00, Rev. D
January 4, 2008, Advance Document Classification: Proprietary Information Page 19
Signal Description
Pin Description
Table 11: Power & Ground
88E3015 88E3018 Pin Name Type Description
24 28 AVDD Power Analog supply1. 2.5V. AVDD can be supplied exter-
nally with 2.5V, or via the 2.5V regulator.
1. AVDD supplies the MDIP/N[1:0] pins.
29 34 AVDDC Power Analog supply - 2.5V or 3.3V2.
AVDDC must be supplied externally. Do not use
the 2.5V regulator to power AVDDC.
2. AVDDC supplies the XTAL_IN and XTAL_OUT pins.
12
13
14
15
AVDDR Power 1.2V Regulator supply - 2.5V
AVDDR can be supplied externally with 2.5V, or via
the 2.5V regulator. If the 1.2V regulator is not used,
AVDDR must still be tied to 2.5V.
14 16 AVDDX Power 2.5V Regulator supply - 3.3V
AVDDX must be supplied externally. Note that this
supply must be the same voltage as AVDDC.
If the 2.5V regulator is not used, then it means a
2.5V supply is in the system. AVDDX should be left
floating.
4
11
34
5
13
40
DVDD Digital core supply - 1.2V.
DVDD can be supplied externally with 1.2V, or via
the 1.2V regulator.
6
20
36
7
24
46
VDDO Power 2.5V or 3.3V non-MAC Interface digital I/O supply3.
VDDO must be supplied externally. Do not use the
2.5V regulator to power VDDO.
3. VDDO supplies the RX_ER, COL, CRS, SIGDET, MDC, MDIO, RESETn, LED[2:0], CONFIG[3:0], TDI, TMS, TCK, TRSTn, TDO,
COMAn, DIS_REG12, CTRL25, HSDAC, and TSTPT pins.
44
48
52
56
VDDOR Power 2.5V or 3.3V MAC Interface digital I/O supply4.
VDDOR must be supplied externally. Do not use
the 2.5V regulator to power VDDOR.
4. VDDOR supplies the TXD[3:0], TX_CLK, TX_CTRL, RXD[3:0], RX_CLK, and RX_CTRL pins.
EPAD EPAD VSS Ground Ground to digital core.
The 64-pin QFN package has an exposed die pad
(E-PAD) at its base. This E-PAD must be soldered
to VSS. Refer to the package mechanical drawings
for the exact location and dimensions of the EPAD.
21
37
40
21
22
27
29
37
47
NC NC No Connect. These pins are not bonded to the die
and can be tied to anything.

Doc. No. MV-S103657-00, Rev. D Copyright © 2008 Marvell
Page 20 Document Classification: Proprietary Information January 4, 2008, Advance
88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Table 12: I/O State at Various Test or Reset Modes
Pin(s) Isolate Loopback Software
Reset
Hardware
Reset
Power Down Power
Down and
Isolate
MDIP/
N[1:0]
Active Active Tri-state Tri-state Tri-state Tri-state
TX_CLK Tri-state Active Active Tri-state Active Tri-state
RXD[0]
RXD[2]
RXD[3]
RXD[1]
RX_DV
RX_ER
CRS
COL
Tri-state Active Low Low Low Tri-state
RX_CLK Tri-state Active Reg. 28.1 state
1 = Active
0 = Low
Low Reg. 28.1 state
1 = Active
0 = Low
Tri-state
MDIO Active Active Active Tri-state Active Active
LED Active Active Active High High High
TDO Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state