Maxlinear Xr17v354 Guide

MaxLinear Confidential

TBD/18 200DGR00 i

MaxLinear Confidential • www.maxlinear.com • 200DGR00

XR17V35x

PCIe UARTs

Design Guide

XR17V35x PCIe UARTs Design Guide Revision History

4/24/20 200DGR00 ii

Revision History

Document No. Release Date Change Description

200DGR00 4/24/20 Initial release.

XR17V35x PCIe UARTs Design Guide Table of Contents

4/24/20 200DGR00 iii

Table of Contents

Introduction......................................................................................................................................................... 1

Reference Documentation ................................................................................................................................. 1

Pin Groups .......................................................................................................................................................... 1

Design and Layout Recommendations ............................................................................................................ 2

XR17V35x PCIe UARTs Design Guide List of Tables

4/24/20 200DGR00 v

List of Tables

Table 1: PCIe Interface......................................................................................................................................... 2

Table 2: Buck Regulator Output ........................................................................................................................... 2

Table 3: XR17V354 / XR17V358 PCIe UART Expansion Interface Signals......................................................... 2

Table 4: Other PCIe UART "Special Handling" Device Pins ................................................................................ 3

Table 5: Analog Voltage Inputs............................................................................................................................. 3

Table 6: Test Inputs .............................................................................................................................................. 3

Table 7: Voltage Rails........................................................................................................................................... 4

XR17V35x PCIe UARTs Design Guide Introduction

4/24/20 200DGR00 1

Introduction

The XR17V35x Design Guide provides a helpful checklist of schematic design and PCB layout tips to aid in applying a

XR17V35x PCIe UART to your product design. The XR17V35x Family provides a single lane PCIe 2.0 Gen 1 compliant

bridge to 2, 4 or 8 independent enhanced 16550 compatible UARTs and also includes 16 multi-purpose I/Os (MPIOs), a 16-

bit general purpose counter / timer and a global interrupt status register.

The design guide contains design information for XR17V354 and XR17V358 which may have a single (master) device or

have a dual (master / slave) configuration using the Expansion Interface signals documented. The XR17V352 can only be

designed as a single device and does not have an Expansion Interface.

Please refer to the respective XR17V35x datasheet for more information, including application block diagram and pin-out

diagram.

Reference Documentation

XR17V352 Data Sheet

XR17V354 Data Sheet

XR17V358 Data Sheet

Visit www.maxlinear.com to obtain copies of these documents.

Pin Groups

The tables below are arranged by the following pin groups:

■PCIe Interface

■Buck Regulator Output

■PCIe UART Expansion Interface Signals (XR17V354 / XR17V358)

■Other PCIe UART "Special Handling" Device Pins

■Analog Voltage Inputs

■Test Inputs

■Voltage Rails

XR17V35x PCIe UARTs Design Guide Design and Layout Recommendations

4/24/20 200DGR00 2

Design and Layout Recommendations

1. Estimated trace capacitance using FR4 dielectric is 3.3pF / inch.

Table 1: PCIe Interface

Schematic Design Recommendations

TX +/- and RX +/- must be AC coupled using 100nF 0603 or smaller (0402) recommended) ceramic capacitors at the transmitting

source.

Layout Recommendations

TX +/- and RX +/- are critical nets at 2.5GHz and must follow specific PCB layout rules: Ensure 100Ω differential impedance.

TX +/- and RX +/- are critical nets at 2.5GHz and must follow specific PCB layout rules:

1. Limit to maximum of 2 vias per signal.

2. Trace length on add-in board should be a maximum of 3.5 inches.

3. Differential pair should be routed symmetrically, length matched within 20 mils.

4. No stubs, test points (if used) should be in series.

5. Traces should not cross split reference planes.

CLK +/- should be routed as symmetrical differential pairs with minimal trace length.

Table 2: Buck Regulator Output

Schematic Design Recommendations

LX pins (pins A13 and A14 on XR17V354 and XR17V358 and pins A9 and A10 on XR17V352), should be connected together and

through 4.7uH inductor to FB pin.

FB pin should be additionally decoupled with 47µF ceramic capacitor.

PWRGD can be connected to an LED or test point for indicating that the 1.2V buck output voltage is stable. If PWRGD is used to

monitor whether the BUCK is in or out of regulation, a glitch filter must be used to ensure that the PWRGD is low >100µs before the

determining that the BUCK is out of regulation. This will ensure that noisy environments that can cause glitches on the PWRGD output

at the switching frequency are not interpreted as a bad BUCK output.

Table 3: XR17V354 / XR17V358 PCIe UART Expansion Interface Signals

Schematic Design and Layout Recommendations

Pins Master Only (No Slave) Slave Present

Master Slave

CLK, D[7:0], SEL, INT Leave open / unconnected Must be routed between master and slave with <25pF of

trace capacitance1

MODE Pull high Pull high Tie to ground

PRES Leave unconnected or tie to ground Pull high Leave unconnected or tie to ground

XR17V35x PCIe UARTs Design Guide Design and Layout Recommendations

4/24/20 200DGR00 3

Table 4: Other PCIe UART "Special Handling" Device Pins

Schematic Design Recommendations

Device Reset

Internally logically “AND”ed together.

Connect PERST# to PCIe edge connector reset input.

Connect RESET# to PERST# or connect to pull-up.

CLKREQ#

CLKREQ# support is optional in PCIe specification and is not supported in the XR17V35x device. Leave this pin unconnected.

MPIO Pins

If unused, it is recommended that MPIO pins are pulled to defined logic states, either high or low.

JTAG Signals

TRST#, TCK, TMS, TDI and TDO may be left unconnected if unused.

EEPROM Signals

If unused, EECK, EECS, EEDI and EEDO may be left unconnected.

EECS must be pulled high with 4.7kΩ resistor if an external EEPROM is connected for its contents to be read by the XR17V35x device.

Other

ENIR# should be pulled high unless IR mode is used.

EN485# should be pulled high unless automatic RS-485 mode is used on all UART ports.

TMRCK should be pulled high unless an external timer / counter clock input is required.

Connect REXT to ground through 191Ω 1% resistor via a short trace.

Unused UART Inputs

RI#, CD#, CTS# and DSR# are all inputs. If unused, they are recommended to be pulled to defined logic state, either high or low.

Layout Recommendations

CLK, D[7:0], SEL, INT must be routed between master and slave with < 25pF of trace capacitance1.

Table 5: Analog Voltage Inputs

Schematic Design Recommendations

Isolate VCC33A from digital VCC33 with ferrite bead to this pin.

Isolate VCC12A from digital 1.2V source (either XR17V35x buck output or external 1.2V source) with ferrite bead to this pin.

Isolate VCC12 from digital 1.2V source (either XR17V35x buck output or external 1.2V source) with ferrite bead to this pin. If using

external 1.2V source, add 250Ω pull-down resistor to this pin per ECN.

Table 6: Test Inputs

Schematic Design Recommendations

On XR17V354 and XR17V358: TEST0, TEST1 and TEST2 should be tied to ground for device normal operation.

On XR17V352: TEST0, TEST1, TEST2, TEST3 and TEST5 should be tied to ground for normal device operation. TEST4# should be

pulled high for normal device operation.

The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by

MaxLinear, Inc. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this

guide. Complying with all applicable copyright laws is the responsibility of the user. Without limiting the rights under copyright, no part of this document may be

reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photocopying, recording, or

otherwise), or for any purpose, without the express written permission of MaxLinear, Inc.

Maxlinear, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be

expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless

MaxLinear, Inc. receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c)

potential liability of MaxLinear, Inc. is adequately protected under the circumstances.

MaxLinear, Inc. may have patents, patent applications, trademarks, copyrights, or other intellectual property rights covering subject matter in this document. Except

as expressly provided in any written license agreement from MaxLinear, Inc., the furnishing of this document does not give you any license to these patents,

trademarks, copyrights, or other intellectual property.

MaxLinear, the MaxLinear logo, and any MaxLinear trademarks, MxL, Full-Spectrum Capture, FSC, G.now, AirPHY and the MaxLinear logo are all on the products

product names appearing herein are the property of their respective owners.

XR17V35x PCIe UARTs Design Guide Disclaimer

MaxLinear, Inc.

5966 La Place Court, Suite 100

Carlsbad, CA 92008

760.692.0711 p.

760.444.8598 f.

www.maxlinear.com

Table 7: Voltage Rails

Schematic Design Recommendations

All decoupling capacitors should be implemented without traces to power or ground reference planes if possible.

Bulk Decoupling