MaxLinear XR17V358 User manual

1
XR17V358
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
JULY 2018 REV. 1.0.6
GENERAL DESCRIPTION
The XR17V3581 is a single chip 8-channel PCI
Express (PCIe) UART (Universal Asynchronous
Receiver and Transmitter), optimized for higher
performance and lower power. The XR17V358
serves as a single lane PCIe bridge to 8 independent
enhanced 16550 compatible UARTs. The XR17V358
is compliant to PCIe 2.0 Gen 1 (2.5 GT/s).
In addition to the UART channels, the XR17V358 has
16 multi-purpose I/Os (MPIOs), a 16-bit general
purpose counter/timer and a global interrupt status
register to optimize interrupt servicing.
Each UART of the XR17V358 has many enhanced
features such as the 256-bytes TX and RX FIFOs,
programmable Fractional Baud Rate Generator,
Automatic Hardware or Software Flow Control, Auto
RS-485 Half-Duplex Direction Control, programmable
TX and RX FIFO Trigger Levels, TX and RX FIFO
Level Counters, infrared mode, and data rates up to
31.25 Mbps. The XR17V358 is available in a 176-pin
FPBGA package (13 x 13 mm).
NOTE 1: Covered by U.S. Patents #5,649,122, #6,754,839,
#6,865,626 and #6,947,999
APPLICATIONS
Next generation Point-of-Sale Systems
Remote Access Servers
Storage Network Management
Factory Automation and Process Control
Multi-port RS-232/RS-422/RS-485 Cards
FEATURES
Single 3.3V power supply
Internal buck regulator for 1.2V core
PCIe 2.0 Gen 1 compliant
x1 Link, dual simplex, 2.5 Gbps in each direction
Expansion bus interface
EEPROM interface for configuration
Global interrupt status register for all eight UARTs
Up to 31.25 Mbps serial data rate
16 multi-purpose inputs/outputs (MPIOs)
16-bit general purpose timer/counter
Sleep mode with wake-up Indicator
Eight independent UART channels controlled with
■16550 compatible register Set
■256-byte TX and RX FIFOs
■Programmable TX and RX Trigger Levels
■TX/RX FIFO Level Counters
■Fractional baud rate generator
■Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
■Automatic Xon/Xoff software flow control
■RS-485 half duplex direction control output
with programmable turn-around delay
■Multi-drop with Auto Address Detection
■Infrared (IrDA 1.1) data encoder/decoder
Software compatible to XR17C15x, XR17D15x,
XR17V25x PCI UARTs
FIGURE 1. BLOCK DIAGRAM OF THE XR17V358
Global
Configuration
Registers
Crystal Osc/Buffer
P C I Lo ca l
Bus
Interface
Configuration
Space
Registers
Multi- purpose
Inputs/Outputs
16-bit
Tim er/Counter
UART Channel 0
64- byte TX FIFO
64- byte RX FIFOBRG
IR
ENDEC
TX & RX
UART
Regs
TX+
RX+
EECK
EEDO
EECS
UART Channel 1
UART Channel 2
UART Channel 3
UART Channel 4
UART Channel 5
UART Channel 6
UART Channel 7
TMRCK
RX[7:0]
TX [7:0 ]
RTS#[7:0]
DTR#[7:0]
C T S #[7 :0 ]
D S R # [7 :0]
DCD#[7:0]
M P IO [7 :0 ]
RI#[7:0]
EEPROM
Interface
Global
Configuration
Registers
Global
Configuration
Registers
PCIe
Interface
Configuration
Space
Registers
Multi- purpose
Inputs/Outputs
Multi-purpose
Inputs/Outputs
16-bit
Tim er/Counter
16-bit
Tim er/Counter
UART Channel 0
64- byte TX FIFO
64-BRG
IR
ENDEC
TX & RX
UART
Regs
UART Channel 0
256-byte TX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
EEDI
UART Channel 1
UART Channel 2
UART Channel 3
UART Channel 4
UART Channel 5
UART Channel 6
UART Channel 7
TMRCK
RX [7:0]
TX [7:0 ]
RTS#[7:0]
DTR#[7:0]
C T S #[7 :0 ]
D S R # [7 :0]
DCD#[7:0]
M P IO [7 :0 ]MPIO[15:0]
RI#[7:0]
ENIR#
EEPROM
Interface
EEPROM
Interface
256-byte RX FIFO
TX-
RX-
CLK+
CLK-
CLKREQ#
PERST#
EN485#
Expansion
In te rfa c e
D[7:0]
SEL
IN T
MODE
CLK
Buck Regulator
125 M Hz Clock
PRES

FIGURE 2. 176-FPBGA PINOUT
Transparent Top View
A1 Corner
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Transparent Top View
A1 Corner
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC TX5 RI4 GND CTS4# TX4 DSR2# GND RTS 2# TMRCK TEST2 GND LX LX NC
CD5# DTR5# CTS5# CD4# DTR4# RX4 CD2# DTR2# RX2 ENIR# TEST1 GND VCC33 VCC33 VCC33
MPIO0 RI5# DSR5# RTS5# DSR4# RTS4# RI2# CTS2# TX2 EN485 # FB GND VCC33 ENABL E D0
MPIO2 MPIO1 RX5 GND VCC33 GND VCC12 GND VCC33 GND VCC12 GND PWRGD INT D2
MPIO5 MPIO4
GND TEST0
RX+ RX-
GND GND
TX+ TX-
GND VCC12
CLKREQ# PERST#
GND MPIO8 MPIO11 MPIO14 TMS GND VCC33 GND VCC12 GND CD7# EEDO RX0 DSR0# GND
MPIO9 MPIO12 MPIO15 TRST# TX3 CTS3# CD3# RI3# DSR6# TX7 CTS7# RI7# TX0 CTS0# DTR0#
MPIO10 MPIO13 TCK TDO RTS3# DTR3# RTS6# RX6 DTR6# Ri6# RX7 DTR7# EECK EEDI RTS0#
NC RESET# TDI GND RX3 DSR3# TX6 GND CTS6# CD6# RTS7# GND DSR7# EECS NC
D3 D4
D6 D7
CLK MODE
PRES GND
DSR1# CD1#
RX1 CTS1#
RI0# TX1
MPIO3 VCC12
MPIO6 GND
GND CLK+
REXT CLK-
GND GND
VCC33 VCC12
MPIO7 GND
VCC33 D1
GND D5
VCC12 SEL
GND RI1#
VCC33 DTR1#
GND RTS1#
VCC12 CD0#
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NC TX5 RI4 GND CTS4# TX4 DSR2# GND RTS 2# TMRCK TEST2 GND LX LX NC
CD5# DTR5# CTS5# CD4# DTR4# RX4 CD2# DTR2# RX2 ENIR# TEST1 GND VCC33 VCC33 VCC33
MPIO0 RI5# DSR5# RTS5# DSR4# RTS4# RI2# CTS2# TX2 EN485 # FB GND VCC33 ENABL E D0
MPIO2 MPIO1 RX5 GND VCC33 GND VCC12 GND VCC33 GND VCC12 GND PWRGD INT D2
MPIO5 MPIO4
GND TEST0
RX+ RX-
GND GND
TX+ TX-
GND VCC12
CLKREQ# PERST#
GND MPIO8 MPIO11 MPIO14 TMS GND VCC33 GND VCC12 GND CD7# EEDO RX0 DSR0# GND
MPIO9 MPIO12 MPIO15 TRST# TX3 CTS3# CD3# RI3# DSR6# TX7 CTS7# RI7# TX0 CTS0# DTR0#
MPIO10 MPIO13 TCK TDO RTS3# DTR3# RTS6# RX6 DTR6# Ri6# RX7 DTR7# EECK EEDI RTS0#
NC RESET# TDI GND RX3 DSR3# TX6 GND CTS6# CD6# RTS7# GND DSR7# EECS NC
D3 D4
D6 D7
CLK MODE
PRES GND
DSR1# CD1#
RX1 CTS1#
RI0# TX1
MPIO3 VCC12
MPIO6 GND
GND CLK+
REXT CLK-
GND GND
VCC33 VCC12
MPIO7 GND
VCC33 D1
GND D5
VCC12 SEL
GND RI1#
VCC33 DTR1#
GND RTS1#
VCC12 CD0#
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ORDERING INFORMATION(1)
PART NUMBER OPERATING TEMPERATURE RANGE LEAD-FREE PACKAGE PACKAGING METHOD
XR17V358IB176-F -40°C to +85°C Yes(2) 176-FPBGA Tray
XR17V358/SP339-0A-EB XR17V358 8-Channel Evaluation Board
XR17V358/SP339-E4-EB XR17V358 12-Channel Evaluation Board (Master / Slave)
XR17V358/SP339-E8-EB XR17V358 16-Channel Evaluation Board (Master / Slave)
NOTES:
1. Refer to www.exar.com/XR17V358 for most up-to-date Ordering Information.
2. Visit www.exar.com for additional information on Environmental Rating.
XR17V358
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HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6

XR17V358
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REV. 1.0.6 HIGH PERFORMANCE OCTAL PCI EXPRESS UART
PIN DESCRIPTIONS
NAME PIN # TYPE DESCRIPTION
PCIe SIGNALS
CLK+
CLK-
G4
H4
I
I
PCIe reference clock input. (Nominal single-ended swing from 0 to 700 mV.)
TX+
TX-
J1
J2
O
O
PCIe differential TX outputs. Must be AC coupled using 0.1 uF non-polarized
capacitor (0603 or smaller) near the transmitting source.
RX+
RX-
G1
G2
I
I
PCIe differential RX inputs. Must be AC coupled using 0.1 uF non-polarized
capacitor (0603 or smaller) near the transmitting source.
CLKREQ# L1 OPCIe edge connector clock request. Optional feature, not supported.
PERST# L2 IPCIe edge connector reset
REXT H3 Connect a 191 ohm 1% resistor to GND. This is used for PCIe PHY 
calibration.
MODEM OR SERIAL I/O INTERFACE
TX0 N13 OUART channel 0 Transmit Data or infrared transmit data.
RX0 M13 IUART channel 0 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted internally prior to
decoding by setting FCTR bit [4]. If unused, a pull-up or pull-down resistor is
recommended on this pin.
RTS0# P15 OUART channel 0 Request to Send or general purpose output (active LOW).
CTS0# N14 IUART channel 0 Clear to Send or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
DTR0# N15 OUART channel 0 Data Terminal Ready or general purpose output (active
LOW).
DSR0# M14 IUART channel 0 Data Set Ready or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
CD0# L13 IUART channel 0 Carrier Detect or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
RI0# L14 IUART channel 0 Ring Indicator or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
TX1 L15 OUART channel 1 Transmit Data or infrared transmit data.
RX1 K14 IUART channel 1 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4]. If unused, a pull-up or pull-down resistor is 
recommended on this pin.
RTS1# K13 OUART channel 1 Request to Send or general purpose output (active LOW).
CTS1# K15 IUART channel 1 Clear to Send or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
DTR1# J13 OUART channel 1 Data Terminal Ready or general purpose output (active
LOW).

XR17V358
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HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6
DSR1# J14 IUART channel 1 Data Set Ready or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
CD1# J15 IUART channel 1 Carrier Detect or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
RI1# H13 IUART channel 1 Ring Indicator or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
TX2 C9 OUART channel 2 Transmit Data or infrared transmit data.
RX2 B9 IUART channel 2 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4]. If unused, a pull-up or pull-down resistor is 
recommended on this pin.
RTS2# A9 OUART channel 2 Request to Send or general purpose output (active LOW).
CTS2# C8 IUART channel 2 Clear to Send or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
DTR2# B8 OUART channel 2 Data Terminal Ready or general purpose output (active
LOW).
DSR2# A7 IUART channel 2 Data Set Ready or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
CD2# B7 IUART channel 2 Carrier Detect or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
RI2# C7 IUART channel 2 Ring Indicator or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
TX3 N5 OUART channel 3 Transmit Data or infrared transmit data.
RX3 R5 IUART channel 3 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4]. If unused, a pull-up or pull-down resistor is 
recommended on this pin.
RTS3# P5 OUART channel 3 Request to Send or general purpose output (active LOW).
CTS3# N6 IUART channel 3 Clear to Send or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
DTR3# P6 OUART channel 3 Data Terminal Ready or general purpose output (active
LOW).
DSR3# R6 IUART channel 3 Data Set Ready or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
CD3# N7 IUART channel 3 Carrier Detect or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
RI3# N8 IUART channel 3 Ring Indicator or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
TX4 A6 OUART channel 4 Transmit Data or infrared transmit data.
PIN DESCRIPTIONS
NAME PIN # TYPE DESCRIPTION

XR17V358
5
REV. 1.0.6 HIGH PERFORMANCE OCTAL PCI EXPRESS UART
RX4 B6 IUART channel 4 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4]. If unused, a pull-up or pull-down resistor is 
recommended on this pin.
RTS4# C6 OUART channel 4 Request to Send or general purpose output (active LOW).
CTS4# A5 IUART channel 4 Clear to Send or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
DTR4# B5 OUART channel 4 Data Terminal Ready or general purpose output (active
LOW).
DSR4# C5 IUART channel 4 Data Set Ready or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
CD4# B4 IUART channel 4 Carrier Detect or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
RI4# A3 IUART channel 4 Ring Indicator or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
TX5 A2 OUART channel 5 Transmit Data or infrared transmit data.
RX5 D3 IUART channel 5 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4]. If unused, a pull-up or pull-down resistor is 
recommended on this pin.
RTS5# C4 OUART channel 5 Request to Send or general purpose output (active LOW).
CTS5# B3 IUART channel 5 Clear to Send or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
DTR5# B2 OUART channel 5 Data Terminal Ready or general purpose output (active
LOW).
DSR5# C3 IUART channel 5 Data Set Ready or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
CD5# B1 IUART channel 5 Carrier Detect or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
RI5# C2 IUART channel 5 Ring Indicator or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
TX6 R7 OUART channel 6 Transmit Data or infrared transmit data.
RX6 P8 IUART channel 6 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4]. If unused, a pull-up or pull-down resistor is 
recommended on this pin.
RTS6# P7 OUART channel 6 Request to Send or general purpose output (active LOW).
CTS6# R9 IUART channel 6 Clear to Send or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
DTR6# P9 OUART channel 6 Data Terminal Ready or general purpose output (active
LOW).
PIN DESCRIPTIONS
NAME PIN # TYPE DESCRIPTION

XR17V358
6
HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6
DSR6# N9 IUART channel 6 Data Set Ready or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
CD6# R10 IUART channel 6 Carrier Detect or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
RI6# P10 IUART channel 6 Ring Indicator or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
TX7 N10 OUART channel 7 Transmit Data or infrared transmit data.
RX7 P11 IUART channel 7 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4]. If unused, a pull-up or pull-down resistor is 
recommended on this pin.
RTS7# R11 OUART channel 7 Request to Send or general purpose output (active LOW).
CTS7# N11 IUART channel 7 Clear to Send or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
DTR7# P12 OUART channel 7 Data Terminal Ready or general purpose output (active
LOW).
DSR7# R13 IUART channel 7 Data Set Ready or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
CD7# M11 IUART channel 7 Carrier Detect or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
RI7# N12 IUART channel 7 Ring Indicator or general purpose input (active LOW). If
unused, a pull-up or pull-down resistor is recommended on this pin.
EXPANSION INTERFACE
MODE G15 IExpansion Interface Mode Select. Connect this pin to VCC to enable master
mode. Connect this pin to GND to enable slave mode.
CLK G14 I/O Expansion Interface Clock. In master mode, this pin is the clock output to the
slave device. In slave mode, this pin is the clock input from the master
device. The expansion interface clock is 62.5 MHz. The UARTs on the slave
device will need to use different baud rate generator divisors than the master
device. The trace capacitance between the master and slave device must be
less than 25pF.
D7 F15 I/O Expansion Interface Data 7 (MSB) with internal pull-down resistor. If a slave
device is present, connect between master and slave with trace capacitance
of less than 25 pF. Leave unconnected if no slave device is present.
D6 F14 I/O Expansion Interface Data 6 with internal pull-down resistor. If a slave device
is present, connect between master and slave with trace capacitance of less
than 25 pF. Leave unconnected if no slave device is present.
D5 F13 I/O Expansion Interface Data 5 with internal pull-down resistor. If a slave device
is present, connect between master and slave with trace capacitance of less
than 25 pF. Leave unconnected if no slave device is present.
D4 E15 I/O Expansion Interface Data 4 with internal pull-down resistor. If a slave device
is present, connect between master and slave with trace capacitance of less
than 25 pF. Leave unconnected if no slave device is present.
PIN DESCRIPTIONS
NAME PIN # TYPE DESCRIPTION

XR17V358
7
REV. 1.0.6 HIGH PERFORMANCE OCTAL PCI EXPRESS UART
D3 E14 I/O Expansion Interface Data 3 with internal pull-down resistor. If a slave device
is present, connect between master and slave with trace capacitance of less
than 25 pF. Leave unconnected if no slave device is present.
D2 D15 I/O Expansion Interface Data 2 with internal pull-down resistor. If a slave device
is present, connect between master and slave with trace capacitance of less
than 25 pF. Leave unconnected if no slave device is present.
D1 E13 I/O Expansion Interface Data 1 with internal pull-down resistor. If a slave device
is present, connect between master and slave with trace capacitance of less
than 25 pF. Leave unconnected if no slave device is present.
D0 C15 I/O Expansion Interface Data 0 (LSB) with internal pull-down resistor. If a slave
device is present, connect between master and slave with trace capacitance
of less than 25 pF. Leave unconnected if no slave device is present.
SEL G13 I/O Expansion Interface Read/Write Select. This is the the read/write select input
in the slave mode. This is the read/write select output in the master mode.
This pin has an internal pull-down resistor and can be left unconnected if
there is no slave device. The trace capacitance between the master and
slave device must be less than 25pF.
INT D14 I/O Expansion Interface Interrupt. This is the expansion interface interrupt output
in the slave mode. This is the expansion interface interrupt input in the 
master mode. This pin has an internal pull-down resistor. If a slave device is
present, connect between master and slave with trace capacitance of less
than 25 pF. Leave unconnected if no slave device is present.
PRES H14 ISlave Present, has internal pull-down resistor. In master mode, pull this pin to
VCC to check if a slave is device present. Connect this pin to GND or leave
unconnected if there is no slave device or to disable checking for a slave
device.
MPIO SIGNALS
MPIO0 C1 I/O Multi-purpose input/output 0. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO1 D2 I/O Multi-purpose input/output 1. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO2 D1 I/O Multi-purpose input/output 2. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO3 E3 I/O Multi-purpose input/output 3. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO4 E2 I/O Multi-purpose input/output 4. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
PIN DESCRIPTIONS
NAME PIN # TYPE DESCRIPTION

XR17V358
8
HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6
MPIO5 E1 I/O Multi-purpose input/output 5. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO6 F3 I/O Multi-purpose input/output 6. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO7 L3 I/O Multi-purpose input/output 7. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO8 M2 I/O Multi-purpose input/output 8. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO9 N1 I/O Multi-purpose input/output 9. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO10 P1 I/O Multi-purpose input/output 10. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO11 M3 I/O Multi-purpose input/output 11. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO12 N2 I/O Multi-purpose input/output 12. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO13 P2 I/O Multi-purpose input/output 13. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO14 M4 I/O Multi-purpose input/output 14. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
MPIO15 N3 I/O Multi-purpose input/output 15. This pin defaults to an input with interrupts 
disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
PIN DESCRIPTIONS
NAME PIN # TYPE DESCRIPTION

XR17V358
9
REV. 1.0.6 HIGH PERFORMANCE OCTAL PCI EXPRESS UART
EEPROM SIGNALS
EECK P13 I/O Serial clock output uses the internal 125 MHz clock divided by 256 (488 KHz)
following power-up or reset to read an external EEPROM. This pin may also
be manually clocked using the Configuration Register REGB.
EECS R14 I/O Active high chip select output to an external EEPROM with internal weak pull-
down resistor. Connect an external 4.7K ohm pull-up resistor to this pin to
enable reading of an external EEPROM. This pin may also be manually
enabled using the Configuration Register REGB.
EEDI P14 OWrite data to EEPROM device. It is manually accessible thru the 
Configuration Register REGB.
EEDO M12 IRead data from EEPROM device with internal pull-down resistor. It is 
manually accessible thru the Configuration Register REGB.
JTAG SIGNALS
TRST# N4 IJTAG Test Reset. This signal is active LOW with internal pull-up resistor.
TCK P3 IJTAG Test Clock
TMS M5 IJTAG Test Mode Select with internal pull-up resistor
TDI R3 IJTAG Data Input with internal pull-up resistor
TDO P4 OJTAG Data Output
BUCK REGULATOR SIGNALS
ENABLE C14 ILogic ’1’ enables, logic ’0’ disables buck regulator output.
LX
LX
A13
A14
O
O
Output of internal buck regulator. Use 4.7 uH inductor and connect to FB pin
as shown in Figure 3.
FB C11 IBuck regulator feedback. Decouple with 47uF capacitor and connect to LX
pins through 4.7 uH inductor as shown in Figure 3.
PWRGD D13 OAsserted when the 1.2V internal buck voltage is powered up and within 
regulation.
ANCILLARY SIGNALS
RESET# R2 ISystem reset (active low). In normal operation, this signal should be HIGH.
TMRCK A10 I16-bit timer/counter external clock input.
EN485# C10 IAuto RS-485 mode enable (active low). This pin is sampled during power up,
following a hardware reset (RST#) or soft reset (register RESET). It can be
used to start up all 8 UARTs in the Auto RS-485 Half-Duplex Direction control
mode. The sampled logic state is transferred to FCTR bit-5 in the UART
channel.
ENIR# B10 IInfrared mode enable (active low). This pin is sampled during power up, 
following a hardware reset (RST#) or soft-reset (register RESET). It can be
used to start up all 8 UARTs in the infrared mode. The sampled logic state is
transferred to MCR bit-6 in the UART.
PIN DESCRIPTIONS
NAME PIN # TYPE DESCRIPTION

XR17V358
10
HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6
NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain, OT=Output Tristate, 
IS=Input Schmitt Trigger.
TEST0
TEST1
TEST2
F2
B11
A11
I
I
I
Factory Test Modes. For normal operation, connect to GND.
POWER / GROUND / NO CONNECT
VCC33 D5, D9, E12,
J12, M7
Pwr 3.3V I/O power supply.
VCC33A K3 Pwr 3.3V analog PHY power supply. A ferrite bead is recommended on this pin.
VCC33P B13, C13 Pwr 3.3V power supply voltage for output stage of buck regulator.
VCC33B B14, B15 Pwr 3.3V power supply for the analog blocks of the buck regulator.
VCC12 D7, D11, E4,
G12, K4, L12,
M9
Pwr 1.2V core power supply. A ferrite bead is recommended on these pins.
VCC12A K2 Pwr 1.2V analog PHY power supply. A ferrite bead is recommended on this pin.
GND A4, A8, A12,
B12, C12, D4,
D6, D8, D10,
D12, F1, F4,
F12, G3, H1,
H2, H12, H15,
J3, J4, K1, K12,
L4, M1, M6,
M8, M10, M15,
R4, R8, R12
Pwr Power supply common, ground.
NC A1, A15, R1,
R15
-No internal connection.
PIN DESCRIPTIONS
NAME PIN # TYPE DESCRIPTION

XR17V358
11
REV. 1.0.6 HIGH PERFORMANCE OCTAL PCI EXPRESS UART
FUNCTIONAL DESCRIPTION
The XR17V358 integrates the functions of eight independent enhanced 16550 UARTs, a general purpose 16-
bit timer/counter, and 16 multi-purpose I/Os (MPIOs). Each UART channel has its own 16550 UART
compatible configuration register set for individual channel control, status and data transfer. The device
configuration registers include a set of four consecutive interrupt source registers that provides interrupt status
for all eight UARTs, timer/counter, MPIOs and a sleep wake-up indicator. Additionally, each UART channel has
256-byte of transmit and receive FIFOs, automatic RTS/CTS or DTR/DSR hardware flow control, automatic
XON/XOFF, special character flow control, programmable transmit and receive FIFO trigger levels, infrared
encoder/decoder (IrDA ver. 1.1), and a programmable fractional baud rate generator with a prescaler of divide
by 1 or 4, and a data rate up to 31.25 Mbps with the 4X sampling rate.
PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
A set of local bus configuration space register is provided. These registers provide the PCI vendor ID, device
ID, sub-vendor ID, product model number, resources and capabilities which is collected by the host during the
auto configuration phase that follows immediately after a power up or system reset/reboot. After the host has
sorted out all devices on the bus, it defines and download the operating conditions to the cards. One of the
definitions is the base address loaded into the Base Address Register (BAR) where the card will be operating
in the PCI local bus memory space. All this is described in more detail in “Section 1.1, PCI LOCAL BUS
CONFIGURATION SPACE REGISTERS” on page 12.
EEPROM INTERFACE
An external 93C46 EEPROM is used to store words of information such as PCI Vendor ID, PCI Device ID,
Class Code, etc. Details of this information can be found in “Section 1.2, EEPROM Interface” on page 16. This
information is only used with the plug-and-play auto configuration of the PCI local bus. These data provide
automatic hardware installation onto the PCI bus. The EEPROM interface consists of 4 signals, EEDI, EEDO,
EECS, and EECK. The EEPROM is not needed when auto configuration is not required in the application.
However, if your design requires non-volatile memory for other purpose, it is possible to store and retrieve data
on the EEPROM through a special PCI device configuration register. See application note DAN112 for its
programming details.
EXPANSION INTERFACE
The expansion interface of the XR17V354 is used to connect a master device to a slave device in order to add
additional UART ports. All pins of the expansion interface must be connected between the two devices or to
logic levels as specified in the pin descriptions for each of the signals.
BUCK REGULATOR
The on chip buck regulator provides a 1.2V output from the device when enabled. This voltage can in turn be
used to provide power to the digital core and analog Phy as depicted in Figure 3.
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FIGURE 3. BUCK REGULATOR

XR17V358
12
HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6
1.0 XR17V358 INTERNAL REGISTERS
The XR17V358 UART register set is very similar to the previous generation PCI UARTs. This makes the
XR17V358 software compatible with the previous generation PCI UARTs. Minimal changes are needed to the
software driver of an existing Exar PCI UART driver so that it can be used with the XR17V358 PCIe UART.
There are three different sets of registers as shown in Figure 4. The PCI Local Bus Configuration Space
Registers are needed for plug-and-play auto-configuration. This auto-configuration feature makes installation
very easy into a PCI system and it is part of the PCI local bus specification. The second register set is the
Device Configuration Registers that are also accessible directly from the PCI bus for programming general
operating conditions of the device and monitoring the status of various functions common to all eight channels.
These functions include all 8 channel UARTs’ interrupt control and status, 16-bit general purpose timer control
and status, multipurpose inputs/outputs control and status, sleep mode, soft-reset, and device identification
and revision. And lastly, each UART channel has its own set of internal UART Configuration Registers for its
own operation control and status reporting. All 8 sets of channel registers are embedded inside the device
configuration registers space, which provides faster access. The second and third set of registers are mapped
into 8K of the PCI bus memory address space. The following paragraphs describe all 3 sets of registers in
detail.
FIGURE 4. THE XR17V358 REGISTER SETS
Channel 0
INT, M PIO ,
TIM ER , R EG
Device Configuration and
UART[7:0] Configuration
Registers are mapped on
to the Base Address
Register (BAR) in a 8K-
byte of memory address
space
PCI Local Bus
Interface
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Device Configuration Registers
8 channel Interrupts,
Multipurpose I/Os,
16-bit Timer/Counter,
Sleep, R eset, DVID, D R EV
UART[7:0] Configuration
Registers
16550 Compatible and EXAR
Enhanced Registers
PCI Local Bus
Configuration Space
Registers for Plug-
and-Play Auto
Configuration
Vendor and Sub-vendor ID
and Product Model Number
in External EEPROM
0x0000
0x0400
0x0800
0x0C00
0x1000
0x1400
0x1800
0x1C00
0x0080
0x1FFF
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
The PCI local bus configuration space registers are responsible for setting up the device’s operating
environment in the PCI local bus. The pre-defined operating parameters of the device is read by the PCI bus
plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data
from every device/card on the bus, it defines and downloads the memory mapping information to each device/
card about their individual operation memory address location and conditions. The operating memory mapped
address location is downloaded into the Base Address Register (BAR) register, located at an address offset of
0x10 in the configuration space. Custom modification of certain registers is possible by using an external
93C46 EEPROM. The EEPROM contains the device vendor and sub-vendor data, along with 6 other words of
information (see “Section 1.2, EEPROM Interface” on page 16) required by the auto-configuration setup.

XR17V358
13
REV. 1.0.6 HIGH PERFORMANCE OCTAL PCI EXPRESS UART
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
OFFSET BITS TYPE DESCRIPTION RESET VALUE (HEX OR BINARY)
0x00 31:16 EWR Device ID - No slave device on expansion interface
Device ID - XR17V358 slave device on expansion interface
Device ID - XR17V354 slave device on expansion interface
0x0358
0x8358
0x4358
15:0 EWR Vendor ID (Exar) specified by PCISIG 0x13A8
0x04 31
30
RWC
RWC
Parity error detected. Cleared by writing a logic 1.
System error detected. Cleared by writing a logic 1.
0b
0b
29:28 RO Unused 00b
27 RO Target Abort. 0b
26:25 RO DEVSEL# timing. 00b
24 RO Unimplemented bus master error reporting bit 0b
23 RO Fast back to back transactions are supported 0b
22 RO Reserved Status bit 0b
21 RO 66MHz capable 0b
20 RO Capabilities List 1b
19:16 RO Reserved Status bits 0000b
15:11,
9,7, 5,
4, 3, 2
RO Command bits (reserved) 0x0000
10 RWR This bit disables the device from asserting INTx#. logic 1 = 
disable assertion of INTx# and logic 0 = enables assertion of
INTx#
0b
8RWR SERR# driver enable. logic 1=enable driver and 0=disable driver 0b
6RWR Parity error enable. logic 1=respond to parity error and 0=ignore 0b
1RWR Command controls a device’s response to mem space accesses:
0=disable mem space accesses, 1=enable mem space accesses
0b
0RO Device’s response to I/O space accesses is disabled.
(0 = disable I/O space accesses)
0b
0x08 31:8 EWR Class Code (Default is ’Simple 550 Communication Controller’) 0x070002
7:0 RO Revision ID (Exar device revision number) Current Rev. value
0x0C 31:24 RO BIST (Built-in Self Test) 0x00
23:16 RO Header Type (a single function device with one BAR) 0x00
15:8 RO Unimplemented Latency Timer (needed only for bus master) 0x00
7:0 RO Unimplemented Cache Line Size 0x00

XR17V358
14
HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6
0x10 31:14 RWR Memory Base Address Register (BAR0) 0x00000
13:0 RO These 14 bits are hardwired to 0 in the XR17V358 to inform the
PCIe host to allocate 16k of memory space for accessing the
Device Configuration and UART Configuration Registers.
0x0000
0x14 31:0 RWR Unimplemented Base Address Register (returns zeros) 0x00000000
0x18h 31:0 RO Unimplemented Base Address Register (returns zeros) 0x00000000
0x1C 31:0 RO Unimplemented Base Address Register (returns zeros) 0x00000000
0x20 31:0 RO Unimplemented Base Address Register (returns zeros) 0x00000000
0x24 31:0 RO Unimplemented Base Address Register (returns zeros) 0x00000000
0x28 31:0 RO Reserved 0x00000000
0x2C 31:16 EWR Subsystem ID (write from external EEPROM by customer) 0x0000
15:0 EWR Subsystem Vendor ID (write from external EEPROM by 
customer)
0x0000
0x30 31:0 RO Expansion ROM Base Address (Unimplemented) 0x00000000
0x34 31:8 RO Reserved (returns zeros) 0x000000
7:0 RO Capability Pointer 0x50
0x38 31:0 RO Reserved (returns zeros) 0x00000000
0x3C 31:24 RO Unimplemented MAXLAT 0x00
23:16 RO Unimplemented MINGNT 0x00
15:8 RO Interrupt Pin, use INTA#. 0x01
7:0 RWR Interrupt Line. 0xXX
0x40 31:0 RO Not implemented or not applicable (return zeros) 0x00000000
0x44 31:0 RO CSR 0x02106160
0x48 31:0 RO Not implemented or not applicable (return zeros) 0x00000000
0x4C 31:0 RO Not implemented or not applicable (return zeros) 0x00000000
0x50 31:16 RO 64-bit address capable 0x0080
15:8 RO Next Capability Pointer 0x78
7:0 RO MSI Capable Capability ID 0x05
0x54-0x67 31:0 RO Not implemented or not applicable (return zeros) 0x00000000
0x68 31:0 RO Not implemented or not applicable 0x0000xxxx
0x6C-0x77 31:0 RO Not implemented or not applicable (return zeros) 0x00000000
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
OFFSET BITS TYPE DESCRIPTION RESET VALUE (HEX OR BINARY)

XR17V358
15
REV. 1.0.6 HIGH PERFORMANCE OCTAL PCI EXPRESS UART
0x78 31:16 RO PME# support (PME# can be asserted from D3hot and D0)
PCI Power Management 1.2
0x4803
15:8 RO Next Capability Pointer 0x80
7:0 RO Power Management Capability ID 0x01
0x7C 31:0 RO No soft reset when transitioning from D3hot to D0 state 0x00000008
0x80 31:16 RO PCI Express 2.0 capable endpoint, Interrupt Message Number 1 0x0202
15:8 RO Next Capability Pointer 0x00
7:0 RO PCI Express Capability ID 0x10
0x84 31:16 RO Not implemented or not applicable (return zeros) 0x0000
15:8 RO Role-Based Error Reporting 0x80
7:0 RO 256 bytes max payload size 0x01
0x88 31:16 RW Not implemented or not applicable (return zeros) 0x0000
15:8 RW 512 bytes max read request, Enable No Snoop 0x28
7:0 RW 256 bytes max TLP payload size 0x10
0x8C 31:24 RO Port Number 0x01
23:22 RO Not implemented or not applicable (return zeros) 00b
21:18 RO Not implemented or not applicable (return zeros) 0000b
17:15 RO L1 Exit Latency < 1 us 000b
14:12 RO L0s Exit Latency < 64 ns 000b
11:10 RO Active State Power Management (ASPM) Support
L0s and L1 Supported
11b
9:4 RO x1 max Link Width 000001b
3:0 RO 2.5 GT/s Link speed supported 0001b
0x90 31:21 RO Not implemented or not applicable (return zeros) 00000000000b
20 RO Data Link Layer Active Reporting capable 1b
19 RO Surprise Down Error Reporting not supported 0b
18 RO Reference clock must not be removed. 0b
17:15 RO L1 Exit Latency - 2 us to less than 4 us 010b
14:10 RO Not implemented or not applicable (return zeros) 00000b
9:4 RO x1 negotiated Link Width 000001b
3:0 RO Current Link Speed is 2.5 GT/s 0001b
0x94 31:0 RO PCIe Capability Offset 0x14 - Slot Capabilities Register 0x00040000
0x98-0xAF 31:0 RO Not implemented or not applicable (return zeros) 0x00000000
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
OFFSET BITS TYPE DESCRIPTION RESET VALUE (HEX OR BINARY)

XR17V358
16
HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6
NOTE: EWR=Read/Write from external EEPROM. RWR=Read/Write. RO= Read Only. RWC=Read/Write-Clear.
1.2 EEPROM Interface
The XR17V358 provides an interface to an Electrically Erasable Programmable Read Only Memory
(EEPROM). The EEPROM must be a 93C46-like device, with its memory configured as 16-bit words. This
interface is provided in order to program the registers in the PCI Configuration Space of the PCI UART during
power-up. The EEPROM must be organized into address/data pairs. The first word of the pair is the address
and the second word is the data. Ta ble 2 below shows the format of the 16-bit address:
TABLE 2: EEPROM ADDRESS BIT DEFINITIONS
BIT(S) DEFINITION
15 Parity Bit - Odd parity over entire address/data pair
If there is a parity error, it will be reported in bit-3 of the REGB register in
the Device Configuration Registers (offset 0x08E).
14 Final Address
If 1, this will be the last data to be read.
If 0, there will be more data to be read after this.
13:8 Reserved - Bits must be ’0’
7:0 Target Address - See Ta bl e 3
Tabl e 3 shows the Target Addresses available for programming into bits 7:0 of the 16-bit address word. All
other Target Addresses are reserved and must not be used.
TABLE 3: TARGET ADDRESS FOR EEPROM VALUES
TARGET ADDRESS DATA EXAR DEFAULT
0x00 Vendor ID 0x13A8
0x01 Device ID 0x0358 - No slave
0x4358 - XR17V354 slave present
0x8358 - XR17V358 slave present
0x02 Class Code [7:0]
lower 8-bits are reserved
0x0200
0x03 Class Code [23:8] 0x0700
0x04 Subsystem Vendor ID 0x0000
0x05 Subsystem ID 0x0000
0xB0 31:0 RO PCIe Capability Offset 0x30 - Link Status2/Control2 0x00010001
0xB4-0xFF 31:0 RO Not implemented or not applicable (return zeros) 0x00000000
0x100 31:0 RO VC Resource Capability Register 0x00010002
0x104-
0x113
31:0 RO Not implemented or not applicable (return zeros) 0x00000000
0x114 31:0 RO VC Offset 0x4 0x8000000FF
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
OFFSET BITS TYPE DESCRIPTION RESET VALUE (HEX OR BINARY)

XR17V358
17
REV. 1.0.6 HIGH PERFORMANCE OCTAL PCI EXPRESS UART
The second 16-bit word of the address/data pair is the data. The default values are shown in Ta b le 3. The
address/data pairs can be in any order. Only the contents which need to be changed from the Exar defaults
need to be included in the EEPROM.
1.3 Device Internal Register Sets
The Device Configuration Registers and the eight individual UART Configuration Registers of the
XR17V358 occupy 8K of PCI bus memory address space. These addresses are offset onto the basic memory
address, a value loaded into the Memory Base Address Register (BAR) in the PCI local bus configuration
register set. The UART Configuration Registers are mapped into 8 address blocks where each UART channel
occupies 1024 bytes memory space for its own registers that include the 16550 compatible registers. The
Device Configuration Registers are accessible from all UART channels. However, not all bits can be controlled
by all channels. The UART channel can only control the 8XMODE, 4XMODE, RESET and SLEEP register bits
that apply to that particular channel. For example, this prevents channel 0 from accidentally resetting channel
1.

XR17V358
18
HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6
TABLE 4: XR17V358 UART AND DEVICE CONFIGURATION REGISTERS
OFFSET ADDRESS MEMORY SPACE READ/WRITE COMMENT
0x0000 - 0x000F UART channel 0 Regs (Table 13 &
Tabl e 14)
First 8 regs are 16550 compatible
0x0010 - 0x007F Reserved
0x0080 - 0x009A DEVICE CONFIGURATION REGISTERS (Table 5)
0x009B - 0x00FF Reserved
0x0100 - 0x01FF UART 0 – Read FIFO Read-Only 256 bytes of RX FIFO data
0x0100 - 0x01FF UART 0 – Write FIFO Write-Only 256 bytes of TX FIFO data
0x0200 - 0x03FF UART 0 – Read FIFO with errors Read-Only 256 bytes of RX FIFO data + LSR
0x0400 - 0x040F UART channel 1 Regs (Table 13 &
Tabl e 14)
First 8 regs are 16550 compatible
0x0410 - 0x047F Reserved
0x0480 - 0x049A DEVICE CONFIGURATION REGISTERS (Table 5)
0x049B - 0x04FF Reserved
0x0500 - 0x05FF UART 1 – Read FIFO Read-Only 256 bytes of RX FIFO data
0x0500 - 0x05FF UART 1 – Write FIFO Write-Only 256 bytes of TX FIFO data
0x0600 - 0x07FF UART 1 – Read FIFO with errors Read-Only 256 bytes of RX FIFO data + LSR
0x0800 - 0x080F UART channel 2 Regs (Table 13 &
Tabl e 14)
First 8 regs are 16550 compatible
0x0810 - 0x087F Reserved
0x0880 - 0x089A DEVICE CONFIGURATION REGISTERS (Table 5)
0x089B - 0x08FF Reserved
0x0900 - 0x09FF UART 2 – Read FIFO Read-Only 256 bytes of RX FIFO data
0x0900 - 0x09FF UART 2 – Write FIFO Write-Only 256 bytes of TX FIFO data
0x0A00 - 0x0BFF UART 2 – Read FIFO with errors Read-Only 256 bytes of RX FIFO data + LSR
0x0C00 - 0x0C0F UART channel 3 Regs (Table 13 &
Tabl e 14)
First 8 regs are 16550 compatible
0x0C10 - 0x0C7F Reserved
0x0C80 - 0x0C9A DEVICE CONFIGURATION REGISTERS (Table 5)
0x0C9B - 0x0CFF Reserved
0x0D00 - 0x0DFF UART 3 – Read FIFO Read-Only 256 bytes of RX FIFO data
0x0D00 - 0x0DFF UART 3 – Write FIFO Write-Only 256 bytes of TX FIFO data
0x0E00 - 0x0FFF UART 3 – Read FIFO with errors Read-Only 256 bytes of RX FIFO data + LSR

XR17V358
19
REV. 1.0.6 HIGH PERFORMANCE OCTAL PCI EXPRESS UART
0x1000 - 0x100F UART channel 4 Regs (Table 13 &
Tabl e 14)
First 8 regs are 16550 compatible
0x1010 - 0x107F Reserved
0x1080 - 0x109A DEVICE CONFIGURATION REGISTERS (Table 5)
0x109B - 0x10FF Reserved
0x1100 - 0x11FF UART 4 – Read FIFO Read-Only 256 bytes of RX FIFO data
0x1100 - 0x11FF UART 4 – Write FIFO Write-Only 256 bytes of TX FIFO data
0x1200 - 0x13FF UART 4 – Read FIFO with errors Read-Only 256 bytes of RX FIFO data + LSR
0x1400 - 0x140F UART channel 5 Regs (Table 13 &
Tabl e 14)
First 8 regs are 16550 compatible
0x1410 - 0x147F Reserved
0x1480 - 0x149A DEVICE CONFIGURATION REGISTERS (Table 5)
0x149B - 0x14FF Reserved
0x1500 - 0x15FF UART 5 – Read FIFO Read-Only 256 bytes of RX FIFO data
0x1500 - 0x15FF UART 5 – Write FIFO Write-Only 256 bytes of TX FIFO data
0x1600 - 0x17FF UART 5 – Read FIFO with errors Read-Only 256 bytes of RX FIFO data + LSR
0x1800 - 0x180F UART channel 6 Regs (Table 13 &
Tabl e 14)
First 8 regs are 16550 compatible
0x1810 - 0x187F Reserved
0x1880 - 0x189A DEVICE CONFIGURATION REGISTERS (Table 5)
0x189B - 0x18FF Reserved
0x1900 - 0x19FF UART 6 – Read FIFO Read-Only 256 bytes of RX FIFO data
0x1900 - 0x19FF UART 6 – Write FIFO Write-Only 256 bytes of TX FIFO data
0x1A00 - 0x1BFF UART 6 – Read FIFO with errors Read-Only 256 bytes of RX FIFO data + LSR
0x1C00 - 0x1C0F UART channel 7 Regs (Table 13 &
Tabl e 14)
First 8 regs are 16550 compatible
0x1C10 - 0x1C7F Reserved
0x1C80 - 0x1C9A DEVICE CONFIGURATION REGISTERS (Table 5)
0x1C9B - 0x1CFF Reserved
0x1D00 - 0x1DFF UART 7 – Read FIFO Read-Only 256 bytes of RX FIFO data
0x1D00 - 0x1DFF UART 7 – Write FIFO Write-Only 256 bytes of TX FIFO data
0x1E00 - 0x1FFF UART 7 – Read FIFO with errors Read-Only 256 bytes of RX FIFO data + LSR
0x2000 - 0x3FFF UARTs 8-15 via expansion port
TABLE 4: XR17V358 UART AND DEVICE CONFIGURATION REGISTERS
OFFSET ADDRESS MEMORY SPACE READ/WRITE COMMENT

XR17V358
20
HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6
1.4 Device Configuration Registers
The Device Configuration Registers provide easy programming of general operating parameters to the
XR17V358 and for monitoring the status of various functions. These registers control or report on all 8 channel
UARTs functions that include interrupt control and status, 16-bit general purpose timer control and status,
multipurpose inputs/outputs control and status, sleep mode control, soft-reset control, and device identification
and revision, and others. Table 5 and Ta b le 6 below show these registers in BYTE and DWORD alignment.
Each of these registers is described in detail in the following paragraphs.
TABLE 5: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT
ADDRESS [A7:A0] REGISTER READ/WRITE COMMENT RESET STATE
0x080 INT0 [7:0] Read-only Interrupt [7:0] Bits [7:0] = 0x00
0x081 INT1 [15:8] Read-only Bits [7:0] = 0x00
0x082 INT2 [23:16] Read-only Bits [7:0] = 0x00
0x083 INT3 [31:24] Read-only Bits [7:0] = 0x00
0x084 TIMERCNTL Read/Write Timer Control Bits [7:0] = 0x00
0x085 REGA Reserved Bits [7:0] = 0x00
0x086 TIMERLSB Read/Write Timer LSB Bits [7:0]= 0x00
0x087 TIMERMSB Read/Write Timer MSB Bits [7:0]= 0x00
Individual UART channels can only control the bit
pertaining to that channel in the registers at address
offset 0x088-0x08B.
0x088 8XMODE Read/Write Bits [7:0] = 0x00
0x089 4XMODE Read/Write Bits [7:0] = 0x00
0x08A RESET Write-only Self clear bits after executing Reset Bits [7:0] = 0x00
0x08B SLEEP Read/Write Sleep mode Bits [7:0]= 0x00
0x08C DREV Read-only Device revision Bits [7:0] = Current Rev.
0x08D DVID Read-only Device identification Bits [7:0] = 0x88
0x08E REGB Read/Write EEPROM control Bits [7:0] = 0x00
0x08F MPIOINT[7:0] Read/Write MPIO[7:0] interrupt mask Bits [7:0] = 0x00
0x090 MPIOLVL[7:0] Read/Write MPIO[7:0] level control Bits [7:0] = 0x00
0x091 MPIO3T[7:0] Read/Write MPIO[7:0] output control Bits [7:0] = 0x00
0x092 MPIOINV[7:0] Read/Write MPIO[7:0] input polarity select Bits [7:0] = 0x00
0x093 MPIOSEL[7:0] Read/Write MPIO[7:0] select Bits [7:0] = 0xFF
0x094 MPIOOD[7:0] Read/Write MPIO[7:0] open-drain output control Bits [7:0] = 0x00
0x095 MPIOINT[15:8] Read/Write MPIO[15:8] interrupt mask Bits [15:8] = 0x00
0x096 MPIOLVL[15:8] Read/Write MPIO[15:8] level control Bits [15:8] = 0x00
0x097 MPIO3T[15:8] Read/Write MPIO[15:8] output control Bits [15:8] = 0x00