Tews Technologies TCP201 User manual

The Embedded I/O Company
TCP201
Compact PCI IP Carrier
Version 1.0
User Manual
Issue 1.4
September 2006
TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC
Am Bahnhof 7
25469 Halstenbek, Germany
www.tews.com
Phone: [phone]
Fax: [phone]
e-mail: [email protected]
9190 Double Diamond Parkway,
Suite 127, Reno, NV 89521, USA
www.tews.com
Phone: [phone]
Fax: [phone]
e-mail: [email protected]

TCP201 User Manual Issue 1.4 Page 2 of 35
TCP201-10
Compact PCI Carrier for 4 IndustryPack®
modules
This document contains information, which is
proprietary to TEWS TECHNOLOGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accurate and
complete. However TEWS TECHNOLOGIES GmbH
reserves the right to change the product described
in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x,
i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‚Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
W Write Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
2002-2006 by TEWS TECHNOLOGIES GmbH
IndustryPack is a registered trademark of SBS Technologies, Inc

TCP201 User Manual Issue 1.4 Page 3 of 35
Issue Description Date
1.0 Initial Issue October 2002
1.1 Corrections in Chapter Endian Conventions November 2002
1.2 General Revision March 2003
1.3 Correction Figure “ PCI to Local Byte lane swapping” November 2003
1.4 New address TEWS LLC September 2006

TCP201 User Manual Issue 1.4 Page 4 of 35
Table of Contents
1PRODUCT DESCRIPTION.........................................................................................6
2TECHNICAL SPECIFICATION...................................................................................7
3PCI INTERFACE.........................................................................................................8
3.1 PCI Configuration (CFG) Registers...............................................................................................9
3.1.1 PCI Header...........................................................................................................................9
3.1.2 PCI Base Address Initialization ..........................................................................................10
3.1.2.1 I/O Base Address Implementation..............................................................................11
3.1.2.2 Memory Base Address Implementation .....................................................................11
3.1.2.3 Expansion ROM Base Address Implementation........................................................12
3.2 Local Configuration Register.......................................................................................................13
3.3 Target Configuration EEPROM....................................................................................................14
3.4 Endian Conventions .....................................................................................................................15
3.4.1 Intel CPU View....................................................................................................................16
3.4.2 PowerPC CPU View...........................................................................................................17
3.4.3 Intel CPU View with TCP201 switched to Big Endian........................................................18
3.4.4 PowerPC CPU View with TCP201 switched to Big Endian................................................19
3.5 Big / Little Endian Mode setting ..................................................................................................20
4IP INTERFACE.........................................................................................................21
4.1 PCI9030 Local Space Assignment ..............................................................................................21
4.1.1 Local Space 0 Address Map...............................................................................................22
4.1.2 Local Space 1 Address Map...............................................................................................22
4.1.3 Local Space 2 Address Map...............................................................................................23
4.1.4 Local Space 3 Address Map...............................................................................................24
4.2 IP Interface Register .....................................................................................................................24
4.2.1 Revision ID Register...........................................................................................................24
4.2.2 IP Control Register .............................................................................................................25
4.2.3 IP Reset Register................................................................................................................29
4.2.4 IP Status Register...............................................................................................................29
4.3 IP Interrupts...................................................................................................................................31
5IP STROBE SIGNAL ................................................................................................32
6INSTALLATION OF INDUSTRYPACKS..................................................................33
7INDICATORS............................................................................................................34
7.1 ACK- and Power- LEDs.................................................................................................................34
7.2 Fuses and Filters...........................................................................................................................34
8PIN ASSIGNMENT...................................................................................................35
8.1 IP Connectors................................................................................................................................35

TCP201 User Manual Issue 1.4 Page 5 of 35
Table of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6
FIGURE 2-1 : TECHNICAL SPECIFICATION...................................................................................................7
FIGURE 3-1 : PCI CONFIGURATION REGISTER MAP..................................................................................9
FIGURE 3-2 : LOCAL CONFIGURATION REGISTERS.................................................................................13
FIGURE 3-3 : PCI9030 CONFIGURATION EEPROM CONTENT.................................................................14
FIGURE 3-4 : INTEL CPU VIEW.....................................................................................................................16
FIGURE 3-5 : POWERPC CPU VIEW............................................................................................................17
FIGURE 3-6 : INTEL CPU VIEW WITH TCP201 SWITCHED TO BIG ENDIAN............................................18
FIGURE 3-7 : POWERPC CPU VIEW WITH TCP201 SWITCHED TO BIG ENDIAN ...................................19
FIGURE 3-8 : PCI TO LOCAL BYTE LANE SWAPPING ...............................................................................20
FIGURE 4-1 : PCI9030 LOCAL SPACE ASSIGNMENT.................................................................................21
FIGURE 4-2 : LOCAL SPACE 0 ADDRESS MAP ..........................................................................................22
FIGURE 4-3 : LOCAL SPACE 1 ADDRESS MAP (IP A-D ID, INT, I/O SPACE)............................................22
FIGURE 4-4 : LOCAL SPACE 2 ADDRESS MAP (IP A-D MEMORY SPACE 16 BIT)..................................23
FIGURE 4-5 : LOCAL SPACE 3 ADDRESS MAP (IP A-D MEMORY SPACE 8 BIT)....................................24
FIGURE 4-6 : REVISION ID REGISTER (PCI BASE ADDRESS 2 + 0X00)..................................................24
FIGURE 4-7 : IP A CONTROL REGISTER (PCI BASE ADDRESS 2 + 0X02)...............................................25
FIGURE 4-8 : IP B CONTROL REGISTER (PCI BASE ADDRESS 2 + 0X04)...............................................26
FIGURE 4-9 : IP C CONTROL REGISTER (PCI BASE ADDRESS 2 +0X06) ...............................................27
FIGURE 4-10: IP D CONTROL REGISTER (PCI BASE ADDRESS 2 + 0X08) .............................................28
FIGURE 4-11: IP RESET REGISTER (PCI BASE ADDRESS 2 + 0X0A)......................................................29
FIGURE 4-12: IP STATUS REGISTER (PCI BASE ADDRESS 2 + 0X0C)....................................................31
FIGURE 5-1 : IP STROBE SIGNAL................................................................................................................32
FIGURE 6-1 : I/O PIN ORDER........................................................................................................................33
FIGURE 7-1 : IP ACK LED..............................................................................................................................34
FIGURE 7-2 : IP POWER LED........................................................................................................................34
FIGURE 8-1 : IP J1 LOGIC INTERFACE PIN ASSIGNMENT........................................................................35

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1 Product Description
The TCP201 is a standard 6U CompactPCI Carrier providing front I/O for up to 4 single-size or two
double-size IndustryPack (IP) modules used to build modular, flexible and cost effective I/O solutions
for applications in process control, medical systems, telecommunication and traffic control.
For improved EMI protection, four HD50 SCSI-2 type connectors (AMP 787395-5) are mounted in the
EMI front panel of the TCP201 and provide access to all IP I/O lines. Status indicators for IP access,
+5V and +/-12V are provided in the front panel.
The TCP201 can operate with 3.3V and 5.0V PCI I/O signaling voltage.
All IP interrupt request lines are mapped to PCI INTA. For fast interrupt source detection, the TCP201
provides a special IP Interrupt Status Register.
IP clock is selectable between 8 MHz and 32 MHz for each IP separately.
Two memory spaces are provided for each IP, allowing linear addressing for either 16 bit or 8 bit
memory on the IP.
The IP power lines are fuse protected by self healing fuses and RF filtered. The operating temperature
range is -40°C to +85°C.
The TCP201 complies with the PICMG 2.0 Revision 3.0 CompactPCI specification.
Figure 1-1 : Block Diagram

TCP201 User Manual Issue 1.4 Page 7 of 35
2Technical Specification
Compact PCI Interface Compact PCI 6U, conforming to PICMG 2.0 R3.0
PCI Interface PCI 2.2 compliant interface, 33 MHz, 32 bit
PCI I/O Signaling Voltage 3.3V or 5.0V
IP Interface According to IndustryPack specification ANSI / VITA 4-1995
IP Slots Four single-size or two double-size with I/O
IP Access 8 / 16 bit
8 / 32 MHz, selectable per IP
8Mbyte memory space per IP
Mapping of IP Interrupts All IP interrupts are mapped to PCI INTA, Local Interrupt Status
Register
I/O Access HD50 SCSI-2 type connector (AMP 787395-5) per IP, front panel
I/O
DMA
32 Bit Access Not supported
Not supported
Status LEDs ACK LED for each IP slot
+5V Power LED for each IP slot
+12V and –12V Power LED
Protection Self healing fuses and RF-filtering on all IP power lines
Power Requirements
without IP Modules 280mA typical @ + 5V DC
1mA typical @ + 12V DC
1mA typical @ -12V DC
Additional power is required by IP modules
Temperature Range Operating
Storage – 40°C to + 85°C – 40°C to + 85°C
MTBF 170766 h
Weight 310g
Size 160mm x 233.35mm
Humidity 5 – 95 % non-condensing
Figure 2-1 : Technical Specification

TCP201 User Manual Issue 1.4 Page 8 of 35
3 PCI Interface
The TCP201 is accessible in the PCI Memory space.
The PCI9030 PCI Target Chip from PLX Technology is used as PCI target device for accessing the IP
interface. A FPGA is used on the PCI9030 local bus to build the IP interface and provide IP interface
control registers.
The PCI9030 provides four local spaces 0:3 that are used for the IP interface.
Basic PCI9030 register configuration is loaded from a serial EEPROM after power-up or board reset.

TCP201 User Manual Issue 1.4 Page 9 of 35
3.1 PCI Configuration (CFG) Registers
3.1.1 PCI Header
Write ‘0’ to all unused (Reserved) bitsPCI CFG
Register
Address 31 24 23 16 15 8 7 0
PCI
write
able
Read after
initialization
write access
(hex values)
0x00 Device ID Vendor ID N 20C9 1498
0x04 Status Command Y 0280 0003
0x08 Class Code Revision ID N 068000 00
0x0C BIST Header Type
PCI Latency
Timer Cache line Size Y[7:0] 00 00 00 00
0x10 PCI Base Address 0 for Mem Mapped Configuration Registers Y FFFFFF80
0x14 PCI Base Address 1 for I/O Mapped Configuration Registers Y FFFFFF81
0x18 PCI Base Address 2 for Local Address Space 0 Y FFFFFF00
0x1C PCI Base Address 3 for Local Address Space 1 Y FFFFFC00
0x20 PCI Base Address 4 for Local Address Space 2 Y FE000000
0x24 PCI Base Address 5 for Local Address Space 3 Y FF000000
0x28 Cardbus CIS Pointer N 00000000
0x2C Subsystem ID Subsystem Vendor ID N 200A 1498
0x30 PCI Base Address for Local Expansion ROM Y 00000000
0x34 Reserved Next Cap P. N 000000 40
0x38 Reserved N 00000000
0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y[7:0] 00 00 01 00
0x40 Power Management Capabilities Next Cap
Pointer Capability ID N 4801 48 01
0x44 Data
PMCSR Bridge
Support
Extensions
Power Management
Control/Status Y 00 00 0000
0x48 Reserved Control/Status
Next_Cap
Pointer Capability ID Y[23:16] 00 02 4C 06
0x4C VPD Address Next_Cap
Pointer Capability ID Y[31:16] 0000 00 03
0x50 VPD Data Register Y 00000000
Figure 3-1 : PCI Configuration Register Map

TCP201 User Manual Issue 1.4 Page 10 of 35
3.1.2 PCI Base Address Initialization
PCI host bus-initialization software determines the required address space by an initialization write
access (writing a value of all ones ‘1’ to a PCI Base Address Register) and then reading back the
value of the PCI Base Address Register. The PCI9030 (PCI Target chip) returns zero ‘0’ in don’t care
address bits, specifying the required address space. The PCI software then maps the local address
space into the PCI address space by programming the PCI Base Address Register.
After programming the required address spaces the user must set bit 0 (enables I/O accesses) and bit
1 (enables memory accesses) of the Command Register (Offset 0x04) to ‘1’.

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3.1.2.1 I/O Base Address Implementation
1. Write a value of ‘1’ to all bits of the PCI Base Address Registers 0 to 5.
2. Check that bit 0 of the register contains a value of ‘1’ (PCI9030 needs an I/O address space).
3. Starting at bit location 2 of the PCI Base Address Register, search for the first bit set to a value of
‘1’. This bit is the binary size of the total contiguous block of I/O address space needed by the
PCI9030.
For example, if bit 5 of the PCI Base Address Register is detected as the first bit set to ‘1’, the
PCI9030 is requesting a 32 byte block of I/O address space.
4. Write the start address of the requested I/O address space to the PCI Base Address Register.
The PCI Base Address 1 for I/O Mapped Configuration Registers (128 byte) is used by the
TCP201 as I/O address space.
3.1.2.2 Memory Base Address Implementation
1. Write a value of ‘1’ to all bits of the PCI Base Address Registers 0 to 5.
2. Check that bit 0 of the register contains a value of ‘0’ (PCI9030 needs a memory address space).
3. Starting at bit location 4 of the PCI Base Address Register, search for the first bit set to a value of
‘1’. This bit is the binary size of the total contiguous block of memory address space needed by the
PCI9030.
For example, if bit 15 of the PCI Base Address Register is detected as the first bit set to ‘1’, the
PCI9030 is requesting a 32 kilobyte block of memory address space.
4. Write the start address of the requested memory address block to the PCI Base Address Register.
This memory address region must not conflict with any other memory space utilized within the
system. In addition, it must comply with the definition contained in bits 1 and 2 of this register.
The PCI Base Address 0 for Memory Mapped Configuration Registers (128 byte) and the PCI
Base Addresses 2 to 5 for Local Address Space 0 to 3 are used by the TCP201 as memory
address space.

TCP201 User Manual Issue 1.4 Page 12 of 35
3.1.2.3 Expansion ROM Base Address Implementation
5. Write a value of ‘1’ to bits 11 through 31 of PCI Base Address Local Expansion ROM Register.
6. Starting at bit location 11 of the PCI Base Address Local Expansion ROM Register, search upward
for the first bit set to a value of ‘1’. This bit is the binary size of the total contiguous block of memory
address space needed by the PCI9030.
For example, if bit 16 of the PCI Base Address Local Expansion ROM Register is detected as the
first bit set, the device is requesting a 64 kilobyte block of memory address space.
7. Write the start address of the requested memory address block to the PCI Base Address Local
Expansion ROM Register. This memory address region must not conflict with any other memory
space utilized within the system.
The Expansion ROM is not used by the TCP201.
For further information please refer to the PCI9030 manual which is also part of the TCP201-ED
Engineering Documentation.

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3.2Local Configuration Register
After reset, the Local Configuration Registers (LCRs) are loaded from the on board EEPROM. The
LCRs are accessible in the PCI Base Address 0 Memory Mapped or in the PCI Base Address 1 I/O
Mapped Configuration Registers.
Do not change the value of these registers because these values are hardware dependent.
PCI (Offset
from Local
Base
Address)
Register Value Description
0x00 Local Address Space 0 Range 0x0FFFFF00 IP Interface Register (256 byte)
0x04 Local Address Space 1 Range 0x0FFFFC00 IP A-D ID-, INT-, I/O-Space
(1kByte)
0x08 Local Address Space 2 Range 0x0E000000 IP A-D MEM Space (16 bit)
(32Mbyte)
0x0C Local Address Space 3 Range 0x0F000000 IP A-D MEM Space (8 bit)
(16Mbyte)
0x10 Local Exp. ROM Range 0x00000000 Not used
0x14 Local Re-map Register Space 0 0x08000001 Enabled
0x18 Local Re-map Register Space 1 0x04000001 Enabled
0x1C Local Re-map Register Space 2 0x00000001 Enabled
0x20 Local Re-map Register Space 3 0x02000001 Enabled
0x24 Local Re-map Register ROM 0x00000000 Not used
0x28 Local Address Space 0 Descriptor 0xD44160A0 Timing local Space 0
0x2C Local Address Space 1 Descriptor 0x144120A2 Timing local Space 1
0x30 Local Address Space 2 Descriptor 0x144120A2 Timing local Space 2
0x34 Local Address Space 3 Descriptor 0x140120A2 Timing local Space 3
0x38 Local Exp. ROM Descriptor 0x00000000 Not used
0x3C Chip Select 0 Base Address 0x08000081 CS for local Space 0
0x40 Chip Select 1 Base Address 0x04000201 CS for local Space 1
0x44 Chip Select 2 Base Address 0x01000001 CS for local Space 2
0x48 Chip Select 3 Base Address 0x02800001 CS for local Space 3
0x4C Interrupt Control/Status 0x00000041 Interrupt Configuration
0x4E EEPROM Write Protect Boundary 0x00000000 No write protection
0x50 Miscellaneous Control Register 0x007A4000 Retry Delay = max
0x54 General Purpose I/O Control 0x02249252 GPI/O2=CS2#
GPI/O3=CS3#
0x70 Hidden 1 Power Management data select 0x00000000 Not used
0x74 Hidden 2 Power Management data scale 0x00000000 Not used
Figure 3-2 : Local Configuration Registers

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3.3Target Configuration EEPROM
After reset, the PCI9030 starts to load the configuration sequence from the on board EEPROM.
This EEPROM contains the following configuration data.
•From 0x00 to 0x27 : PCI – Configuration
•From 0x28 to 0x87 : Local – Configuration
EEPROM Address 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E
0x00 0x20C9 0x1498 0x0280 0x0000 0x0680 0x0000 0x200A 0x1498
0x10 0x0000 0x0040 0x0000 0x0100 0x4801 0x0001 0x0000 0x0000
0x20 0x0000 0x4C06 0x0000 0x0003 0x0FFF 0xFF00 0x0FFF 0xFC00
0x30 0x0E00 0x0000 0x0F00 0x0000 0x0000 0x0000 0x0800 0x0001
0x40 0x0400 0x0001 0x0000 0x0001 0x0200 0x0001 0x0000 0x0000
0x50 0xD441 0x60A0 0x1441 0x20A2 0x1441 0x20A2 0x1401 0x20A2
0x60 0x0000 0x0000 0x0800 0x0081 0x0400 0x0201 0x0100 0x0001
0x70 0x0280 0x0001 0x0000 0x0041 0x007A 0x4000 0x0224 0x9252
0x80 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0x90 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0xA0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0xB0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0xC0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0xD0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0xE0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0xF0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
Figure 3-3 : PCI9030 Configuration EEPROM Content

TCP201 User Manual Issue 1.4 Page 15 of 35
3.4 Endian Conventions
This chapter tries to illuminate the mixed use of Big Endian and Little Endian convention in one
system. The major difference between Big Endian and Little Endian are swapped byte lanes. The
byte lanes for 16 bit and 32 bit data busses with Big Endian and Little Endian are shown below:
Little Endian convention on a 16 bit Data Bus:
Byte Lane Byte 1 Byte 0
Data Line D15 : D8 D7 : D0 (LSB)
Big Endian convention on a 16 bit Data Bus:
Byte Lane Byte 0 Byte 1
Data Line D15 : D8 D7 : D0 (LSB)
Little Endian convention on a 32 bit Data Bus:
Byte Lane Byte 3 Byte 2 Byte 1 Byte 0
Data Line D31 : D24 D23 : D16 D15 : D8 D7 : D0 (LSB)
Big Endian convention on a 32 bit Data Bus:
Byte Lane Byte 0 Byte 1 Byte 2 Byte 3
Data Line D31 : D24 D23 : D16 D15 : D8 D7 : D0 (LSB)
The PCI Bus and all Intel CPUs work in Little Endian mode. VMEbus, PowerPC and 68K CPUs
work in Big Endian mode. Most IP modules, which are common in VMEbus systems, also use Big
Endian byte ordering.
The TCP201 works in Little Endian mode by default, but can be switched to work in Big Endian
mode. This leads to 4 major Big- Little Endian combinations in one system:
- Little Endian CPU with TCP201 (Little Endian) and IP module (Big Endian)
- Little Endian CPU with TCP201 (Big Endian) and IP module (Big Endian)
- Big Endian CPU with TCP201 (Big Endian) and IP module (Big Endian)
- Big Endian CPU with TCP201 (Little Endian) and IP module (Big Endian)
See the next four subchapters for a detailed view on these combinations.

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3.4.1 Intel CPU View
Figure 3-4 : Intel CPU View

TCP201 User Manual Issue 1.4 Page 17 of 35
3.4.2 PowerPC CPU View
Figure 3-5 : PowerPC CPU View

TCP201 User Manual Issue 1.4 Page 18 of 35
3.4.3 Intel CPU View with TCP201 switched to Big Endian
Figure 3-6 : Intel CPU View with TCP201 switched to Big Endian

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3.4.4 PowerPC CPU View with TCP201 switched to Big Endian
Figure 3-7 : PowerPC CPU View with TCP201 switched to Big Endian

TCP201 User Manual Issue 1.4 Page 20 of 35
3.5 Big / Little Endian Mode setting
The PCI target chip of the TCP201, the PCI9030 can be set to convert to Big Endian data ordering
on the local bus. This is useful for IP modules that use Big Endian byte ordering. Big Endian byte
ordering is the convention used in the Motorola 68000 microprocessor family and is the VMEbus
convention.
Changing Local Space 0, 1 or 2 to Big Endian mode results in swapped data lines of the local bus:
A 32 bit access is separated by the PCI9030 into two local 16 bit accesses. Byte lane 0 and 1 are
swapped, and byte lane 2 and 3 are swapped.
During 16 bit access, the upper and lower bytes are displayed in reverse order.
During 8 bit access odd and even addresses are swapped. To access Address 0x00, the Address
0x01 must be used. An access to Address 0x01 is done by Address 0x00.
Figure 3-8 : PCI to Local Byte lane swapping
The local Endian mode of the PCI9030 can be changed for each local space separately. This is
done by changing the value of bit 24 in the corresponding Bus Region Descriptor Register:
To change local Space 0, that provides access to the local control and status registers, from Little
Endian to Big Endian mode, write 0xD5 to PCI BAR0 + 0x2B.
To change local Space 1, that provides access to IP I/O- ID and INT- Space, from Little Endian to
Big Endian mode, write 0x15 to PCI BAR0 + 0x2F.
To change local Space 2, that provides access to the IP MEM-Space (16 bit port), from Little
Endian to Big Endian mode, write 0x15 to PCI BAR0 + 0x33.
Changing local Space 3 from Little Endian to Big Endian mode has no effect, because this space
has only an 8 bit port.