Microsemi SmartTime User manual

SmartTime Static Timing Analyzer
User Guide
SmartFusion2, IGLOO2, RTG4, and PolarFire
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Table of Contents
About SmartTime (Enhanced Constraint Flow) .........................................................................7
Design Flows with SmartTime ...................................................................................................9
Starting and Closing SmartTime - SmartFusion2, IGLOO2, RTG4, and PolarFire .................10
SmartTime Components..........................................................................................................10
Setting SmartTime Options - SmartFusion2, IGLOO2, RTG4, and PolarFire.........................11
SmartTime Toolbar ..................................................................................................................13
SmartTime Timing Analyzer.....................................................................................................14
SmartTime Timing Analyzer........................................................................15
Components of the SmartTime Timing Analyzer.....................................................................16
Analyzing Your Design.............................................................................................................17
Performing a Bottleneck Analysis............................................................................................19
Managing Clock Domains........................................................................................................21
Managing Path Sets.................................................................................................................22
Displaying Path List Timing Information...................................................................................24
Displaying Expanded Path Timing Information........................................................................26
Using Filters .............................................................................................................................28
Advanced Timing Analysis .........................................................................31
Understanding Inter-Clock Domain Analysis ...........................................................................32
Activating Inter-Clock Domain Analysis...................................................................................33
Displaying Inter-Clock Domain Paths ......................................................................................34
Deactivating a Specific Inter-Clock Domain.............................................................................35
Changing Output Port Capacitance.........................................................................................36
Generating Timing Reports.........................................................................37
Types of Reports......................................................................................................................38
Generating a Timing Report.....................................................................................................39
Understanding Timing Reports ................................................................................................40
Generating a Timing Violation Report......................................................................................43
Understanding Timing Violation Reports .................................................................................44
Generating a Constraints Coverage Report ............................................................................46
Understanding Constraints Coverage Reports........................................................................47
Generating a Bottleneck Report...............................................................................................49
Understanding Bottleneck Reports - SmartFusion2, IGLOO2, RTG4, and PolarFire .............50
Generating a Datasheet Report...............................................................................................52
Understanding Datasheet Reports...........................................................................................53
Generating a Combinational Loop Report ...............................................................................55
Understanding Combinational Loop Reports...........................................................................56
Timing Concepts..........................................................................................57

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Static Timing Analysis Versus Dynamic Simulation.................................................................58
Timing Exceptions Overview....................................................................................................60
SmartTime Tutorials (Enhanced Constraints Flow).................................................................67
Dialog Boxes................................................................................................92
Add Path Analysis Set Dialog Box...........................................................................................93
Analysis Set Properties Dialog Box .........................................................................................95
Edit Filter Set Dialog Box.........................................................................................................96
Customize Analysis View Dialog Box ......................................................................................97
Manage Clock Domains Dialog Box ........................................................................................99
Set False Path Constraint Dialog Box....................................................................................100
SmartTime Options Dialog Box - SmartFusion2, IGLOO2, RTG4, and PolarFire.................102
Store Filter as Analysis Set Dialog Box .................................................................................105
Timing Bottleneck Analysis Options Dialog Box....................................................................106
Timing Datasheet Report Options Dialog Box.......................................................................110
Timing Report Options Dialog Box.........................................................................................111
Timing Violations Report Options Dialog Box........................................................................115
Data Change History - SmartTime............................................................117
Tcl Commands...........................................................................................118
create_set ..............................................................................................................................119
expand_path ..........................................................................................................................121
list_paths................................................................................................................................123
remove_set ............................................................................................................................125
report......................................................................................................................................126
save........................................................................................................................................130
set_options (SmartFusion2, IGLOO2, RTG4, and PolarFire)................................................131
Glossary .....................................................................................................134

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About SmartTime (Enhanced Constraint Flow)
SmartTime is the Libero SoC gate-level static timing analysis tool. With SmartTime, you can perform
complete timing analysis of your design to ensure that you meet all timing constraints and that your design
operates at the desired speed with the right amount of margin across all operating conditions.
Note: SmartTime in the Enhanced Constraint Flow has changed. Creation and Editing of timing constraints
are now handled in a separate Timing Constraints Editor. See the Timing Constraints Editor for help
with creating and editing timing constraints in the Enhanced Constraints Flow.
Static Timing Analysis (STA)
Static timing analysis (STA) offers an efficient technique for identifying timing violations in your design and
ensuring that it meets all your timing requirements. You can communicate timing requirements and timing
exceptions to the system by setting timing constraints. A static timing analysis tool will then check and report
setup and hold violations as well as violations on specific path requirements.
STA is particularly well suited for traditional synchronous designs. The main advantage of STA is that unlike
dynamic simulation, it does not require input vectors. It covers all possible paths in the design and does all
the above with relatively low run-time requirements.
The major disadvantage of STA is that the STA tools do not automatically detect false paths in their
algorithms as it reports all possible paths, including false paths, in the design. False paths are timing paths
in the design that do not propagate a signal. To get a true and useful timing analysis, you need to identify
those false paths, if any, as false path constraints to the STA tool and exclude them from timing
considerations.
The SmartTime user interface provides efficient, user-friendly ways to define these critical false paths.
Timing Constraints
SmartTime supports a range of timing constraints to provide useful analysis and efficient timing-driven
layout.
Timing Analysis
SmartTime provides a selection of analysis types that enable you to:
•Find the minimum clock period/highest frequency that does not result in a timing violations
•Identify paths with timing violations
•Analyze delays of paths that have no timing constraints
•Perform inter-clock domain timing verification
•Perform maximum and minimum delay analysis for setup and hold checks
To improve the accuracy of the results, SmartTime evaluates clock skew during timing analysis by
individually computing clock insertion delays for each register.
SmartTime checks the timing requirements for violations while evaluating timing exceptions (such as
multicycle or false paths).
SmartTime and Place and Route
Because Libero SoC Place and Route uses SmartTime STA during timing-driven place-and-route in the
background; your analysis and place and route constraints are always consistent.
SmartTime and Timing Reports
From SmartTime > Tools > Reports, the following report files can be generated:
•Timing Report (for both Max and Min Delay Analysis)
•Timing Violations Report (for both Max and Min Delay Analysis)
•Bottleneck Report
•Constraints Coverage Report
•Combinational Loop Report

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SmartTime and Cross-Probing into Chip Planner
From SmartTime, you can select a design object and cross-probe the same design object in Chip Planner.
Design objects that can be cross-probed from SmartTime to Chip Planner include:
•Ports
•Macros
•Timing Paths
SmartTime and Cross-Probing into Constraints Editor
From SmartTime, you can cross-probe into the Constraints Editor. Select a Timing Path in SmartTime’s
Analysis View and add a Timing Exception Constraint (False Path, Multicycle Path, Max Delay, Min Delay) .
The Constraint Editor reflects the newly added timing exception constraint.
The Constraints Editor must be running for Cross-Probing to work.
See Also
Starting and Closing SmartTime
Components of SmartTime Timing Analyzer
Changing SmartTime Preferences

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Design Flows with SmartTime
You can access SmartTime in Libero SoC either implicitly or explicitly during the following phases of design
implementation:
•During Place and Route – When you select timing-driven place-and-route, SmartTime runs in the
background to provide accurate timing information.
•After Place and Route – Run SmartTime to perform post-layout timing analysis and adjust timing
constraints. In the Libero SoC Design Flow window, expand Implement Design > Verify Post-Layout
Implementation. You can:
•Double-click Verify Timing to generate Timing Reports.
•Right-click Open SmartTime > Open Interactively to run SmartTime.
•During Back-Annotation – SmartTime runs in the background to generate the SDF file for timing
simulation.
You can also run SmartTime whenever you need to generate timing reports, regardless of which design
implementation phase you are in.
See Libero SoC for Enhanced Constraint Flow for more information about Place and Route and Back-
Annotation.

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Starting and Closing SmartTime - SmartFusion2, IGLOO2, RTG4, and
PolarFire You must have completed Place and Route for your design before using SmartTime interactively. If your
design has not yet been placed-and-routed, Libero SoC will complete that phase prior to starting SmartTime.
To open SmartTime interactively, in Implement Design > Verify Post Layout Implementation right-click
Open SmartTime > Open Interactively.
SmartTime reads your design and displays post- or pre-layout timing information.
To close SmartTime, from the File menu, choose Exit.
SmartTime Components
•The Maximum Delay Analysis View and the Minimum Delay Analysis View enable you to
analyze your design
With SmartTime, you can:
•Browse through your design’s various clock domains to examine the timing paths and identify those
that violate your timing requirements
•Create customizable timing reports
•Navigate directly to the paths responsible for violating your timing requirements