Mips Technologies MIPS32 M14K User manual

Document Number: MD00668
Revision 02.04
March 24, 2014
MIPS32® M14K™ Processor Core Family
Software User’s Manual

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MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 3

4 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04

MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 1
Table of Contents
Chapter 1: Introduction to the MIPS32® M14K™ Processor Core.....................................................4
1.1: Features ......................................................................................................................................................4
1.2: M14K™ Core Block Diagram ......................................................................................................................8
1.2.1: Required Logic Blocks .......................................................................................................................9
1.2.1.1: Execution Unit ..........................................................................................................................9
1.2.1.2: General Purposed Register (GPR) Shadow Registers........................................................... 10
1.2.1.3: Multiply/Divide Unit (MDU) .....................................................................................................10
1.2.1.4: System Control Coprocessor (CP0) .......................................................................................10
1.2.1.5: Memory Management Unit (MMU) ......................................................................................... 12
1.2.1.6: SRAM Interface Controller...................................................................................................... 14
1.2.1.7: Power Management ...............................................................................................................15
1.2.2: Optional Logic Blocks....................................................................................................................... 16
1.2.2.1: Reference Design...................................................................................................................16
1.2.2.2: microMIPS™ ISA.................................................................................................................... 17
1.2.2.3: Memory Protection Unit.......................................................................................................... 17
1.2.2.4: Coprocessor 2 Interface .........................................................................................................17
1.2.2.5: CorExtend® User-defined Instruction Extensions..................................................................18
1.2.2.6: EJTAG Debug Support...........................................................................................................18
Chapter 2: Pipeline of the M14K™ Core.............................................................................................22
2.1: Pipeline Stages..........................................................................................................................................22
2.1.1: I Stage: Instruction Fetch.................................................................................................................24
2.1.2: E Stage: Execution...........................................................................................................................24
2.1.3: M Stage: Memory Fetch...................................................................................................................24
2.1.4: A Stage: Align ..................................................................................................................................25
2.1.5: W Stage: Writeback .........................................................................................................................25
2.2: Multiply/Divide Operations......................................................................................................................... 25
2.3: MDU Pipeline - High-performance MDU ...................................................................................................25
2.3.1: 32x16 Multiply (High-Performance MDU) ........................................................................................28
2.3.2: 32x32 Multiply (High-Performance MDU) ........................................................................................29
2.3.3: Divide (High-Performance MDU) .....................................................................................................29
2.4: MDU Pipeline - Area-Efficient MDU...........................................................................................................30
2.4.1: Multiply (Area-Efficient MDU)...........................................................................................................31
2.4.2: Multiply Accumulate (Area-Efficient MDU)....................................................................................... 32
2.4.3: Divide (Area-Efficient MDU)............................................................................................................. 32
2.5: Branch Delay.............................................................................................................................................32
2.6: Data Bypassing .........................................................................................................................................33
2.6.1: Load Delay.......................................................................................................................................34
2.6.2: Move from HI/LO and CP0 Delay..................................................................................................... 35
2.7: Coprocessor 2 Instructions........................................................................................................................ 35
2.8: Interlock Handling...................................................................................................................................... 36
2.9: Slip Conditions...........................................................................................................................................37
2.10: Instruction Interlocks................................................................................................................................38
2.11: Hazards................................................................................................................................................... 39
2.11.1: Types of Hazards...........................................................................................................................39
2.11.2: Instruction Listing...........................................................................................................................40
2.11.2.1: Instruction Encoding.............................................................................................................41

2 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04
2.11.3: Eliminating Hazards.......................................................................................................................41
Chapter 3: Memory Management of the M14K™ Core......................................................................43
3.1: Introduction................................................................................................................................................ 43
3.1.1: Memory Management Unit (MMU) ..................................................................................................43
3.1.1.1: Fixed Mapping Translation (FMT) ..........................................................................................43
3.2: Modes of Operation...................................................................................................................................44
3.2.1: Virtual Memory Segments................................................................................................................44
3.2.1.1: Unmapped Segments.............................................................................................................45
3.2.1.2: Mapped Segments .................................................................................................................46
3.2.2: User Mode........................................................................................................................................46
3.2.3: Kernel Mode.....................................................................................................................................47
3.2.3.1: Kernel Mode, User Space (kuseg) .........................................................................................49
3.2.3.2: Kernel Mode, Kernel Space 0 (kseg0)....................................................................................49
3.2.3.3: Kernel Mode, Kernel Space 1 (kseg1)....................................................................................49
3.2.3.4: Kernel Mode, Kernel Space 2 (kseg2)....................................................................................49
3.2.3.5: Kernel Mode, Kernel Space 3 (kseg3)....................................................................................49
3.2.4: Debug Mode.....................................................................................................................................49
3.2.4.1: Conditions and Behavior for Access to drseg, EJTAG Registers...........................................50
3.2.4.2: Conditions and Behavior for Access to dmseg, EJTAG Memory ........................................... 51
3.3: Fixed Mapping MMU .................................................................................................................................51
3.4: System Control Coprocessor.....................................................................................................................53
Chapter 4: Exceptions and Interrupts in the M14K™ Core...............................................................55
4.1: Exception Conditions................................................................................................................................. 55
4.2: Exception Priority.......................................................................................................................................56
4.3: Interrupts ...................................................................................................................................................57
4.3.1: Interrupt Modes................................................................................................................................57
4.3.1.1: Interrupt Compatibility Mode................................................................................................... 58
4.3.1.2: Vectored Interrupt (VI) Mode.................................................................................................. 60
4.3.1.3: External Interrupt Controller Mode .........................................................................................63
4.3.2: Generation of Exception Vector Offsets for Vectored Interrupts...................................................... 66
4.3.3: MCU ASE Enhancement for Interrupt Handling...............................................................................67
4.3.3.1: Interrupt Delivery ....................................................................................................................67
4.3.3.2: Interrupt Latency Reduction ...................................................................................................67
4.4: GPR Shadow Registers.............................................................................................................................68
4.5: Exception Vector Locations.......................................................................................................................69
4.6: General Exception Processing.................................................................................................................. 71
4.7: Debug Exception Processing ....................................................................................................................73
4.8: Exception Descriptions..............................................................................................................................74
4.8.1: Reset/SoftReset Exception..............................................................................................................74
4.8.2: Debug Single Step Exception ..........................................................................................................75
4.8.3: Debug Interrupt Exception ...............................................................................................................76
4.8.4: Non-Maskable Interrupt (NMI) Exception.........................................................................................76
4.8.5: Interrupt Exception...........................................................................................................................77
4.8.6: Debug Instruction Break Exception..................................................................................................77
4.8.7: Address Error Exception — Instruction Fetch/Data Access.............................................................77
4.8.8: SRAM Parity Error Exception...........................................................................................................78
4.8.9: Bus Error Exception — Instruction Fetch or Data Access................................................................ 78
4.8.10: Protection Exception......................................................................................................................79
4.8.11: Debug Software Breakpoint Exception ..........................................................................................79
4.8.12: Execution Exception — System Call..............................................................................................79
4.8.13: Execution Exception — Breakpoint................................................................................................80

MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 3
4.8.14: Execution Exception — Reserved Instruction................................................................................ 80
4.8.15: Execution Exception — Coprocessor Unusable ............................................................................80
4.8.16: Execution Exception — CorExtend Unusable................................................................................81
4.8.17: Execution Exception — Coprocessor 2 Exception.........................................................................81
4.8.18: Execution Exception — Implementation-Specific 1 Exception.......................................................81
4.8.19: Execution Exception — Integer Overflow....................................................................................... 82
4.8.20: Execution Exception — Trap.......................................................................................................... 82
4.8.21: Debug Data Break Exception.........................................................................................................82
4.8.22: Complex Break Exception..............................................................................................................83
4.9: Exception Handling and Servicing Flowcharts ..........................................................................................83
Chapter 5: CP0 Registers of the M14K™ Core ..................................................................................88
5.1: CP0 Register Summary............................................................................................................................. 88
5.2: CP0 Register Descriptions ........................................................................................................................90
5.2.1: UserLocal Register (CP0 Register 4, Select 2)................................................................................90
5.2.2: HWREna Register (CP0 Register 7, Select 0)................................................................................. 91
5.2.3: BadVAddr Register (CP0 Register 8, Select 0)................................................................................ 92
5.2.4: BadInstr Register (CP0 Register 8, Select 1)................................................................................... 92
5.2.5: BadInstrP Register (CP0 Register 8, Select 2)................................................................................93
5.2.6: Count Register (CP0 Register 9, Select 0) ......................................................................................94
5.2.7: Compare Register (CP0 Register 11, Select 0)...............................................................................94
5.2.8: Status Register (CP0 Register 12, Select 0)....................................................................................95
5.2.9: IntCtl Register (CP0 Register 12, Select 1)...................................................................................... 99
5.2.10: SRSCtl Register (CP0 Register 12, Select 2)..............................................................................103
5.2.11: SRSMap Register (CP0 Register 12, Select 3)............................................................................ 106
5.2.12: View_IPL Register (CP0 Register 12, Select 4)...........................................................................107
5.2.13: SRSMap2 Register (CP0 Register 12, Select 5).......................................................................... 107
5.2.14: Cause Register (CP0 Register 13, Select 0)................................................................................ 108
5.2.15: View_RIPL Register (CP0 Register 13, Select 4)........................................................................113
5.2.16: NestedExc (CP0 Register 13, Select 5)....................................................................................... 113
5.2.17: Exception Program Counter (CP0 Register 14, Select 0)............................................................ 114
5.2.18: NestedEPC (CP0 Register 14, Select 2)...................................................................................... 115
5.2.19: Processor Identification (CP0 Register 15, Select 0)................................................................... 116
5.2.20: EBase Register (CP0 Register 15, Select 1) ...............................................................................117
5.2.21: CDMMBase Register (CP0 Register 15, Select 2)....................................................................... 118
5.2.22: Config Register (CP0 Register 16, Select 0)................................................................................ 119
5.2.23: Config1 Register (CP0 Register 16, Select 1).............................................................................. 121
5.2.24: Config2 Register (CP0 Register 16, Select 2).............................................................................. 122
5.2.25: Config3 Register (CP0 Register 16, Select 3).............................................................................. 123
5.2.26: Config4 Register (CP0 Register 16, Select 4).............................................................................. 126
5.2.27: Config5 Register (CP0 Register 16, Select 5).............................................................................. 126
5.2.28: Config7 Register (CP0 Register 16, Select 7).............................................................................. 127
5.2.29: Debug Register (CP0 Register 23, Select 0) ...............................................................................127
5.2.30: Trace Control Register (CP0 Register 23, Select 1)....................................................................132
5.2.31: Trace Control2 Register (CP0 Register 23, Select 2)..................................................................134
5.2.32: User Trace Data1 Register (CP0 Register 23, Select 3)/User Trace Data2 Register (CP0 Register
24, Select 3).............................................................................................................................................135
5.2.33: TraceBPC Register (CP0 Register 23, Select 4) .........................................................................136
5.2.34: Debug2 Register (CP0 Register 23, Select 6) .............................................................................137
5.2.35: Debug Exception Program Counter Register (CP0 Register 24, Select 0).................................. 138
5.2.36: Performance Counter Register (CP0 Register 25, select 0-3)..................................................... 139
5.2.37: ErrCtl Register (CP0 Register 26, Select 0).................................................................................144
5.2.38: CacheErr Register (CP0 Register 27, Select 0)...........................................................................144

4 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04
5.2.39: ErrorEPC (CP0 Register 30, Select 0)......................................................................................... 145
5.2.40: DeSave Register (CP0 Register 31, Select 0).............................................................................146
5.2.41: KScratchn Registers (CP0 Register 31, Selects 2 to 3)...............................................................146
Chapter 6: Hardware and Software Initialization of the M14K™ Core...........................................149
6.1: Hardware-Initialized Processor State......................................................................................................149
6.1.1: Coprocessor 0 State ......................................................................................................................149
6.1.2: Bus State Machines.......................................................................................................................150
6.1.3: Static Configuration Inputs.............................................................................................................150
6.1.4: Fetch Address................................................................................................................................150
6.2: Software Initialized Processor State........................................................................................................ 150
6.2.1: Register File...................................................................................................................................150
6.2.2: Coprocessor 0 State ......................................................................................................................150
Chapter 7: Power Management of the M14K™ Core.......................................................................153
7.1: Register-Controlled Power Management ................................................................................................153
7.2: Instruction-Controlled Power Management.............................................................................................154
Chapter 8: EJTAG Debug Support in the M14K™ Core..................................................................155
8.1: Debug Control Register...........................................................................................................................155
8.2: Hardware Breakpoints.............................................................................................................................160
8.2.1: Data Breakpoints............................................................................................................................161
8.2.2: Complex Breakpoints.....................................................................................................................161
8.2.3: Conditions for Matching Breakpoints .............................................................................................161
8.2.3.1: Conditions for Matching Instruction Breakpoints .................................................................. 161
8.2.3.2: Conditions for Matching Data Breakpoints ........................................................................... 163
8.2.4: Debug Exceptions from Breakpoints..............................................................................................165
8.2.4.1: Debug Exception by Instruction Breakpoint.......................................................................... 165
8.2.4.2: Debug Exception by Data Breakpoint................................................................................... 165
8.2.5: Breakpoint Used as Triggerpoint.................................................................................................... 166
8.2.6: Instruction Breakpoint Registers....................................................................................................166
8.2.6.1: Instruction Breakpoint Status (IBS) Register (0x1000).........................................................167
8.2.6.2: Instruction Breakpoint Address n (IBAn) Register (0x1100 + n * 0x100)..............................167
8.2.6.3: Instruction Breakpoint Address Mask n (IBMn) Register (0x1108 + n*0x100) ..................... 168
8.2.6.4: Instruction Breakpoint ASID n (IBASIDn) Register (0x1110 + n*0x100) .............................. 168
8.2.6.5: Instruction Breakpoint Control n (IBCn) Register (0x1118 + n*0x100).................................168
8.2.6.6: Instruction Breakpoint Complex Control n (IBCCn) Register (0x1120 + n*0x100)............... 170
8.2.6.7: Instruction Breakpoint Pass Counter n (IBPCn) Register (0x1128 + n*0x100) .................... 170
8.2.7: Data Breakpoint Registers.............................................................................................................171
8.2.7.1: Data Breakpoint Status (DBS) Register (0x2000) ................................................................ 172
8.2.7.2: Data Breakpoint Address n (DBAn) Register (0x2100 + 0x100 * n).....................................172
8.2.7.3: Data Breakpoint Address Mask n (DBMn) Register (0x2108 + 0x100 * n)........................... 173
8.2.7.4: Data Breakpoint ASID n (DBASIDn) Register (0x2110 + 0x100 * n).................................... 173
8.2.7.5: Data Breakpoint Control n (DBCn) Register (0x2118 + 0x100 * n) ...................................... 173
8.2.7.6: Data Breakpoint Value n (DBVn) Register (0x2120 + 0x100 * n)......................................... 175
8.2.7.7: Data Breakpoint Complex Control n (DBCCn) Register (0x2128 + n*0x100).......................176
8.2.7.8: Data Breakpoint Pass Counter n (DBPCn) Register (0x2130 + n*0x100)............................ 177
8.2.7.9: Data Value Match (DVM) Register (0x2ffo).......................................................................... 177
8.2.8: Complex Breakpoint Registers....................................................................................................... 178
8.2.8.1: Complex Break and Trigger Control (CBTC) Register (0x8000) .......................................... 178
8.2.8.2: Priming Condition A (PrCndAI/Dn) Registers....................................................................... 179
8.2.8.3: Stopwatch Timer Control (STCtl) Register (0x8900)............................................................ 181

MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 5
8.2.8.4: Stopwatch Timer Count (STCnt) Register (0x8908).............................................................182
8.3: Complex Breakpoint Usage..................................................................................................................... 182
8.3.1: Checking for Presence of Complex Break Support........................................................................ 182
8.3.2: General Complex Break Behavior.................................................................................................. 183
8.3.3: Usage of Pass Counters................................................................................................................183
8.3.4: Usage of Tuple Breakpoints...........................................................................................................184
8.3.5: Usage of Priming Conditions.......................................................................................................... 184
8.3.6: Usage of Data Qualified Breakpoints.............................................................................................185
8.3.7: Usage of Stopwatch Timers...........................................................................................................185
8.4: Test Access Port (TAP)...........................................................................................................................186
8.4.1: EJTAG Internal and External Interfaces......................................................................................... 186
8.4.2: Test Access Port Operation...........................................................................................................187
8.4.2.1: Test-Logic-Reset State.........................................................................................................188
8.4.2.2: Run-Test/Idle State............................................................................................................... 188
8.4.2.3: Select_DR_Scan State.........................................................................................................188
8.4.2.4: Select_IR_Scan State ..........................................................................................................188
8.4.2.5: Capture_DR State ................................................................................................................189
8.4.2.6: Shift_DR State......................................................................................................................189
8.4.2.7: Exit1_DR State.....................................................................................................................189
8.4.2.8: Pause_DR State...................................................................................................................189
8.4.2.9: Exit2_DR State.....................................................................................................................189
8.4.2.10: Update_DR State ...............................................................................................................189
8.4.2.11: Capture_IR State................................................................................................................190
8.4.2.12: Shift_IR State .....................................................................................................................190
8.4.2.13: Exit1_IR State..................................................................................................................... 190
8.4.2.14: Pause_IR State ..................................................................................................................190
8.4.2.15: Exit2_IR State..................................................................................................................... 190
8.4.2.16: Update_IR State.................................................................................................................190
8.4.3: Test Access Port (TAP) Instructions..............................................................................................190
8.4.3.1: BYPASS Instruction.............................................................................................................. 191
8.4.3.2: IDCODE Instruction.............................................................................................................. 191
8.4.3.3: IMPCODE Instruction ...........................................................................................................191
8.4.3.4: ADDRESS Instruction........................................................................................................... 191
8.4.3.5: DATA Instruction ..................................................................................................................192
8.4.3.6: CONTROL Instruction ..........................................................................................................192
8.4.3.7: ALL Instruction...................................................................................................................... 192
8.4.3.8: EJTAGBOOT Instruction ......................................................................................................192
8.4.3.9: NORMALBOOT Instruction ..................................................................................................192
8.4.3.10: FASTDATA Instruction .......................................................................................................193
8.4.3.11: PCsample Register (PCSAMPLE Instruction).................................................................... 193
8.4.3.12: FDC Instruction................................................................................................................... 193
8.4.3.13: TCBCONTROLA Instruction...............................................................................................193
8.4.3.14: TCBCONTROLB Instruction...............................................................................................193
8.4.3.15: TCBDATA Instruction .........................................................................................................193
8.5: EJTAG TAP Registers............................................................................................................................. 193
8.5.1: Instruction Register........................................................................................................................193
8.5.2: Data Registers Overview ...............................................................................................................194
8.5.2.1: Bypass Register ...................................................................................................................194
8.5.2.2: Device Identification (ID) Register........................................................................................ 194
8.5.2.3: Implementation Register....................................................................................................... 195
8.5.2.4: EJTAG Control Register....................................................................................................... 196
8.5.3: Processor Access Address Register..............................................................................................202
8.5.3.1: Processor Access Data Register..........................................................................................202

6 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04
8.5.4: Fastdata Register (TAP Instruction FASTDATA)........................................................................... 203
8.6: TAP Processor Accesses........................................................................................................................204
8.6.1: Fetch/Load and Store from/to EJTAG Probe Through dmseg....................................................... 205
8.7: SecureDebug...........................................................................................................................................206
8.7.1: Disabling EJTAG Debugging .........................................................................................................206
8.7.1.1: EJ_DisableProbeDebug Signal ............................................................................................206
8.7.1.2: Override for EjtagBrk and DINT Disable............................................................................... 207
8.7.2: EJTAG Features Unmodified by SecureDebug .............................................................................207
8.8: iFlowtrace™ Mechanism.........................................................................................................................207
8.8.1: A Simple Instruction-Only Tracing Scheme ...................................................................................208
8.8.1.1: Trace Inputs.......................................................................................................................... 208
8.8.1.2: Normal Trace Mode Outputs ................................................................................................208
8.8.2: Special Trace Modes .....................................................................................................................209
8.8.2.1: Mode Descriptions................................................................................................................209
8.8.2.2: Special Trace Mode Outputs................................................................................................ 211
8.8.3: ITCB Overview...............................................................................................................................212
8.8.4: ITCB iFlowtrace Interface............................................................................................................... 212
8.8.5: TCB Storage Representation.........................................................................................................213
8.8.6: ITCB Register Interface for Software Configurability .....................................................................214
8.8.6.1: iFlowtrace Control/Status (IFCTL) Register (offset 0x3fc0)..................................................214
8.8.6.2: ITCBTW Register (offset 0x3F80) ........................................................................................ 216
8.8.6.3: ITCBRDP Register (Offset 0x3f88)....................................................................................... 217
8.8.6.4: ITCBWRP Register (Offset 0x3f90)......................................................................................217
8.8.7: ITCB iFlowtrace Off-Chip Interface................................................................................................218
8.8.8: Breakpoint-Based Enabling of Tracing........................................................................................... 218
8.9: PC/Data Address Sampling..................................................................................................................... 219
8.9.1: PC Sampling in Wait State.............................................................................................................220
8.9.2: Data Address Sampling .................................................................................................................220
8.10: Fast Debug Channel..............................................................................................................................220
8.10.1: Common Device Memory Map..................................................................................................... 221
8.10.2: Fast Debug Channel Interrupt......................................................................................................221
8.10.3: M14K™ Core FDC Buffers........................................................................................................... 221
8.10.4: Sleep mode..................................................................................................................................223
8.10.5: FDC TAP Register .......................................................................................................................223
8.10.6: Fast Debug Channel Registers....................................................................................................224
8.10.6.1: FDC Access Control and Status (FDACSR) Register (Offset 0x0).....................................224
8.10.6.2: FDC Configuration (FDCFG) Register (Offset 0x8)............................................................225
8.10.6.3: FDC Status (FDSTAT) Register (Offset 0x10) ...................................................................226
8.10.6.4: FDC Receive (FDRX) Register (Offset 0x18).....................................................................227
8.10.6.5: FDC Transmit n (FDTXn) Registers (Offset 0x20 + 0x8*n)................................................ 227
8.11: cJTAG Interface.....................................................................................................................................228
Chapter 9: Instruction Set Overview.................................................................................................230
9.1: CPU Instruction Formats......................................................................................................................... 230
9.2: Load and Store Instructions.....................................................................................................................231
9.2.1: Scheduling a Load Delay Slot........................................................................................................231
9.2.2: Defining Access Types................................................................................................................... 231
9.3: Computational Instructions......................................................................................................................232
9.3.1: Cycle Timing for Multiply and Divide Instructions........................................................................... 233
9.4: Jump and Branch Instructions.................................................................................................................233
9.4.1: Overview of Jump Instructions....................................................................................................... 233
9.4.2: Overview of Branch Instructions ....................................................................................................233
9.5: Control Instructions..................................................................................................................................233

MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 7
9.6: Coprocessor Instructions......................................................................................................................... 233
9.7: Enhancements to the MIPS Architecture.................................................................................................233
9.7.1: CLO - Count Leading Ones............................................................................................................234
9.7.2: CLZ - Count Leading Zeros............................................................................................................ 234
9.7.3: MADD - Multiply and Add Word.....................................................................................................234
9.7.4: MADDU - Multiply and Add Unsigned Word ..................................................................................234
9.7.5: MSUB - Multiply and Subtract Word ..............................................................................................234
9.7.6: MSUBU - Multiply and Subtract Unsigned Word............................................................................ 235
9.7.7: MUL - Multiply Word....................................................................................................................... 235
9.7.8: SSNOP- Superscalar Inhibit NOP..................................................................................................235
9.8: MCU ASE Instructions............................................................................................................................. 235
9.8.1: ACLR..............................................................................................................................................235
9.8.2: ASET..............................................................................................................................................235
9.8.3: IRET...............................................................................................................................................235
Chapter 10: M14K™ Processor Core Instructions ..........................................................................236
10.1: Understanding the Instruction Descriptions........................................................................................... 236
10.2: M14K™ Core Opcode Map................................................................................................................... 236
10.3: MIPS32®Instruction Set for the M14K™ Core..................................................................................... 239
Chapter 11: microMIPS™ Instruction Set Architecture ..................................................................267
11.1: Overview................................................................................................................................................267
11.1.1: MIPSr3™ Architecture .................................................................................................................267
11.1.2: Default ISA Mode.........................................................................................................................268
11.1.3: Software Detection.......................................................................................................................268
11.1.4: Compliance and Subsetting.........................................................................................................268
11.1.5: Mode Switch.................................................................................................................................268
11.1.6: Branch and Jump Offsets.............................................................................................................269
11.1.7: Coprocessor Unusable Behavior .................................................................................................269
11.2: Instruction Formats................................................................................................................................ 269
11.2.1: Instruction Stream Organization and Endianness........................................................................272
11.3: microMIPS Re-encoded Instructions.....................................................................................................272
11.3.1: 16-Bit Category............................................................................................................................273
11.3.1.1: Frequent MIPS32 Instructions............................................................................................273
11.3.1.2: Frequent MIPS32 Instruction Sequences...........................................................................275
11.3.1.3: Instruction-Specific Register Specifiers and Immediate Field Encodings...........................277
11.3.2: 16-bit Instruction Register Set......................................................................................................278
11.3.3: 32-Bit Category............................................................................................................................280
11.3.3.1: New 32-bit instructions .......................................................................................................280
Appendix A: References ....................................................................................................................283
Appendix B: Revision History ...........................................................................................................285

8 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04

MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 1
List of Figures
Figure 1.1: M14K™ Processor Core Block Diagram ................................................................................................9
Figure 1.2: M14K™ Core Virtual Address Map ......................................................................................................13
Figure 1.3: Address Translation During SRAM Access with FMT Implementation ................................................14
Figure 1.4: Reference Design Block Diagram.........................................................................................................17
Figure 1.5: FDC Overview.......................................................................................................................................20
Figure 1.6: cJTAG Support ..................................................................................................................................... 21
Figure 2.1: M14K™ Core Pipeline Stages with high-performance MDU ...............................................................23
Figure 2.2: M14K™ Core Pipeline Stages with area-efficient MDU .......................................................................23
Figure 2.3: MDU Pipeline Behavior During Multiply Operations ............................................................................28
Figure 2.4: MDU Pipeline Flow During a 32x16 Multiply Operation .......................................................................29
Figure 2.5: MDU Pipeline Flow During a 32x32 Multiply Operation .......................................................................29
Figure 2.6: High-Performance MDU Pipeline Flow During a 8-bit Divide (DIV) Operation ....................................30
Figure 2.7: High-Performance MDU Pipeline Flow During a 16-bit Divide (DIV) Operation ..................................30
Figure 2.8: High-Performance MDU Pipeline Flow During a 24-bit Divide (DIV) Operation ..................................30
Figure 2.9: High-Performance MDU Pipeline Flow During a 32-bit Divide (DIV) Operation ..................................30
Figure 2.10: M14K™ Area-Efficient MDU Pipeline Flow During a Multiply Operation ...........................................31
Figure 2.11: M14K™ Core Area-Efficient MDU Pipeline Flow During a Multiply Accumulate Operation ............... 32
Figure 2.12: M14K™ Core Area-Efficient MDU Pipeline Flow During a Divide (DIV) Operation ...........................32
Figure 2.13: IU Pipeline Branch Delay ...................................................................................................................33
Figure 2.14: IU Pipeline Data Bypass ...................................................................................................................34
Figure 2.15: IU Pipeline M to E bypass ..................................................................................................................34
Figure 2.16: IU Pipeline A to E Data bypass ..........................................................................................................35
Figure 2.17: IU Pipeline Slip after a MFHI ..............................................................................................................35
Figure 2.18: Coprocessor 2 Interface Transactions ...............................................................................................36
Figure 2.19: Instruction Cache Miss Slip ................................................................................................................38
Figure 3.1: Address Translation During SRAM Access .........................................................................................44
Figure 3.2: M14K™ processor core Virtual Memory Map ......................................................................................45
Figure 3.3: User Mode Virtual Address Space .......................................................................................................46
Figure 3.4: Kernel Mode Virtual Address Space ...................................................................................................48
Figure 3.5: Debug Mode Virtual Address Space ....................................................................................................50
Figure 3.6: FMT Memory Map (ERL=0) in the M14K™ Processor Core ...............................................................52
Figure 3.7: FMT Memory Map (ERL=1) in the M14K™ Processor Core ...............................................................53
Figure 4.1: Interrupt Generation for Vectored Interrupt Mode ................................................................................62
Figure 4.2: Interrupt Generation for External Interrupt Controller Interrupt Mode ..................................................65
Figure 4.3: General Exception Handler (HW) ........................................................................................................ 84
Figure 4.4: General Exception Servicing Guidelines (SW) .................................................................................... 85
Figure 4.5: Reset, Soft Reset and NMI Exception Handling and Servicing Guidelines .........................................86
Figure 5.1: UserLocal Register Format ..................................................................................................................90
Figure 5.2: HWREna Register Format.................................................................................................................... 91
Figure 5.3: BadVAddr Register Format ..................................................................................................................92
Figure 5.4: BadInstr Register Format......................................................................................................................93
Figure 5.5: BadInstrP Register Format ................................................................................................................... 93
Figure 5.6: Count Register Format .........................................................................................................................94
Figure 5.7: Compare Register Format ................................................................................................................... 95
Figure 5.8: Status Register Format.........................................................................................................................95
Figure 5.9: IntCtl Register Format...........................................................................................................................99
Figure 5.10: SRSCtl Register Format ................................................................................................................... 103

2 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04
Figure 5.11: SRSMap Register Format.................................................................................................................106
Figure 5-12: View_IPL Register Format................................................................................................................107
Figure 5-13: SRSMap Register Format.................................................................................................................108
Figure 5.14: Cause Register Format.....................................................................................................................108
Figure 5-15: View_RIPL Register Format............................................................................................................. 113
Figure 5-16: NestedExc Register Format..............................................................................................................114
Figure 5.17: EPC Register Format .......................................................................................................................115
Figure 5-18: NestedEPC Register Format............................................................................................................ 116
Figure 5.19: PRId Register Format ...................................................................................................................... 116
Figure 5.20: EBase Register Format.....................................................................................................................118
Figure 5.21: CDMMBase Register Format............................................................................................................118
Figure 5.22: Config Register Format — Select 0 ................................................................................................. 119
Figure 5.23: Config1 Register Format — Select 1 ............................................................................................... 121
Figure 5.24: Config2 Register Format — Select 2 ............................................................................................... 122
Figure 5-25: Config3 Register Format...................................................................................................................123
Figure 5-26: Config4 Register Format...................................................................................................................126
Figure 5-27: Config5 Register Format...................................................................................................................127
Figure 5.28: Config7 Register Format ..................................................................................................................127
Figure 5.29: Debug Register Format ....................................................................................................................128
Figure 5.30: TraceControl Register Format ......................................................................................................... 132
Figure 5.31: TraceControl2 Register Format ....................................................................................................... 134
Figure 5.32: User Trace Data1/User Trace Data2 Register Format ....................................................................136
Figure 5.33: Trace BPC Register Format .............................................................................................................136
Figure 5.34: Debug2 Register Format ..................................................................................................................137
Figure 5.35: DEPC Register Format .................................................................................................................... 139
Figure 5.36: Performance Counter Control Register ............................................................................................140
Figure 5.37: Performance Counter Count Register ..............................................................................................143
Figure 5.38: ErrCtl Register Format ....................................................................................................................144
Figure 5.39: CacheErr Register (Primary Caches) ..............................................................................................144
Figure 5.40: ErrorEPC Register Format ...............................................................................................................146
Figure 5.41: DeSave Register Format ................................................................................................................. 146
Figure 5-42: KScratchn Register Format .............................................................................................................. 147
Figure 8.1: DCR Register Format ......................................................................................................................... 156
Figure 8.2: IBS Register Format .......................................................................................................................... 167
Figure 8.3: IBAn Register Format ........................................................................................................................ 167
Figure 8.4: IBMn Register Format ........................................................................................................................168
Figure 8.5: IBASIDn Register Format .................................................................................................................. 168
Figure 8.6: IBCn Register Format ........................................................................................................................ 169
Figure 8.7: IBCCn Register Format ......................................................................................................................170
Figure 8.8: IBPCn Register Format ......................................................................................................................171
Figure 8.9: DBS Register Format .........................................................................................................................172
Figure 8.10: DBAn Register Format .....................................................................................................................172
Figure 8.11: DBMn Register Format .................................................................................................................... 173
Figure 8.12: DBASIDn Register Format ...............................................................................................................173
Figure 8.13: DBCn Register Format .....................................................................................................................173
Figure 8.14: DBVn Register Format .....................................................................................................................175
Figure 8.15: DBCCn Register Format ..................................................................................................................176
Figure 8.16: DBPCn Register Format................................................................................................................... 177
Figure 8.17: DVM Register Format ...................................................................................................................... 177
Figure 8.18: CBTC Register Format ..................................................................................................................... 178
Figure 8.19: PrCndA Register Format ..................................................................................................................179
Figure 8.20: STCtl Register Format ..................................................................................................................... 181
Figure 8.21: STCnt Register Format ....................................................................................................................182

MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 3
Figure 8.22: TAP Controller State Diagram ......................................................................................................... 188
Figure 8.23: Concatenation of the EJTAG Address, Data and Control Registers ................................................192
Figure 8.24: TDI to TDO Path When in Shift-DR State and FASTDATA Instruction is Selected .........................193
Figure 8.25: Device Identification Register Format ..............................................................................................194
Figure 8.26: Implementation Register Format ......................................................................................................195
Figure 8.27: EJTAG Control Register Format ......................................................................................................196
Figure 8.28: Endian Formats for the PAD Register ..............................................................................................203
Figure 8.29: Fastdata Register Format................................................................................................................. 203
Figure 8.30: Trace Logic Overview....................................................................................................................... 212
Figure 8.31: Control/Status Register..................................................................................................................... 214
Figure 8.32: ITCBTW Register Format ................................................................................................................. 216
Figure 8.33: ITCBRDP Register Format ............................................................................................................... 217
Figure 8.34: ITCBWRP Register Format...............................................................................................................217
Figure 8.35: PCSAMPLE TAP Register Format (MIPS32) ...................................................................................219
Figure 8.36: Fast Debug Channel Buffer Organization.........................................................................................222
Figure 8.37: FDC TAP Register Format................................................................................................................223
Figure 8.38: FDC Access Control and Status Register.........................................................................................224
Figure 8.39: FDC Configuration Register..............................................................................................................225
Figure 8.40: FDC Status Register.........................................................................................................................226
Figure 8.41: FDC Receive Register...................................................................................................................... 227
Figure 8.42: FDC Transmit Register..................................................................................................................... 227
Figure 8.43: cJTAG Interface................................................................................................................................228
Figure 9.1: Instruction Formats ............................................................................................................................ 231
Figure 11.1: 16-Bit Instruction Formats.................................................................................................................270
Figure 11.2: 32-Bit Instruction Formats.................................................................................................................271
Figure 11.3: Immediate Fields within 32-Bit Instructions.......................................................................................271

4 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04

MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 1
List of Tables
Table 2.1: MDU Instruction Latencies (High-Performance MDU)...........................................................................26
Table 2.2: MDU Instruction Repeat Rates (High-Performance MDU).....................................................................27
Table 2.3: M14K™ Core Instruction Latencies (Area-Efficient MDU).....................................................................31
Table 2.4: Pipeline Interlocks..................................................................................................................................37
Table 2.5: Instruction Interlocks.............................................................................................................................. 38
Table 2.6: Execution Hazards.................................................................................................................................40
Table 2.7: Instruction Hazards................................................................................................................................ 40
Table 2.8: Hazard Instruction Listing ......................................................................................................................40
Table 3.1: User Mode Segments ............................................................................................................................ 46
Table 3.2: Kernel Mode Segments .........................................................................................................................48
Table 3.3: Physical Address and Cache Attributes for dseg, dmseg, and drseg Address Spaces.........................50
Table 3.4: CPU Access to drseg Address Range................................................................................................... 50
Table 3.5: CPU Access to dmseg Address Range ................................................................................................. 51
Table 3.6: Cacheability of Segments with Block Address Translation....................................................................51
Table 4.1: Priority of Exceptions ............................................................................................................................. 56
Table 4.2: Interrupt Modes......................................................................................................................................58
Table 4.3: Relative Interrupt Priority for Vectored Interrupt Mode...........................................................................61
Table 4.4: Exception Vector Offsets for Vectored Interrupts...................................................................................66
Table 4.5: Exception Vector Base Addresses......................................................................................................... 70
Table 4.6: Exception Vector Offsets .......................................................................................................................70
Table 4.7: Exception Vectors.................................................................................................................................. 70
Table 4.8: Value Stored in EPC, ErrorEPC, or DEPC on an Exception..................................................................71
Table 4.9: Debug Exception Vector Addresses ...................................................................................................... 74
Table 4.10: Register States an Interrupt Exception ................................................................................................ 77
Table 4.11: CP0 Register States on an Address Exception Error...........................................................................78
Table 4.12: CP0 Register States on a SRAM Parity Error Exception.....................................................................78
Table 4.13: Register States on a Coprocessor Unusable Exception......................................................................81
Table 5.1: CP0 Registers........................................................................................................................................88
Table 5.2: CP0 Register R/W Field Types.............................................................................................................. 90
Table 5.4: HWREna Register Field Descriptions....................................................................................................91
Table 5.3: UserLocal Register Field Descriptions...................................................................................................91
Table 5.5: BadVAddr Register Field Description.....................................................................................................92
Table 5.6: BadInstr Register Field Descriptions......................................................................................................93
Table 5.8: Count Register Field Description ........................................................................................................... 94
Table 5.7: BadInstrP Register Field Descriptions ................................................................................................... 94
Table 5.9: Compare Register Field Description......................................................................................................95
Table 5.10: Status Register Field Descriptions.......................................................................................................96
Table 5.11: IntCtl Register Field Descriptions.......................................................................................................100
Table 5.12: SRSCtl Register Field Descriptions ................................................................................................... 103
Table 5.13: Sources for new SRSCtlCSS on an Exception or Interrupt.................................................................106
Table 5.14: SRSMap Register Field Descriptions.................................................................................................106
Table 5.15: View_IPL Register Field Descriptions................................................................................................107
Table 5.16: SRSMap Register Field Descriptions.................................................................................................108
Table 5.17: Cause Register Field Descriptions.....................................................................................................108
Table 5.18: Cause Register ExcCode Field..........................................................................................................112
Table 5.19: View_RIPL Register Field Descriptions ............................................................................................. 113
Table 5.20: NestedExc Register Field Descriptions..............................................................................................114

2 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04
Table 5.21: EPC Register Field Description..........................................................................................................115
Table 5.22: NestedEPC Register Field Descriptions ............................................................................................ 116
Table 5.23: PRId Register Field Descriptions....................................................................................................... 116
Table 5.24: EBase Register Field Descriptions.....................................................................................................118
Table 5.25: CDMMBase Register Field Descriptions............................................................................................119
Table 5.26: Config Register Field Descriptions.....................................................................................................120
Table 5.27: Cache Coherency Attributes.............................................................................................................. 121
Table 5.28: Config1 Register Field Descriptions — Select 1................................................................................121
Table 5.29: Config2 Register Field Descriptions — Select 1................................................................................122
Table 5.30: Config3 Register Field Descriptions...................................................................................................123
Table 5.31: Config4 Register Field Descriptions...................................................................................................126
Table 5.32: Config5 Register Field Descriptions...................................................................................................127
Table 5.33: Config7 Register Field Descriptions...................................................................................................127
Table 5.34: Debug Register Field Descriptions.....................................................................................................128
Table 5.35: TraceControl Register Field Descriptions .......................................................................................... 132
Table 5.36: TraceControl2 Register Field Descriptions ........................................................................................ 134
Table 5.37: UserTraceData1/UserTraceData2 Register Field Descriptions .........................................................136
Table 5.38: TraceBPC Register Field Descriptions...............................................................................................136
Table 5.39: Debug2 Register Field Descriptions...................................................................................................138
Table 5.40: DEPC Register Formats.....................................................................................................................139
Table 5.41: Performance Counter Register Selects..............................................................................................139
Table 5.42: Performance Counter Control Register Field Descriptions................................................................140
Table 5.43: Performance Counter Events Sorted by Event Number .................................................................... 140
Table 5.44: Performance Counter Event Descriptions Sorted by Event Type......................................................142
Table 5.46: Errctl Register Field Descriptions.......................................................................................................144
Table 5.45: Performance Counter Count Register Field Descriptions..................................................................144
Table 5.47: CacheErr Register Field Descriptions (Primary Caches)...................................................................145
Table 5.48: ErrorEPC Register Field Description..................................................................................................146
Table 5.49: DeSave Register Field Description.................................................................................................... 146
Table 5.50: KScratchn Register Field Descriptions...............................................................................................147
Table 8.1: DCR Register Field Descriptions ......................................................................................................... 156
Table 8.2: Addresses for Instruction Breakpoint Registers...................................................................................166
Table 8.3: IBS Register Field Descriptions ........................................................................................................... 167
Table 8.4: IBAn Register Field Descriptions ......................................................................................................... 167
Table 8.5: IBMn Register Field Descriptions.........................................................................................................168
Table 8.6: IBASIDn Register Field Descriptions ................................................................................................... 168
Table 8.7: IBCn Register Field Descriptions......................................................................................................... 169
Table 8.8: IBCCn Register Field Descriptions.......................................................................................................170
Table 8.9: IBPCn Register Field Descriptions.......................................................................................................171
Table 8.10: Addresses for Data Breakpoint Registers..........................................................................................171
Table 8.11: DBS Register Field Descriptions........................................................................................................172
Table 8.12: DBAn Register Field Descriptions......................................................................................................172
Table 8.13: DBMn Register Field Descriptions.....................................................................................................173
Table 8.14: DBASIDn Register Field Descriptions................................................................................................173
Table 8.15: DBCn Register Field Descriptions......................................................................................................174
Table 8.16: DBVn Register Field Descriptions......................................................................................................175
Table 8.17: DBCCn Register Field Descriptions...................................................................................................176
Table 8.18: DBPCn Register Field Descriptions...................................................................................................177
Table 8.19: DVM Register Field Descriptions.......................................................................................................177
Table 8.20: Addresses for Complex Breakpoint Registers ................................................................................... 178
Table 8.21: CBTC Register Field Descriptions ..................................................................................................... 178
Table 8.23: Priming Conditions and Register Values for 6I/2D Configuration ......................................................180
Table 8.24: Priming Conditions and Register Values for 8I/4D Configuration ......................................................180

MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 3
Table 8.22: PrCndA Register Field Descriptions...................................................................................................180
Table 8.25: STCtl Register Field Descriptions......................................................................................................181
Table 8.26: STCtl Register Field Descriptions......................................................................................................182
Table 8.27: EJTAG Interface Pins ........................................................................................................................186
Table 8.28: Implemented EJTAG Instructions ...................................................................................................... 191
Table 8.30: Implementation Register Descriptions ............................................................................................... 195
Table 8.29: Device Identification Register.............................................................................................................195
Table 8.31: EJTAG Control Register Descriptions................................................................................................197
Table 8.32: Fastdata Register Field Description...................................................................................................203
Table 8.33: Operation of the FASTDATA access ................................................................................................. 204
Table 8.34: EJ_DisableProbeDebug Signal Overview..........................................................................................207
Table 8.35: Data Bus Encoding ............................................................................................................................ 213
Table 8.36: Tag Bit Encoding................................................................................................................................ 213
Table 8.37: Control/Status Register Field Descriptions ........................................................................................ 215
Table 8.38: ITCBTW Register Field Descriptions ................................................................................................. 216
Table 8.39: ITCBRDP Register Field Descriptions ............................................................................................... 217
Table 8.40: ITCBWRP Register Field Descriptions...............................................................................................217
Table 8.41: drseg Registers that Enable/Disable Trace from Breakpoint-Based Triggers.................................... 218
Table 8.42: FDC TAP Register Field Descriptions................................................................................................223
Table 8.43: FDC Register Mapping.......................................................................................................................224
Table 8.44: FDC Access Control and Status Register Field Descriptions ............................................................224
Table 8.45: FDC Configuration Register Field Descriptions .................................................................................225
Table 8.46: FDC Status Register Field Descriptions.............................................................................................226
Table 8.47: FDC Receive Register Field Descriptions..........................................................................................227
Table 8.49: FDTXn Address Decode.................................................................................................................... 228
Table 8.48: FDC Transmit Register Field Descriptions.........................................................................................228
Table 9.1: Byte Access Within a Word..................................................................................................................232
Table 10.1: Encoding of the Opcode Field............................................................................................................ 237
Table 10.2: Special Opcode Encoding of Function Field...................................................................................... 237
Table 10.3: Special2 Opcode Encoding of Function Field.................................................................................... 237
Table 10.4: Special3 Opcode Encoding of Function Field.................................................................................... 238
Table 10.5: RegImm Encoding of rt Field..............................................................................................................238
Table 10.6: COP2 Encoding of rs Field ................................................................................................................238
Table 10.7: COP2 Encoding of rt Field When rs=BC2.......................................................................................... 238
Table 10.8: COP0 Encoding of rs Field ................................................................................................................239
Table 10.9: COP0 Encoding of Function Field When rs=CO................................................................................ 239
Table 10.10: Instruction Set.................................................................................................................................. 239
Table 11.1: 16-Bit Re-encoding of Frequent MIPS32 Instructions........................................................................274
Table 11.2: 16-Bit Re-encoding of Frequent MIPS32 Instruction Sequences.......................................................275
Table 11.3: Instruction-Specific Register Specifiers and Immediate Field Values...............................................277
Table 11.4: 16-Bit Instruction General-Purpose Registers - $2-$7, $16, $17.......................................................278
Table 11.5: SB16, SH16, SW16 Source Registers - $0, $2-$7, $17.....................................................................279
Table 11.6: 16-Bit Instruction Implicit General-Purpose Registers .......................................................................279
Table 11.7: 16-Bit Instruction Special-Purpose Registers.....................................................................................280
Table 11.8: 32-bit Instructions introduced within microMIPS................................................................................280

Chapter 1
MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04 4
Introduction to the MIPS32® M14K™ Processor Core
The MIPS32® M14K™ core from MIPS Technologies is a high-performance, low-power, 32-bit MIPS RISC proces-
sor core intended for custom system-on-silicon applications. The core is designed for semiconductor manufacturing
companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripher-
als with a high-performance RISC processor. The M14K core is fully synthesizable to allow maximum flexibility; it
is highly portable across processes and can easily be integrated into full system-on-silicon designs. This allows devel-
opers to focus their attention on end-user specific characteristics of their product.
The M14K core is especially well-suited for microcontrollers and applications that have real-time requirements with
a high level of performance efficiency and security requirements.
The M14K core implements the MIPS Architecture in a 5-stage pipeline. It includes support for the microMIPS™
ISA, an Instruction Set Architecture with optimized MIPS32 16-bit and 32-bit instructions that provides a significant
reduction in code size with a performance equivalent to MIPS32. The M14K core is a successor to the M4K®,
designed from the same microarchitecture, including the Microcontroller Application-Specific Extension (MCU™
ASE), enhanced interrupt handling, lower interrupt latency, a memory protection unit (MPU), a reference design of
an optimized interface for flash memory and built-in native AMBA®-3 AHB-Lite Bus Interface Unit (BIU), with
additional power saving, debug, and profiling features.
The M14K core is cacheless; in lieu of caches, it includes a simple interface to SRAM-style devices. This interface
may be configured for independent instruction and data devices or combined into a unified interface. The SRAM
interface allows deterministic latency to memory, while still maintaining high performance.
The core includes one of two different Multiply/Divide Unit (MDU) implementations, selectable at build-time, allow-
ing the user to trade-off performance and area for integer multiply and divide operations. The high-performance
MDU option implements single-cycle multiply and multiply-accumulate (MAC) instructions that enable DSP algo-
rithms to be performed efficiently. It allows 32-bit x 16-bit MAC instructions to be issued every cycle, while a 32-bit
x 32-bit MAC instruction can be issued every other cycle. The area-efficient MDU option handles multiplies with a
one-bit-per-clock iterative algorithm.
The MMU consists of a simple Fixed Mapping Translation (FMT) mechanism, for applications that do not require
the full capabilities of a Translation Lookaside Buffer- (TLB-) based MMU available on other MIPS cores.
The basic Enhanced JTAG (EJTAG) features provide CPU run control with stop, single-stepping and re-start, and
with software breakpoints using the SDBBP instruction. Additional EJTAG features such as instruction and data vir-
tual address hardware breakpoints, complex hardware breakpoints, connection to an external EJTAG probe through
the Test Access Port (TAP), and PC/Data tracing, may be included as an option.
1.1 Features
• 5-stage pipeline
• 32-bit Address and Data Paths