MITS altair 8800b Operator's manual

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ALTAIR 8800b
TABLE OF CONTENTS
Section
Page
LIST OF TABLES.
. . . i1
LIST OF ILLUSTRATIONS
I. INTRODUCTION
. . . . . . .. . . . . . . . . . . .. . . • • •
11
1-1. Scope •••••
1-2. Arrangement •••
l".'3. Description •••••
.. .
II. OPERATORS GUIDE
. . . . . . . . . . . . . . . . . . . 1-1
• •••••••••••••• 1-1
. . . . . . . . . . . . . . . . . 1-1
2-1. General ••••.••••••••••••••••••••••• 2-1
2-2. Front Panel Switches and Indicators •••••••••••••• 2-1
2-12. Loading A Sample Program . . . . . . . . . . . . . . . . . 2-11
III. THEORY OF OPERATION
3-1. General. . . . . . . . . . . . . . . . . . . . . . . . 3-3
3-2. Logic Circuits •••••••••••••••••••••••• 3-3
3-3. Altair 8800b Operation. • • • • • •••••••••••• 3-3
3-5. 8800b Block Diagram Description •••••••••••••••• 3-10.
3-11.
8800b Data Processing Operation •••••••••••••••• 3-15
3-12. Instruction Fetch Cycle. • • • • • • • • • • • • • • • • • • • 3-15
3-15. Memory Read Cycle. • • • • • • • • • • • • • • • • • • • • • • 3-20
3-18. External Device to CPU Data Transfer ••••••••••••• 3-25
3-21. CPU to Memory Data Transfer. • • • • • • • • • • • • • • • • • 3-30
3-23. Memory Write Cycle Detailed Operation ••••••••••••• 3-32
3-24. Memory to CPU Data Transfer •••••••••••••••••• 3-34
3-25. CPU to External Device Data Transfer. • ••••••••• 3-35
3-28. Front Panel Operation •••••••.••••••••.•••• 3-39
3-39. 8800b Options. • • • • • • • • . • • • • • •••••• 3-59
3-42. 8800b Power Supplies. • • • • • • • • • • • • • • • • • • 3-60
IV. TROUBLESHOOTING AIDS
V. ASSEMBLY
4-1
5-1. General. . • • • • • • • • . • • • • •••••••••• ~ 5-3
5-2. Assembly Hints. • • . . • • • • • • • • • • • • • • • 5-3
5-3.
Component Installation Instructions. • • • • •• 5-5
5-9. Interface Card Assembly. • • • • • • • • • ••••• 5-13
5-19. Display/Control Board Assembly . • • • • • • • • •••• 5-19
5-32. CPU Board Assembly. • • • • • • • • • • • • • •••••• 5-37
5-44. Power Supply Board Assemb].Y_._ • • • . • • • • • • • • • 5-47
5-53. Back Panel Assembly •••••••.•••••••••••••• 5-54
5-69. 18-Slot Motherboard Assembly ;·-~--;--;·-.··- ••.••••••.•• 5-69
APPENDIX
© Oui)~ 1976
2450 Alamo SE
Albuquerque, NM 87106
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ilumbar
2-1
2·-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
· 3-1
3-2
Number
1-1
l-2
1-3
1--4
1-5
?·:· .·~r' (='' : ;:.~·.· :nr:~ ,
.~:-~71 ,::.-7=;"1 '.:·i .J:l , ... 3
Stop G~~:~1 ~: i en-~ . ~ :,
!..!ST OF T,:.JL::S
- Examine i·lemory Gpera t 'Jon.
f • • ' • ' •
,"') -,
• .:..-1
. • . . . • . 2-7
Altering ;,12n:ory Cont2i1ts •••••••••.•
2-8
Examine Next Memory Location. . . . ••.
• . . . . • . • . 2-8
Al taring iiext r!errrory Ccnt2nts . . . • . .
•. 2-9
Loading and Displaying Accumulator Data .••
•..•...•. 2-10
......... 2-12
. . . . . . . . . . 2-13
.•.•.••.•. 2-14
Machine Language Bit Patterns. • • •
Addition
Program ••••••.••••••••
Addition Program Loading ••••••••••
Symbol Definitions •••••••••
PROM Programs ••••••••
. . . . . . . . . . . . . . . . . 3-5
•••••••••••••• 3-47
LIST OF-ILLUSTRATIONS
Title
Page
Altair 8800b Computer • • • • . • • . . • • • • • 1-0
Power Supply 80<2,·d. • • • • • • • • • • • • • • • • • • • • 1-2
Interface Board. . • • . . . . • • . • • • •••.••.• 1-2
CPU Board • . • • • • • • • . • • • . • • • • • • • • • • • • • 1-4
Display/Control Board ••••••••••••••••••••• 1-4
2-1 Al ta1 r 8800b Front Panel. • • • • • • • • • • • • • • • • • • • 2-1
3-1
3-2
3-3
3-4
3-5
3-6
.,. ..
:,-,
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-15
3-15
3-16
3-16
3-16
11
8800b 81 ock Diagram • • • • • • • • • • • • • • • • • • • • • • 3-11
Instruction Fetch Cycle Bloc!< Diagram ••••••••••••• 3-17
Inst.ruction Fetch Cycle T1m1ng. • • • • • . 3-18
fl.emory Read Cyc 1e Block 01 a gram • ~ • • • • • • • • • • • • • • 3-21
Memory Read Cycle Timing. • • • • • • • • • • • • • • • • • •. 3-24
Inp:.at Read Cycle Block 01 a gram. • • • • • • • • • • • • . • • • 3-27
Input Read Cycle T1mfng •••••••••••••••••••• 3-28
Memory Write Cycle Block Diagram. • • • • • • • • • • • •• 3-31
Memory Write Cycle Timing • • • • • • • • • • • • • • • • • 3-33
Output Write Cycle Block D1agram •••••••••••••••. 3-36
Output Write CJ.·c le Timing • • • • • • • • • • • • • • • • • • • 3-38
Front Panel Block Diagram ••••••••••••••••••• 3-40
PROM Block Di a gram. • • • • • . • • • • • • • • • • • • • • 3-46
CPU Schematic. • • • • • • • • • • • • • • • • • • • • • • 3-63
Interface Schematic • • • • • • •. • • • • • • • • • • • • • • • 3-65
Interface Schemat1c:-{sheet·2of 3) ••••••••••••••• 3-67
Interface Schematic (sheet 3 of 3). • • • • • • • • • • • • 3-69
Display/Control Schematic !sheet 1 of 3l. ... 3-71
Display/Control Schematic sheet 2· of 3 •••••••••••• 3-73
Display/Control Schematic sheet 3 of 3 •••••••••••• 3-75
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LIST OF ILLUSTRATIONS - Continued
Title
Page
3-17 Power Supply Board Schematic. • • • • • • • • • • • • • • 3-77
3-18 CPU Voltage Regulator Schematic. • • • • • • • • •• 3-79
3-19 Interface Voltage Regulator Schematic •••••••••••• 3-81
3-20 Display/Control Voltage Regulator Schematic ••••••••• 3-83
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20A
5-20B
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5.A37
5-38
5-39
5-40
5-41
5-42
5-43
Typical Silkscreen •••••••••••••.•••••••• 5-4
Interface IC Instal1 ati on • • • • • • • • • • • • • • • • • • 5-2
Interface Resistor Installation ••••••••••••••• 5-14
Interface Suppressor Capacitor and Capacitor Installation •• 5-15
Interface Jumper Connections ••••••••••••••••• 5-16
Interface Ferrite Bead Installation ••••••••••••• 5-16
Interface Voltage Regulator Installation ••••••••••• 5-17
Interface Male Connector Installation •••••••••••• 5-18
Interface Ribbon Cable Plug Installation ••••••••••• 5-19
Display/Control IC Socket and IC Installation •••••••• 5-21
Display/Control IC Installation ••••••••••••••• 5-22
Display/Control Resisto·r Installation •••••••••••• 5-23
Display/Control Resistor Pack Installation. • • • • • •• 5-24
Display/Control Substitute Resistor Assembly ••••••••• 5-25
Display/Control Jumper Connections •••••••••••••• 5-26
Display/Control Suppressor Capacitor Installation •••••• 5-27
Display/Control Capacitor Installation •••••••••••• 5-28
Display/Control Diode and Ferrite Bead Installation •••.• 5-29
Display/Control Voltage Regulator Installation •••••••• 5-30
Display/Control Switch Installation .••••••••••••• 5-31
Display/Control Switch Installation ••••••••••••• 5-32
Display/Control Switch Nut Placement ••••••••••••• 5-33
Covering LED Holes on Sub Panel ••••••••••••••• 5-33
Display/Control LED Orientation and Installation. • • •• 5-34
Securing Sub Panel Over Display/Control Board •••••••• 5-34
Display/Control LED Adjustment •••••••••••••••• 5-35
CPU IC Installation ••••••••••••••••••••• 5-37
CPU Resistor Installation • • • • • • • • • ••••••• 5-38
CPU Suppressor Capacitor Installation • • • • • • • . • • 5-39
CPU Capacitor Installation •••••••••••••••••• 5-40
CPU Diode Installation. • • • • • • • • ••••••••. 5-41
CPU Ferrite BeaC: Installation • • • • • ••••••• 5-42
CPU Voltage Regula tor Installation. • • • • • • • • . . • • • 5-43
CPU Transistor and Male Connector Installation •••••••• 5-44
CPU Crystal Installation ••••••••••••••••••• 5-45
CPU IC Socket and IC Installation •••••••••••••• 5-46
Power Supply Capacitor and Resistor Installation ••••••• 5-47
Power Supply Diode Installation ••••••••••••••• 5-48
Power Supply Transistor Installation. • • • • • • • •• 5-49
Power Supply Bridge Rec ti fi er . • • • . • • • • • • • . • • • 5-50
Power Supply Terminal Block Screw Removal •••••••••• 5-51
Power Supply Terminal Block Screw Insertion ••••••••• 5-51
Power Supply Terminal Block Shorting Link Insertion ••••• 5-51
Power Supply Board Mounting to Cross Member. • • • • • • 5-52
iii

Number
5-!+4
5-45
5-46
5-47
5-48
5-49A
5-49B
5-50
5-51
5-52
5-53
5-54
5-55
5-56
5-57
5-58
5-59
5-60
5-61
5-62
" 5-63
5-64
5-65
iv
LiST OF ILLUST:i\TICNS - Cvntittuad
Title
?s·.:=; s~~; 1:.1 C;:.;.;3.c~ ~er 3~~i ,:i ;1::-p I!! t~ i: ,~ t~ ·.;;;
' - ~ ~ ' ·,
,::: ~~a J~?c::c:;.
?:':i-=t Sw~;J 1:; C2;::3:~ t:;: :;i: c~ 2?:'J I!iS tJ 11.1 ~~ Ctl
?age
_ ( :=or T·.110 G·apaci tors) . . . 3-53
Completed Back Panel Assembly ..•......•...... 5-54
Terminal End Sizes . . . . . . . . . . . . . . . . . . . . 5-55
Terminal End Attachment. . • . • . . • . . • • . . . . . 5-56
Connector-Pin and Connector Socket Wire Ins1:rtion ••••.. 5-57
Pin and Socket Housing Assembly. . . . . . • • • • • . • 5-57
Wiring Diagram ••••••••••••••••••••••• 5-58
Bridge Rectifier Installation. • . ••• 5-60
Fan Mounting.·. • • • • • . • • •. 5-61
Fuse Holder Installation. • • • • • • • • • • • • • • • 5-62
AC Power Cord Installation • • • • • • • • • • • • • •• 5-62
"L" Bracket Mounting. • • • • • ••••.••••• 5-63
Tenninal End Attachment. . • • • • • • . •• 5-63
Terminal Block Mounting. • • • • • 5-63
Pin Housing Insertion. • . . . • . • •.• 5-65
Transfonner Mounting • • . • • . 5-66
Back Panel Mounting ••••••••••.••••...•.• 5-67
Motherboard Wire Connections • . . . . . . . . 5-68
Card Guide Mounting. . . • . . . • . • . ...• 5-70
Chassis Ground Connection. . • • • .. 5-71
On/Off Switch Wiring ••••••••••••••••••.• 5-73
Female Connecto·r Wiring for P3 • • • • . . • • • • • 5-75
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1-1. SCOPE
This ALTAIR~800b Documentation
provides a general description of
the various printed circuit cards
contained in the
ALTAIR 8800b and
detailed theory of their operation.
Included in the documentation
is
an operator's guide which famili-
arizes the operator with the var-
ious switches
and indicators on
th.e ALTAIR 8800b front panel. De-
tailed assembly instructions are
also provided.
1-2.
ARRANGEMENT
This manual contains five sections
as fol lows:
1. Section I contains a general
description of the
ALTAIR 8800b
computer and associated printed
circuit cards.
2. Section II contains information
on the controls and indicators
which are located on the ALTAIR
8800b front panel.
3. Section III contains a detailed
theory explanation of the
ALTAIR
8800b circuit operation.
4. Sect-ion IV contains troub1e-
shooti
ng infonnation for the
ALTAIR 8800b.
5. Section Vcontains the detailed
assembly instructions for the
ALTAIR 8800b.
SECTION I
INTRODUCTION
1~3. DESCRIPTION
The ALTAIR 8800b computer (Figure
1-1)
is a general purpose, byte-
oriented
machine (8-bit word).
It uses a common 100-pin bus struc-
ture that allows for expansion of
either standard or custom plug-in
modules. It supports up to 64K of
directly addressable memory and
can address 256 separate input and
output devices. The ALTAIR 8800b
_ computer has 78 basic machine lan-
guage instructions and consists of
a
power supply board, an interface
board, a central processing unit
(CPU) board, and a display/control
board.
1-4. POWER SUPPLY BOARD (Figure 1-2)
The Power Supply Board provides two
of the three output voltages to the
ALTAIR 8800b computer bus, a posi-
tive and negative 18 volts. It
includes a bridge rectifier circuit
and associated filter capacitors, a
10-pin tenninal block connector,
and the regulating transistors for
the positive
and negative 18 volt
supplies.
1-5. JNTERFACE BOARD (Figure 1-3)
The Interface Board buffers all
signals between the display/control
board
and the ALTAIR 8800b bus. It
also contains eight parallel data
lines
which transfer data to the CPU
from the Display/Control board.
Page 1-1

0
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., ·····".--~._.,.~,......,·i_~'.fl~.,l;'J~~-~.(W""""•'-'~~--,.,·~·,..._,..,~l·,"':'_..,';·-e,,<''"'' .~·~.;;.-~,,;~"1,.-.·/•~.._ ~', ,_ .• _,.,,,..,...,. -~~":"':' · -·-~~+. · •"'. b,. r -:..~· ,_,.,,...._..,.,,,,..,, •• ..<',,,..,_" .,..,...._ ""j~·• ·•oc•,...-u...,.-...,_...,.-. .., .. -: • ·, .. ,.:---!'!it'
· - ·- .. n~ I ~-,11"-,l.~.:,-~;,!t-~•ne""~:"'.,.~·;;_~.~c>,,!-'i"~~i':-7~.'r!<-~-~-:!,v,~·".~·""'····~-¥~".,.~...;"i.--.,_,. .. -~~"P~·~-.!'l't~::'·.,._,: .. yw,_,,.. _ _.,....~~•
'~~~~ri-~~~:W1~{iiff't~t1?fe'?CD1ctilf
Figure 1-2.
Power Supply Board
0
Figure 1-3. Interface Board
1-2

0 1-6. fPU BOARD (Figure 1-4)
C
0
The CPU board controls and processes
all instructions and data within
the
ALTAIR 8800b computer. It con-
tains the Intel Corporation model
8080A microprocessor circuit, the
master timing
circuit, eight input
and eight output data lines to the
ALTAIR bus control circuits.
1-7. DISPLAY/CONTROL BOARD (Figure
Eli
The Display/Control Board conditions
all ALTAIR 8800b front panel switches
and receives information -to be dis-
played
on the front panel. It con-
tains a programmable read only
memory (PROM), ~witch and display
control
circuits, and control cir-
cuits to condition the CPU.
Page 1-3

1-4
~\~~.~~;~:;:~:~:;~:~-=~:;~:- .. ~- ~·~~
,, ...... ..,. •. ~ • .,.~~- ¥·
~---~~;',.:#
"
Figure 1-5.
0
Figure 1-4 .. CPU Board
Display /Control Board
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SECTION II
C
OPERATORS GUICE
0
•PAGE 2·1 / (2•2 Blank)

02-1. GENERAL
The Operators Guide contains information on the ALTAIR 8800b
computer (880Gb) front panel controls and indicators. It includes
general switch operation ~xercises
and a sample program whi~h is
intended to familiarize the operator with the various front panel
operations.
This section does not contain specific information on
the 8800b software; but the Intel 8080 Microcomputer Systems Users
Manual is provided for this purpose. Also, additional programs avail-
able to the user are described in the ALTAIR Software Library. Up-
date information is contained with your unit.
2-2. FRONT PANEL SWITCHES AND INDICATORS
The Front Panel switches permit the. operator to perform various
ALTAIR 8800b operations, and the indicators display address informa-
tion, data information, and primary status control line information.
Refer to Figure
2-1 for the location of the switches and indicators
<::and Table 2-1 for an explanation of each.
0 Figure 2-1.
Altair 8800b Front Panel
2-1

Table 2-1. A~TAI? 380Gb S~itches ar~ Incicators
;::.1
STOP/RUN
SINGLE STEP/
SLOW
EXAMINE/
EX NEXT
2-2
-.
,_ "': ... - ..., ..... ,...,_
! ',i; ,\.,. V ( .J j \
The RUN position allows the CPU to process
data
and disables all functions on the
front panel except reset. The STOP pos-
ition conditions the CPU to a wait state
and enables all functions on the front
panel.
The SINGLE STEP position allows execu-
tion of
one machine cycle or one instruc-
tion cycle (depending upon the option
selected). SLOW position allows execu-
tion of
machine or instruction cycles
at a rate of approximately 2 cycles per
second.
(Normal speed is approximately
500,000
machine cycles per second.)
The CPU will execute the cycles as long
as the SLOW position is maintained.
The EXAMINE position allows the operator
to
examine the memory address selected
on the AO-Al5 MEMORY switches. The
contents at that address are displayed
on the DATA 00-07 indtcators. The EX
NEXT position allows the operator to
examine the next sequential memory
address. Each time EX NEXT is actuated,
the contents
of the next sequential
memory address are displayed.
c,
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Table 2-1. ALTAIR 8800b Switches and Indicators -Continued
Switch
DEPOSIT/
DEP NEXT
RESET/
EXT CLR
PROTECT/
UN PROTECT*
ACCUMULATOR
DISPLAY/LOAD
Function or Indication
The DEP~SIT position stores the contents
of the lower address switches
(AO-A?)
into the memory address that is displayed
on the MEMORY address AO-Al5 indicators.
The DEP NEXT position stores the contents
of the 1 ower address switches (AO-A7) into
the next successive
memory address.
The RESET position resets the program
counter to zero and the interrupt enable
flag in the
CPU. The EXT CLR position
produces
an external clear signal on the
system
bus which generally clears an
input/output.
The PROTECT position conditions the
write protect
circuits on the currently
addressed
memory board, preventing data
in
that block of memory from being
changed.
The front panel or the CPU
cannot affect the memory when protected.
UNPROTECT position allows the contents
of
memory to be changed.
The DISPLAY position allows the contents
of the CPU accumulator register to be
displayed on the DATA OO-D7 indicators.
The LOAD position allows the lower
eight address switch
(AO-A?) information
to
be stored in the CPU accumulator
register.
*Protect switch only appHes fo memory-boards with a protect
circuit.
2-3

2-4
2- 1.
' ... ·, - .. "'
- ; I ,...o , \,.,:J, ...,'-.) !
EIPUT /
OUTPUT
Address Switches
AO-A15
SENSE switches
A8-Al5
MEMORY AO-Al5
PROTECT
INTE
MEMR
INP
Ml
OUT
.~ :~ 1-. -. :.-.. ..:-: ·,I_; ..,. ,.-. .-. .) '
.,. ,._,· -· , ·•'-' ... _.
- -. . ~
.;. ; ·- ' ·- ~· • ' '"' • i
an externa]
davice, se1ected on the !/0 AO-A7 switches
(upper eignt atdr2ss switches), to input
data into the CPU accumulator. The
OUTPUT position allows an external de-
vice, selected
on the I/0 AO-A? switches,
to receive data
from the CPU accumulator
register.
These switches are used to select an
address in memory or to enter data. The
up position denotes a one bit and the
down position denotes a zero bit.
The upper eight address switches (A8-
A15) also function as SENSE switches.
The data present on these switches is
stored in the accumulator if an input
from channel 3778 (front panel) is exe-
cuted.
Display the
memory address being examined
or loaded with data.
Memory is protected.
Interrupts are enabled.
The CPU is reading data from memory.
An external device is inputting data
to the
CPU.
The CPU is in machine cycle one of an
instruction cycle.
The CPU is outputting data to an
external device.
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Table 2-1. ALTAIR 8800b Switches and Indicators - Continued
Indicator
Hl.:TA
STACK
WO
INT
DATA DO-D7
WAIT
HLDA
Function or Indication
..
The CPU is in a halt condition.
The address bus contains the address
of the stack pointer.
The CPU is writing out data to an
external device or memory.
The CPU has acknowledged an interrupt
request.
Data from memory, an external device,
or the
CPV
The CPU is in a wait condition.
The CPU has acknowledged a hold
signal.
2-5

2-6
. '
~ ._,... ::r.
'-" I -
-; .-, -- "J. ,""'. , ..... ~/1
•I,"" ..,.1 I'--·-'
t,i2 :p2raccr i.·1~ ch :n2 .~.L;,~:~ 38CCJ f~ont panel s·,·,~t::las and inaica-
tors. Pe~form the operations in a sequential manner as shown in the
following
tables.
2-4. POWER ON SEQUENCE (Table 2-2)
The power on sequence resets the CPU program counter to the first
memory address and places the CPU in a wait condition at the beginning
of an instruction cycle.
Table 2-2.
Power On Sequence
Step Function Indication
1 Position the
POWER ON/ MEMR, Ml, and WAIT
indica-
'
OFF switch to ON.
tors are on. Some
DATA
00-07 indicators may also
be on. All
other indicators
are
off.
2-5. RUN OPERATION (Table 2-3)
The run operation releases the CPU from a wait condition, and
allows it to execute a program. When the run operation is enabled,
all other front panel switches are inactive except the RESET switch.
Table 2-3.
Run Operation
Step Function Indication
1 Momentarily position the
WAIT i ndi ca tor is off
STOP/RUN switch to RUN.
(or may be dimly lit).
The machine can now exe-
cute a program.
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0

0 2-6. STOP OPERATION (Table 2-4)
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0
The stop operation places the CPU in a wait condition and allows
the operator to
use the switches on the 8800b front panel.
Table 2-4. Stop Operation
Step Function Indication
1 Position the STOP/RUN
WAIT,
MEMR, and Ml
indicators
switch to
STOP.
are on. The operator now
has control of the front
panel.
2-7.
EXAMINE MEMORY OPERATION (Table 2-5)
This procedure allows the operator to select a memory address
and examine its contents.
Table 2-5. Examine Memory Operation
Step Function Indication
1 Position the address
switches·Ao-Al5
..
down .
2 Position the
EXAMINE/
AO through Al5 indicators are
EX NEXT switch to
off, indicating memory address
EXAMINE.
location 000
8 is being
examined.
DATA DO through D7 indicators
are displaying the contents
of location
000
8.
3
~
Position address
switches
Al and A2
up.
4 Position the EXAMINE/
Al and A2 indicators are on,
EX NEXT switch to indicating
memory address 006
8
EXAMINE.
is being examined. DATA DO
through D7 indicators are dis-
playing the contents of loca-
tion
006
8.
2-7

2-8
,.-..,-:-. ...... ,;/~
_,!,,..I ~'-
: · .... ::
Step
1
2
3
4
.
•, . \
/ .. -'J _:
- .,.. ..... _.,_ - ,.... .....
-· ~ .:; . -- ""' ..) .
.L....... ... .... , ..... .,... .... .,
~..:; i ...: ._ .... ....
-~ ......... ,..... ...... .'
,,.,::, ,...., / - -
., ..... - .......
~:: ~ ... ,_. l -.:: :.:i .;
ccnt2:rts.
Table 2-6. Alterina Memory Contents
.,
Function Indication
Position address switch
A5 up and the remaining
switches
down.
Position the EXAMINE/
A5 indicator is on, indi-
EX NEXT switch to EXAMINE
eating memory address 040
8.
DATA DO through D7 indi-
caters are displaying the
contents of location
040
8.
Position the
AO through
A7 address switches up.
Position the DEPOSIT/OEP
DATA DO through 07 indi-
NEXT to DEPOSIT
caters are on, indicating
< the
new data that has been
placed in address location
0408.
2-9. EXAMINE NEXT MEMORY LOCATION (Table 2-7)
This procedure allows the operator to
examine the next sequential
memory location, as determined by the address switches.
Table 2-7.
Examine Next Memory Location
Step Function Indication
l Position address switches
AO and A5 up, and the re-
maining switches
down.
2 Position the
EXAMINE/EX AO and A5 indicators are
NEXT switch to EXAMINE on, indicating memory
address 041
8.
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0
Step
3
4
5
6
7
Table 2-7. Examine Next Memory Location -Continued
Function
Position address
switches Al, A4, and
A6 up, and the remain-
ing switches
down.
Position the DEPOSIT/
DEP NEXT switch to
DEPOSIT
Position address switch
A5 up, and the remaining
switches
down.
Position the EXAMINE/EX
NEXT switch to EX NEXT
Position the EXAMINE/EX
NEXT switch to EX NEXT
Indication
DATA Dl, D4, and D6 in-
dicators are
on.
A5 indicator is on, in-
dicating
memory address
040
8.
DATA DO through
D7 iridicators a~e on.
A5 and AO indicators are
on, indicating address
0418. DATA Dl, D4, and
D6 indicators are on.
2-10.
ALTER NEXT MEMORY LOCATION CONTENTS (Table 2-8)
This procedure allows the operator to select a memory address
and change the contents of the address that immediately follows.
Table 2-8. Altering
Next Memory Contents
Step Function Indication
1 Position address switches
AO and A5 up, and the re-
maining switches down.
2 Position the
EXAMINE/EX
AO and A5
indicators
NEXT switch to EXAMINE
are on.
3 Position address switches
AO through A7 up
2-9

2-10
5
6
: ~,..... - .; ........
' ... , .J •.., : ·-· :
Ci:? :>lc:X-T S',vi cci1 to CC:?
MEXT
To verify, position ad-
dress switches
AS and Al
up, and the remaining
switches
down .
. Position the
EXAMI~E/
EX NEXT switch to EXAMINE
,;.~,.., ., ·"'Ir·~ ... ":: --""\ '"'".'.:
' '_. ''' - ........... -..,,.... ' ..:
on, inaicati~g 042
8.
DATA DO through 07 are
on, displaying the
new
contents of location 042
8.
Al and AS indicators are
on,
and DATA DO through
07 are on.
. .
2-11. LOADING AND DISPLAYING ACCUMULATOR DATA (Table 2-9)
This procedure allows the operator to load new data into the
accumulator
or check the contents of the accumulator.
Step
l
2
3
• <
Table 2-9. Loading and Displaying Accumulator Data
Function
Position address switches
AO, Al, and A2 up, and the
remaining switches
down.
Position the ACCUMULATOR
DISPLAY/LOAD switch to LOAD
Position the ACCUMULATOR
DISPLAY/LOAD switch to
DISPLAY
Indication
DATA DO, 01, and D2
indicators are on
while "DISPLAY" is
activated.
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