6
(on the right) is the lowest-address ROM socket, and G1 (on the right)
is the highest-address ROM socket.
IC S (74 LS138) decodes which individual ROM is addressed, based on
versions of address bits A11, A12 and A13 that are latched by IC F
(74L75). The ROMs are addressed when both A14 and A14 are high, as
determined by the NAND gate at IC P (74L10). ROM data is gated into
the bus by IC Z (74LS244) when any of the ROMs is addressed, and when
PDBIN and SMEMR are both active.
Sense Switches
SW-2 has a DIP switch for each of the 8 data bits. A data bit will be
low if the switch is closed (grounding that bit, and will be pulled to
a high state by resistor pack RP2 (4.7 K-ohms) if the switch is open.
IC X (74LS244) gates the sense switch data onto the bus when the CPU
inputs from I/O port 377 (octal). IC D1 (74LS30) recognizes 377
(octal) on the address bus, and IC A (74L10) recognize a port input
cycle.
Serial Port
The serial port is based on the 6850 ACIA at IC C1.
The ACIA drives its data pins when PDBIN is active and the ACIA is
addressed during an I/O input cycle. ICs E1 (74LS04) and F1 (74LS30)
recognize 20 and 21 (octal) on the address bus, and IC E (74L10)
recognize a port input cycle. Address signal A0 determines whether the
ACIA drives its data channel or its status channel onto its data pins.
IC A1 (74LS244) gates the ACIA data onto the bus when the CPU inputs
from I/O port 20 or 21 (octal).
IC B1 (74LS244) drives the bus data onto the ACIA data pins when the
CPU performs any output cycle. If the output is to ports 20 or 21
(octal) then the ACIA will latch the data on the trailing edge of the
–PWR bus signal. Address signal A0 determines whether the ACIA data
channel or control channel is written to.
IC K (1488) and IC W (1489) serve as RS-232 drivers and receivers when
RS-232 levels are used. IC J (7404) is used to drive TTL signals. The
1489 also serves as the TTL-level receiver.
Pullup resistors R3, R4, and R5 (4.7 K-ohms) are available for unused
signal inputs, and are put in circuit with jumpers W13, W14, and W15.
C5 (1 uF) is available for slew-rate control on the RxD signal. This
capacitor is put in circuit with jumper W12.
Baud Rate Generator
The baud rate generator uses the 2 MHz CLK signal from the bus for its
time base.
ICs U, V, and H (all 74LS161s) form a 12-bit synchronous counter that
is clocked by the CLK signal. This counter counts up, and is re-loaded
with the value set by DIP switch SW-1 when it overflows. Thus, the SW-
1 controls the frequency of it reload signal, as detected by IC T
(74LS13). Note that to minimize the number of DIP switches, several
counter-reload bits are tied together. This has the side effect of