Mostek z80 User manual

MOSTEK CO
Z80
Technical Manual
MK3881
PARALLEL I/O
CONTROLLER

$2.00
Z80- PIO TECHNICAL MANUAL
TABLE OF CONTENTS
1.0 Introduction
2.0 Architecture
3.0 Pin Description 5
4.0 Programming the PIO 9
4.1 Reset 9
4.2 Loading the Interrupt Vector 9
4.3 Selecting an Operating Mode 10
4.4 Setting the Interrupt Control Word 11
5.0 Timing 13
5.1 Output Mode Timing 13
5.2 Input Mode Timing 13
5.3 Bidirectional Mode Timing 14
5.4 Control Mode 14
6.0 Interrupt Control 15
7.0 Applications 17
7.1 Interrupt Daisy Chain 17
7.2 I/O Device Interface 18
7.3 Control Interface 19
8.0 Programming Summary 21
8.1 Load Interrupt Vector 21
8.2 Set Mode 21
8.3 Set Interrupt Control 21
9.0 Electrical Specifications 23
9.1 Absolute Maximum Ratings 23
9.2 D.C. Characteristics 23
9.3 Clock Driver 23
9.4 A.C. Characteristics 24
9.5 Capacitance 24
10.0 Timing Chart 25

1.0 INTRODUCTION
The Z80 Parrallel I/O (PIO) Circuit is aprogrammable, two port device which provides aTTL
compatible interface between peripheral devices and the Z80-CPU. "rtie CPU can configure the Z80-PIO
to interface with awide range of peripheral devices with no other external logic required. Typical peripheral
devices that are fully compatible with the Z80-PIO include most keyboards, paper tape readers and
punches, printers, PROM programmers, etc. The Z80-PIO utilizes Nchannel silicon gate depletion load
technology and is packaged in a40 pin DIP. Major features of the Z80-PIO include:
•Two independent 8bit bidirectional peripheral interface ports with 'handshake' data transfer
control
•Interrupt driven 'handshake' for fast response
•Any one of four distinct modes of operation may be selected for aport including:
Byte output
Byte input
Byte bidirectional bus (Available on Port Aonly)
Bit control mode
All with interrupt controlled handshake
•Daisy chain priority interrupt logic included to provide for automatic interrupt vectoring without
external logic
•Eight outputs are capable of driving Darlington transistors.
•All inputs and outputs fully TTL compatible
•Single 5volt supply and single phase clock are required.
One of the unique freatures of the Z80-PIO that separates it from other interface controllers is that all
data transfer between the peripheral device and the CPU is accomplished under total interrupt control. The
interrupt logic of the PIO permits full usage of the efficient interrupt capabilities of the Z80-CPU during I/O
transfers. All logic necessary to implement afully nested interrupt structure is included in the PIO so that
additional circuits are not required. Another unique feature of the PIO is that it can be programmed to
interrupt the CPU on the occurrence of specified status conditions in the peripheral device. For example,
the PIO can be programmed to interrupt if any specified peripheral alarm conditions should occur. This
interrupt capability reduces the amount of time that the processor must spend in polling peripheral status.
1

2.0 PIO ARCHITECTURE
Ablock diagram of the Z80-PIO is shown in figure 2.0-1. The internal structure of the Z80-PIO
consists of aZ80-CPU bus interface, internal control logic, Port AI/O logic. Port BI/O logic, and interrupt
control logic. The CPU bus interface logic allows the PIO to interface directly to the Z80-CPU with no
other external logic. However, address decoders and/or line buffers may be required for large systems. The
internal control logic synchronizes the CPU data bus to the peripheral device interfaces (Port Aand Port B).
The two I/O ports (A and B) are virtually identical and are used to interface directly to peripheral devices.
+S' GNO *
iii
INTERNAL
CONTROL
LOGIC
CPU
INTERFACE^
<7H
DATA BUS
4-
PIO CONTROL
LINES
CPU
BUS
I/O cINTERNAL BUS
INTERRUPT
CONTROL
PORT
A
I/O
a'/ E
a
cHANDSHAKE
PORT
B
I/O
(]
—
y>DATA OR CONTROL
HANDSHAKE
PERIPHERAL
INTERFACE
INTERRUPT CONTROL LINES
FIGURE ZO-1
PIO BLOCK DIAGRAM
The Port I/O logic is composed of 6registers with "handshake" control logic as shown in figure 2.0-2.
The registers include: an 8 bit data input register, an 8bit data output register, a2bit mode control
register, an 8bit mask register, an 8bit input/output select register, and a2bit mask control register.
MODE
CONTROL
REG
(2 BITS)
INTERNAL BUS
INPUT/OUTPUT
SELECT REG
(8 BITS)
1OUTPUT
ENABLE
MASK
CONTROL
REG
(2 BITS)
MASK
REG
(8 BITS) cINPUT DATA
DATA
INPUT
REG
(8 BITS)
PERIPHERAL
DATA OR
CONTROL BUS
INTERRUPT ,
REQUESTS
HANDSHAKE READY^
1
CONTROL ^STROBE
a
LOGIC
,HANDSHAKE
LINES
FIGURE ZO-2
PORT I/O BLOCK DIAGRAM
3

The 2-bit mode control register is loaded by the CPU to select the desired operating mode (byte
output, byte input, byte bidirectional bus, or bit control mode). All data transfer between the peripheral
device and the CPU is achieved through the data input and data output registers. Data may be written into
the output register by the CPU or read back to the CPU from the input register at any time. The handshake
lines associated with each port are used to control the data transfer between the PIO and the peripheral
device.
The 8-bit mask register and the 8-bit input/output select register are used only in the bit control
mode. In this mode any of the 8peripheral data or control bus pins can be programmed to be an input or
an output as specified by the select register. The mask register is used in this mode in conjunction with a
special interrupt feature. This feature allows an interrupt to be generated when any or all of the unmasked
pins reach aspecified state (either high or low). The 2-bit mask control register specifies the active state
desired (high or low) and if the interrupt should be generated when all unmasked pins are active (AND
condition) or whenan>' unmasked pin is active (OR condition). This feature reduces the requirement for
CPU status checking of the peripheral by allowing an interrupt to be automatically generated on specific
peripheral status conditions. For example, in asystem with 3alarm conditions, an interrupt may be
generated if any one occurs or if all three occur.
The interrupt control logic section handles all CPU interrupt protocol for nested priority interrupt
structures. The priority of any device is determined by its physical location in adaisy chain configuration.
Two lines are provided in each PIO to form this daisy chain. The device closest to the CPU has the highest
priority. Within aPIO, Port Ainterrupts have higher priority than those of Port B. In the byte input, byte
output or bidirectional modes, an interrupt can be generated whenever anew byte transfer is requested by
the peripheral. In the bit control mode an interrupt can be generated when the peripheral status matches a
programmed value. The PIO provides for complete control of nested interrupts. That is, lower priority
devices may not interrupt higher priority devices that have not had their interrupt service routine com-
pleted by the CPU. Higher priority devices may interrupt the servicing of lower priority devices.
When an interrupt is accepted by the CPU in mode 2, the interrupting device must provide an 8-bit
interrupt vector for the CPU. This vector is used to form apointer to alocation in the computer memory
where the address of the interrupt service routine is located. The 8-bit vector from the interrupting device
forms the least significant 8bits of the indirect pointer while the IRegister in the CPU provides the most
significant 8bits of the pointer. Each port (A and B) has an independent interrupt vector. The least
significant bit of the vector is automatically set to awithin the PIO since the pointer must point to two
adjacent memory locations for acomplete 16-bit address.
The PIO decodes the RETI (Return from interrupt) instruction directly from the CPU data bus so
that each PIO in the system knows at all times whether it is being serviced by the CPU interrupt service
routine without any other communication with the CPU.
4

3.0 PIN DESCRIPTION
Adiagram of the Z80-PIO pin configuration is shown in figure 3.0-1. This section describes the
function of each pin.
D^-Dq Z80-CPU Data Bus (bidirectional, tristate)
This bus is used to transfer all data and commands between the Z80-CPU and the Z80-PIO.
Dq is the least significant bit of the bus.
B/A Sel Port Bor ASelect (input, active high)
This pin defines which port will be accessed during adata transfer between the Z80-CPU and
the Z80-PIO. Alow level on this pin selects Port Awhile ahigh level selects Port B. Often
Address bit Aq from the CPU will be used for this selection function.
C/D Sel Control or Data Select (input, active high)
This pin defines the type of data transfer to be performed between the CPU and the PIO. A
high level on this pin during aCPU write to the PIO causes the Z-80 data bus to be inter-
preted as acommand for the port selected by the B/A Select Hne. Alow level on this pin
means that he Z-80 data bus is being used to transfer data between the CPU and the PIO.
Often Address bit Aj from the CPU will be used for this function.
CE Chip Enable (input, active low)
Alow level on this pin enables the PIO to accept command or data inputs from the CPU
during awrite cycle or to transmit data to the CPU during aread cycle. This signal is
generally adecode of four I/O port numbers that encompass port Aand B, data and control.
$System Clock (input)
The Z80-PIO uses the standard Z-80 system clock to synchronize certain signals intemally.
This is asingle phase clock.
Ml Machine Cycle One Signal from CPU (input, active low)
This signalfrom the CPU isusedas async pulse to control several internal PIO operations.
When Ml is active and the RD signal is active, the Z80-CPU is fetching an instruction from
memory. Conversely, whenMlis active and lORQ is active, the CPU is acknowledging an
interrupt. In addition, the Ml Signal has two other functions within the Z80-PIO.
1.Ml synchronizes the PIO interrupt logic.
2. When Ml occurs without an active RD or lORQ signal the PIO logic enters areset
state.
lORQ Input/Output Request from Z80-CPU (input, active low)
The lORQ signal is used in conjunction with the B/A Select, C/D Select, CE, and RD signals
to transfer commands and data between the Z80-CPU and the Z80-PIO. When CE, RD and
lORQ are active, the port addressed by B/A will transfer data to the CPU (a read operation).
Conversely, when CE and lORQ are active but RD is not active, then the port addressed by
B/A will be written into from theCPU with either data or control information as specified
by the C/D Select signal. Also, if lORQ and Ml are active simultaneously, the CPU is
acknowledging an interrupt and the interrupting port will automatically place its interrupt
vector on the CPU data bus if it is the highest priority device requesting an interrupt.
RD Read Cycle Status from the Z80-CPU (input, active low)
If RD is active aMEMORY READ or I/O READ operation is in progress. The RD signal is
used with B/A Select, C/D Select, CE, and lORQ signals to transfer data from the Z80-PIO
to the Z80-CPU.
5

lEI Interrupt Enable In (input, active high)
This signal is used to form apriority interrupt daisy chain when more than one interrupt
driven device is being used. Ahigh level on this pin indicates that no other devices of higher
priority are being serviced by aCPU interrupt service routine.
lEO Interrupt Enable Out (output, active high)
The lEO signal is the other signal required to form adaisy chain priority scheme. It is high
only if lEI is high and the CPU is not servicing an interrupt from this PIO. Thus this signal
blocks lower priority devices from interrupting while ahigher priority device is being
serviced by its CPU interrupt service routine.
INT Interrupt Request (output, open drain, active low)
When INT is active the Z80-PIO is requesting an interrupt from the Z80-CPU.
Aq -Ay Port ABus (bidirectional, tristate)
This 8bit bus is used to transfer data and/or status or control information between Port A
of the Z80-PIO and aperipheral device. Aq is the least significant bit of the Port Adata bus.
ASTB Port AStrobe Pulse from Peripheral Device (input, active low)
The meaning of this signal depends on the mode of operation selected for Port Aas follows:
1) Output mode: The positive edge of this strobe is issued by the peripheral to
acknowledge the receipt of data made available by the PIO.
2) Input mode: The strobe is issued by the peripheral to load data from the peripheral
into the Port Ainput register. Data is loaded into the PIO when this signal is active.
3) Bidirectional mode: When this signal is active, data from the Port Aoutput register
is gated onto Port Abidirectional data bus. The positive edge of the strobe
acknowledges the receipt of the data.
4) Control mode: The strobe is inhibited internally.
ARDY Register AReady (output, active high)
The meaning of this signal depends on the mode of operation selected for Port Aas follows:
1) Output mode: This signal goes active to indicate that the Port Aoutput register has
been loaded and the peripheral data bus is stable and ready for transfer to the
peripheral device.
2) Input mode: This signal is active when the Port Ainput register is empty and is
ready to accept data from the peripheral device.
3) Bidirectional mode: This signal is active when data is available in the Port Aoutput
register for transfer to the peripheral device. In this mode data is not placed on the
Port Adata bus unless ASTB is active.
4) Control mode: This signal is disabled and forced to a low state.
Bq -Bj Port BBus (bidirectional, tristate)
This 8bit bus is used to transfer data and/or status or control information between Port B
of the PIO and aperipheral device. The Port Bdata bus is capable of supplying 1.5ma @
1.5 Vto drive Darlington transistors. Bq is the least significant bit of the bus.
BSTB Port BStrobe Pulse from Peripheral Device (input, active low)
The meaning of this signal is similar to that of ASTB with the following exception:
In the Port Abidirectional mode this signal strobes data from the peripheral device
into the Port Ainput register.
BRDY Register BReady (output, active high)
The meaning of this signal is similar to that of AReady with the following exception:
In the Port Abidirectional mode this signal is high when the Port Ainput register is
empty and ready to accept data from the peripheral device.
6

CPU
DATA <
BUS
n-^ 40
"6"*-
PORT B/A SEL
CONTROL/DATA SEL-
PIO .
CONTROL SCHIP ENABLE-
MT-
lORQ
RD
-H5V -
GND-
<1>-
INTERRUPT
CONTROL '
INT
INT ENABLE IN
INT ENABLE OUT
39
38
37
36
JTT? 35
26
11
25
23
24
22
Z80-PIO
MK 3881
15
14
13
12
10
18
16
27
28
29
30
31
32
33
34
21
17 -B RDY
-BSTB
PORTA
I/O
•ARDY
•A STB
PORT B
I/O
FIGURE 3.0-1
PIO PIN CONFIGURATION
7

1
9
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