Mostek z80 User manual

MOSTEK CO
Z80
Technical Manual
MK3881
PARALLEL I/O
CONTROLLER

$2.00
Z80- PIO TECHNICAL MANUAL
TABLE OF CONTENTS
1.0 Introduction
2.0 Architecture
3.0 Pin Description 5
4.0 Programming the PIO 9
4.1 Reset 9
4.2 Loading the Interrupt Vector 9
4.3 Selecting an Operating Mode 10
4.4 Setting the Interrupt Control Word 11
5.0 Timing 13
5.1 Output Mode Timing 13
5.2 Input Mode Timing 13
5.3 Bidirectional Mode Timing 14
5.4 Control Mode 14
6.0 Interrupt Control 15
7.0 Applications 17
7.1 Interrupt Daisy Chain 17
7.2 I/O Device Interface 18
7.3 Control Interface 19
8.0 Programming Summary 21
8.1 Load Interrupt Vector 21
8.2 Set Mode 21
8.3 Set Interrupt Control 21
9.0 Electrical Specifications 23
9.1 Absolute Maximum Ratings 23
9.2 D.C. Characteristics 23
9.3 Clock Driver 23
9.4 A.C. Characteristics 24
9.5 Capacitance 24
10.0 Timing Chart 25

1.0 INTRODUCTION
The Z80 Parrallel I/O (PIO) Circuit is aprogrammable, two port device which provides aTTL
compatible interface between peripheral devices and the Z80-CPU. "rtie CPU can configure the Z80-PIO
to interface with awide range of peripheral devices with no other external logic required. Typical peripheral
devices that are fully compatible with the Z80-PIO include most keyboards, paper tape readers and
punches, printers, PROM programmers, etc. The Z80-PIO utilizes Nchannel silicon gate depletion load
technology and is packaged in a40 pin DIP. Major features of the Z80-PIO include:
•Two independent 8bit bidirectional peripheral interface ports with 'handshake' data transfer
control
•Interrupt driven 'handshake' for fast response
•Any one of four distinct modes of operation may be selected for aport including:
Byte output
Byte input
Byte bidirectional bus (Available on Port Aonly)
Bit control mode
All with interrupt controlled handshake
•Daisy chain priority interrupt logic included to provide for automatic interrupt vectoring without
external logic
•Eight outputs are capable of driving Darlington transistors.
•All inputs and outputs fully TTL compatible
•Single 5volt supply and single phase clock are required.
One of the unique freatures of the Z80-PIO that separates it from other interface controllers is that all
data transfer between the peripheral device and the CPU is accomplished under total interrupt control. The
interrupt logic of the PIO permits full usage of the efficient interrupt capabilities of the Z80-CPU during I/O
transfers. All logic necessary to implement afully nested interrupt structure is included in the PIO so that
additional circuits are not required. Another unique feature of the PIO is that it can be programmed to
interrupt the CPU on the occurrence of specified status conditions in the peripheral device. For example,
the PIO can be programmed to interrupt if any specified peripheral alarm conditions should occur. This
interrupt capability reduces the amount of time that the processor must spend in polling peripheral status.
1

2.0 PIO ARCHITECTURE
Ablock diagram of the Z80-PIO is shown in figure 2.0-1. The internal structure of the Z80-PIO
consists of aZ80-CPU bus interface, internal control logic, Port AI/O logic. Port BI/O logic, and interrupt
control logic. The CPU bus interface logic allows the PIO to interface directly to the Z80-CPU with no
other external logic. However, address decoders and/or line buffers may be required for large systems. The
internal control logic synchronizes the CPU data bus to the peripheral device interfaces (Port Aand Port B).
The two I/O ports (A and B) are virtually identical and are used to interface directly to peripheral devices.
+S' GNO *
iii
INTERNAL
CONTROL
LOGIC
CPU
INTERFACE^
<7H
DATA BUS
4-
PIO CONTROL
LINES
CPU
BUS
I/O cINTERNAL BUS
INTERRUPT
CONTROL
PORT
A
I/O
a'/ E
a
cHANDSHAKE
PORT
B
I/O
(]
—
y>DATA OR CONTROL
HANDSHAKE
PERIPHERAL
INTERFACE
INTERRUPT CONTROL LINES
FIGURE ZO-1
PIO BLOCK DIAGRAM
The Port I/O logic is composed of 6registers with "handshake" control logic as shown in figure 2.0-2.
The registers include: an 8 bit data input register, an 8bit data output register, a2bit mode control
register, an 8bit mask register, an 8bit input/output select register, and a2bit mask control register.
MODE
CONTROL
REG
(2 BITS)
INTERNAL BUS
INPUT/OUTPUT
SELECT REG
(8 BITS)
1OUTPUT
ENABLE
MASK
CONTROL
REG
(2 BITS)
MASK
REG
(8 BITS) cINPUT DATA
DATA
INPUT
REG
(8 BITS)
PERIPHERAL
DATA OR
CONTROL BUS
INTERRUPT ,
REQUESTS
HANDSHAKE READY^
1
CONTROL ^STROBE
a
LOGIC
,HANDSHAKE
LINES
FIGURE ZO-2
PORT I/O BLOCK DIAGRAM
3

The 2-bit mode control register is loaded by the CPU to select the desired operating mode (byte
output, byte input, byte bidirectional bus, or bit control mode). All data transfer between the peripheral
device and the CPU is achieved through the data input and data output registers. Data may be written into
the output register by the CPU or read back to the CPU from the input register at any time. The handshake
lines associated with each port are used to control the data transfer between the PIO and the peripheral
device.
The 8-bit mask register and the 8-bit input/output select register are used only in the bit control
mode. In this mode any of the 8peripheral data or control bus pins can be programmed to be an input or
an output as specified by the select register. The mask register is used in this mode in conjunction with a
special interrupt feature. This feature allows an interrupt to be generated when any or all of the unmasked
pins reach aspecified state (either high or low). The 2-bit mask control register specifies the active state
desired (high or low) and if the interrupt should be generated when all unmasked pins are active (AND
condition) or whenan>' unmasked pin is active (OR condition). This feature reduces the requirement for
CPU status checking of the peripheral by allowing an interrupt to be automatically generated on specific
peripheral status conditions. For example, in asystem with 3alarm conditions, an interrupt may be
generated if any one occurs or if all three occur.
The interrupt control logic section handles all CPU interrupt protocol for nested priority interrupt
structures. The priority of any device is determined by its physical location in adaisy chain configuration.
Two lines are provided in each PIO to form this daisy chain. The device closest to the CPU has the highest
priority. Within aPIO, Port Ainterrupts have higher priority than those of Port B. In the byte input, byte
output or bidirectional modes, an interrupt can be generated whenever anew byte transfer is requested by
the peripheral. In the bit control mode an interrupt can be generated when the peripheral status matches a
programmed value. The PIO provides for complete control of nested interrupts. That is, lower priority
devices may not interrupt higher priority devices that have not had their interrupt service routine com-
pleted by the CPU. Higher priority devices may interrupt the servicing of lower priority devices.
When an interrupt is accepted by the CPU in mode 2, the interrupting device must provide an 8-bit
interrupt vector for the CPU. This vector is used to form apointer to alocation in the computer memory
where the address of the interrupt service routine is located. The 8-bit vector from the interrupting device
forms the least significant 8bits of the indirect pointer while the IRegister in the CPU provides the most
significant 8bits of the pointer. Each port (A and B) has an independent interrupt vector. The least
significant bit of the vector is automatically set to awithin the PIO since the pointer must point to two
adjacent memory locations for acomplete 16-bit address.
The PIO decodes the RETI (Return from interrupt) instruction directly from the CPU data bus so
that each PIO in the system knows at all times whether it is being serviced by the CPU interrupt service
routine without any other communication with the CPU.
4

3.0 PIN DESCRIPTION
Adiagram of the Z80-PIO pin configuration is shown in figure 3.0-1. This section describes the
function of each pin.
D^-Dq Z80-CPU Data Bus (bidirectional, tristate)
This bus is used to transfer all data and commands between the Z80-CPU and the Z80-PIO.
Dq is the least significant bit of the bus.
B/A Sel Port Bor ASelect (input, active high)
This pin defines which port will be accessed during adata transfer between the Z80-CPU and
the Z80-PIO. Alow level on this pin selects Port Awhile ahigh level selects Port B. Often
Address bit Aq from the CPU will be used for this selection function.
C/D Sel Control or Data Select (input, active high)
This pin defines the type of data transfer to be performed between the CPU and the PIO. A
high level on this pin during aCPU write to the PIO causes the Z-80 data bus to be inter-
preted as acommand for the port selected by the B/A Select Hne. Alow level on this pin
means that he Z-80 data bus is being used to transfer data between the CPU and the PIO.
Often Address bit Aj from the CPU will be used for this function.
CE Chip Enable (input, active low)
Alow level on this pin enables the PIO to accept command or data inputs from the CPU
during awrite cycle or to transmit data to the CPU during aread cycle. This signal is
generally adecode of four I/O port numbers that encompass port Aand B, data and control.
$System Clock (input)
The Z80-PIO uses the standard Z-80 system clock to synchronize certain signals intemally.
This is asingle phase clock.
Ml Machine Cycle One Signal from CPU (input, active low)
This signalfrom the CPU isusedas async pulse to control several internal PIO operations.
When Ml is active and the RD signal is active, the Z80-CPU is fetching an instruction from
memory. Conversely, whenMlis active and lORQ is active, the CPU is acknowledging an
interrupt. In addition, the Ml Signal has two other functions within the Z80-PIO.
1.Ml synchronizes the PIO interrupt logic.
2. When Ml occurs without an active RD or lORQ signal the PIO logic enters areset
state.
lORQ Input/Output Request from Z80-CPU (input, active low)
The lORQ signal is used in conjunction with the B/A Select, C/D Select, CE, and RD signals
to transfer commands and data between the Z80-CPU and the Z80-PIO. When CE, RD and
lORQ are active, the port addressed by B/A will transfer data to the CPU (a read operation).
Conversely, when CE and lORQ are active but RD is not active, then the port addressed by
B/A will be written into from theCPU with either data or control information as specified
by the C/D Select signal. Also, if lORQ and Ml are active simultaneously, the CPU is
acknowledging an interrupt and the interrupting port will automatically place its interrupt
vector on the CPU data bus if it is the highest priority device requesting an interrupt.
RD Read Cycle Status from the Z80-CPU (input, active low)
If RD is active aMEMORY READ or I/O READ operation is in progress. The RD signal is
used with B/A Select, C/D Select, CE, and lORQ signals to transfer data from the Z80-PIO
to the Z80-CPU.
5

lEI Interrupt Enable In (input, active high)
This signal is used to form apriority interrupt daisy chain when more than one interrupt
driven device is being used. Ahigh level on this pin indicates that no other devices of higher
priority are being serviced by aCPU interrupt service routine.
lEO Interrupt Enable Out (output, active high)
The lEO signal is the other signal required to form adaisy chain priority scheme. It is high
only if lEI is high and the CPU is not servicing an interrupt from this PIO. Thus this signal
blocks lower priority devices from interrupting while ahigher priority device is being
serviced by its CPU interrupt service routine.
INT Interrupt Request (output, open drain, active low)
When INT is active the Z80-PIO is requesting an interrupt from the Z80-CPU.
Aq -Ay Port ABus (bidirectional, tristate)
This 8bit bus is used to transfer data and/or status or control information between Port A
of the Z80-PIO and aperipheral device. Aq is the least significant bit of the Port Adata bus.
ASTB Port AStrobe Pulse from Peripheral Device (input, active low)
The meaning of this signal depends on the mode of operation selected for Port Aas follows:
1) Output mode: The positive edge of this strobe is issued by the peripheral to
acknowledge the receipt of data made available by the PIO.
2) Input mode: The strobe is issued by the peripheral to load data from the peripheral
into the Port Ainput register. Data is loaded into the PIO when this signal is active.
3) Bidirectional mode: When this signal is active, data from the Port Aoutput register
is gated onto Port Abidirectional data bus. The positive edge of the strobe
acknowledges the receipt of the data.
4) Control mode: The strobe is inhibited internally.
ARDY Register AReady (output, active high)
The meaning of this signal depends on the mode of operation selected for Port Aas follows:
1) Output mode: This signal goes active to indicate that the Port Aoutput register has
been loaded and the peripheral data bus is stable and ready for transfer to the
peripheral device.
2) Input mode: This signal is active when the Port Ainput register is empty and is
ready to accept data from the peripheral device.
3) Bidirectional mode: This signal is active when data is available in the Port Aoutput
register for transfer to the peripheral device. In this mode data is not placed on the
Port Adata bus unless ASTB is active.
4) Control mode: This signal is disabled and forced to a low state.
Bq -Bj Port BBus (bidirectional, tristate)
This 8bit bus is used to transfer data and/or status or control information between Port B
of the PIO and aperipheral device. The Port Bdata bus is capable of supplying 1.5ma @
1.5 Vto drive Darlington transistors. Bq is the least significant bit of the bus.
BSTB Port BStrobe Pulse from Peripheral Device (input, active low)
The meaning of this signal is similar to that of ASTB with the following exception:
In the Port Abidirectional mode this signal strobes data from the peripheral device
into the Port Ainput register.
BRDY Register BReady (output, active high)
The meaning of this signal is similar to that of AReady with the following exception:
In the Port Abidirectional mode this signal is high when the Port Ainput register is
empty and ready to accept data from the peripheral device.
6

CPU
DATA <
BUS
n-^ 40
"6"*-
PORT B/A SEL
CONTROL/DATA SEL-
PIO .
CONTROL SCHIP ENABLE-
MT-
lORQ
RD
-H5V -
GND-
<1>-
INTERRUPT
CONTROL '
INT
INT ENABLE IN
INT ENABLE OUT
39
38
37
36
JTT? 35
26
11
25
23
24
22
Z80-PIO
MK 3881
15
14
13
12
10
18
16
27
28
29
30
31
32
33
34
21
17 -B RDY
-BSTB
PORTA
I/O
•ARDY
•A STB
PORT B
I/O
FIGURE 3.0-1
PIO PIN CONFIGURATION
7

1
9
t'
9''

4.0 PROGRAMMING THE PIO
4.1 RESET
The Z80-PIO automatically enters areset state when power is applied. The reset state performs the
following functions:
1) Both port mask registers are reset.
2) Port data bus lines are set to ahigh impedance state and the Ready "handshake" signals are
inactive (low).
3) The vector address registers are not reset.
4) Both port interrupt enable flip flops are reset.
5) Both port output registers are reset.
In addition to the automatic power onreset,the PIOcan be reset by applying an Ml signal without
the presence of aRD or lORQ signal. If no RD or lORQ is detected during Ml the PIO will enter the reset
state immediately after the Ml signal goes inactive. The purpose of this reset is to allow asingle external
gate to generate areset without apower down sequence. This approach was required due to the 40 pin
packaging Umitation.
Once the PIO has entered the internal reset state it is held there until the PIO receives acontrol word
from the CPU.
4.2 LOADING THE INTERRUPT VECTOR
The PIO has been designed to operate with the Z80-CPU using the mode 2interrupt response. This
mode requires that an interrupt vector be suppHed by the interrupting device. This vector is used by the
CPU to form the address for the interrupt service routine of that port. This vector is placed on the Z-80 data
bus during an interrupt acknowledge cycle by the highest priority device requesting service at that time.
(Refer to the Z80-CPU Technical Manual for details on how an interrupt is serviced by the CPU). The
desired interrupt vector is loaded into the PIO by writing a control word to the desired port of the PIO with
the following format:
D7 D6 D5 D4 D3 D2 Dl DO
V7 V6 V5 V4 V3 V2 VI ^signifies this control word is an interrupt
vector
DO is used in this case as a flag bit which when low causes V7 thru VI to be loaded into the vector register.
At interrupt acknowledge time, the vector of the interrupting port will appear on the Z-80 data bus exactly
as shown in the format above.
9

4.3 SELECTING AN OPERATING MODE
Port Aof the PIG may be operated in any of four distinct modes: Mode (output mode), Mode 1
(input mode), Mode 2(bidirectional mode), and Mode 3(control mode). Note that the mode numbers have
been selected for mnemonic significance; i.e. O=0ut, l=In, 2=Bidirectional. Port Bcan operate in any of
these modes except Mode 2.
The mode of operation must be established by writing acontrol word to the PIG in the following
format:
D7 D6 D5 D4 D3 D2 Dl DO
Ml MO XX1111X=unused bit
s/
mode word
—\/
signifies mode word
to be set
Bits Ml and MO from the binary code for the desired mode according to the following table:
ModeMl
1
1
Mq
1
1
(output)
1(input)
2(bidirectional)
3(control)
Bits D5 and D4 are ignored. Bits D3-D0 must be set to 1111 to indicate "Set Mode".
Selecting Mode enables any data written to the port output register by the CPU to be enabled onto
the port data bus. The contents of the output register may be changed at any time by the CPU simply by
writing anew data word to the port. Also the current contents of the output register may be read back to
the Z80-CPU at any time through the execution of an input instruction.
With Mode active, adata write from the CPU causes the Ready handshake line of that port to go
high to notify the peripheral that data is available. This signal remains high until astrobe is received from
the peripheral. The rising edge of the strobe generates an interrupt (if it has been enabled) and causes the
Ready line to go inactive. This very simple handshake is similar to that used in many peripheral devices.
Selecting Mode 1puts the port into the input mode. To start handshake operation, the CPU merely
performs an input read operation from the port. This activates the Ready line to the peripheral to signify
that data should be loaded into the empty input register. The peripheral device then strobes data into the
port input register using the strobe line. Again, the rising edge of the strobe causes an interrupt request (if
it has been enabled) and deactivates the Ready signal.
Mode 2is abidirectional data transfer mode which uses all four handshake lines. Therefore only Port
Amay be used for Mode 2operation. Mode 2operation uses the Port Ahandshake signals for output
control and the Port Bhandshake signals for input control. Thus, both ARDY and BRDY may be active
simultaneously. The only operational difference between Mode and the output portion of Mode 2is that
data from the Port Aoutput register is allowed on to the port data bus orJy when ASTB is active in order
to achieve abidirectional capability.
Mode 3operation is intended for status and control applications and does not utilize the handshake
signals. When Mode 3is selected, the next control word sent to that port defines which of the port data bus
lines are to be inputs and which are outputs. The format of the control word is shown below:
D7 D6 D5 D4 D3 D2 Dl DO
I/G7 V06 I/G5 I/G4 I/G3 I/O2 I/O I
10

If any bit is set to aone, then the corresponding data bus line will be used as an input. Conversely, if the bit
is reset, the line will be used as an output.
During Mode 3operation the strobe signal is ignored and the Ready line is held low. Data may be
written to aport or read from aport by the Z80-CPU at any time during Mode 3operation. When reading
aport, the data returned to the CPU will be composed of input data from port data bus lines assigned as
inputs plus port output register data from those lines assigned as outputs.
4.4 SETTING THE INTERRUPT CONTROL WORD
The interrupt control word for each port has the following format:
D7 D6 D5 D4 D3 D2 Dl DO
Enable
Interrupt AND/
OR High/
Low Masks follows 111
used in Mode 3 only signifies interrupt control word
If bit D7=l the interrupt enable flip flop of the port is set and the port may generate an interrupt. If bit
D7=0 the enable flag is reset and interrupts may not be generated. If an interrupt is pending when the
enable flag is set, it will then be enabled onto the CPU interrupt request line. Bits D6, D5, and D4 are used
only with Mode 3operation. They are disregarded for all other modes. These three bits are used to allow for
interrupt operation in Mode 3when any group of the I/O lines go to certain defined states. Bit D6 (AND/
OR) defines the logical operation to be performed in port monitoring. If bit D6=l an AND function is
specified and if D6=0, an OR function is specified. For example, if the AND function is specified, all bits
must go to aspecified state before an interrupt will be generated while the OR function will generate an
interrupt if any specified bit goes to the active state.
Bit D5 defines the active polarity of the port data bus line to be monitored. If bit D5=l the port data
lines are monitored for ahigh state while if D5=0 they will be monitored for alow state.
If bit D4=l the next control word sent to the port will be interpreted as amask as follows:
D7 D6 D5 D4 D3 D2 Dl DO
MB-j MBg MB5 MB4 MB3 MB2 MBj MBq
Only those port lines whose mask bit is zero will be monitored for generating an interrupt.
11

&
4
3a;

5.0 TIMING
5.1 OUTPUT MODE (MODE 0)
Figure 5.0-1 illustrates the timing associated with Mode operation. An output cycle is always started
by the execution of an output instruction by the CPU. The low level of the WR signal is used to latch the
data from the CPU data bus into the addressed port's (A or B) output register. The rising edge of the write
pulse then raises the Ready flag after the next falling edge of $to indicate that data is available for the peri-
pheral device. In most systems the rising edge of the Ready signal can be used as alatching signal in the
peripheral device if desired. The Ready signal will remain active until apositive edge is received from the
strobe line indicating that the peripheral has taken the data. However, the Ready signal will not go inactive
until afalling edge occurs on the clock ($) line. The purpose of delaying the negative transition of the
Ready signal until after anegative clock transition is that it allows for avery simple generation scheme for
the strobe pulse. By merely connecting the Ready line to the Strobe line, astrobe with aduration of one
clock period will be generated with no other logic required. The positive edge of the strobe pulse auto-
matically generates an INT request if the interrupt enable flip flop has been set and this device is the highest
priority device requesting an interrupt.
5.2 INPUT MODE (MODE 1)
Figure 5.0-2 illustrates the timing of an input cycle. The peripheral initiates this cycle using the strobe
line after the CPU has performed adata read. Alow level on this line loads data into the port input register
and the rising edge of the strobe line activates the interrupt request line (INT) if the interrupt enable is
set and this is the highest priority requesting device. The next falling edge of the clock line ($) will then
reset the Ready Une to an inactive state signifying that the input register is full and further loading must be
inhibited until the CPU reads the data. The CPU will in the course of its interrupt service routine, read the
data from the interrupting port. When this occurs, the positive edge from the CPU read signal will raise the
Ready line with the next low going transition of indicating that new data can be loaded into the PIG.
MODE lOUTPUTI TIMING
WR* >: RD CE -£75- lORQ
FIGURE 5.0-1
MODE (OUTPUT) TIMING
RD* =RD •CE •C/D •lORO
FIGURE &0-2
MODE 1(INPUT) TIMING
13

5.3 BIDIRECTIONAL MODE (MODE 2)
This mode is merely acombination of Mode and Mode 1using all four handshake lines. Since it
requires all four lines, it is available only on Port A. When this mode is used on Port A, Port Bmust be set
to the Bit Control Mode. Figure 5.0-3 illustrates the timing for this mode. It is almost identical to that pre-
viously described for Mode and Mode 1with the Port Ahandshake lines used for output control and the
Port Blines used for input control. The difference between the two modes is that, in Mode 2, data is
allowed out onto the bus only when the Astrobe is low. The rising edge of this strobe can be used to latch
the data into the peripheral since the data will remain stable until after this edge. The input portion of
Mode 2operates identically to Mode 1
.
BRDY \_
WR» =RD CE •C/D •lORQ FIGURE 5.0-3
PORT A, MODE 2(BIDIRECTIONAL) TIMING
The peripheral must notgate data onto aport data bus while ASTB is active. Bus contention is
avoided if the peripheral uses BSTB to gate input data onto the bus. The PIG uses the BSTB low level to
latch this data. The PIG has been designed with azero hold time requirement for the data when latching in
this mode so that this simple gating structure can be used by the peripheral. That is, the data can be disabled
from the bus immediately after the strobe rising edge.
5.4 CONTROL MODE (MODE 3)
The control mode does not utilize the handshake signals and anormal port write or port read can be
executed at any time. When writing, the data will be latched into output registers with the same timing as
Mode 0.
When reading the PIG, the data returned to the CPU will be composed of output register data from
those port data lines assigned as outputs and input register data from those port data lines assigned as
inputs. The input register will contain data which was present immediately prior to the falling edge of RD.
An interrupt will be generated if interrupts from the port are enabled and the data on the port data
lines satisfies the logical equation defined by the 8-bit mask and 2-bit mask control registers.
PORT
DATA BUS
INT
lORO
~)[DATA WORD 1XDATA WORD 2](~
CH \_
DATA MATCH \Ll(
OCCURS HERE '"
RD
(DATA IN 1
•Inserted by 280-CPU "ata word iplaced on bus
FIGURE 5.0-4
14

6.0 INTERRUPT SERVICING
Sometime afte ran interrupt is requested by the PIO, the CPU will send out an interrupt acknowl-
edge (Ml and lORQ). During this time the interrupt logic of the PIO will determine the highest priority
port which is requesting an interrupt. (This is simply the device with its Interrupt Enable Input high and
its Interrupt Enable Output low). To insure that the daisy chain enable lines stabilize, devices are inhibited
from changing their interrupt request status when Ml is active. The highest priority device places the con-
tents of its interrupt vector register onto the Z80 data bus during interrupt acknowledge.
Figure 6.0-1 illustrates the timing associated with interrupt requests. During Ml time, no new
interrupt requests can be generated. This gives time for the Int Enable signals to ripple through up to four
PIO circuits. The PIO with lEI high and lEO low during INTA will place the 8-bit interrupt vector of the
appropriate port on the data bus at this time.
IE!
•Inserted by Z80-CPU FIGURE 6.0-1
INTERRUPT ACKNOWLEDGE TIMING
lEO is held low until areturn from interrupt (RETI) Instruction is executed while lEI is high. The
PIO chip decodes the 2byte RETI instruction internally.
Figure 6.0-2 illustrates atypical nested interrupt sequence that could occur with four ports connected
in the daisy chain. In this sequence Port 2A requests and is granted an interrupt. While this port is being
serviced, ahigher priority port (IB) requests and is granted an interrupt. The service routine for the higher
priority port is completed and aRETI instruction is executed to indicate to the port that its routine is
complete. At this time the service routine of the lower priority port is completed.
15

HIGHEST PRIORITY PORT
4PORT 1A PORT IB PORT 2A PORT 2B
|H, lEI lEO HI IE! lEO HI lEI lEO HI lEI lEO HI
1. PRIORITY INTERRUPT DAISY CHAIN BEFORE ANY INTERRUPT OCCURS.
UNDER SERVICE
1lEI lEO HI lEI lEO HI lEI lEO LO lEI lEO LO
2. PORT 2A REOUESTS AN INTERRUPT AND IS ACKNOWLEDGED.
UNDER SERVICE SERVICE SUSPENDED
1"' lEI lEO HI lEI lEO LO lEI lEO LO lEI lEO LO
3. PORT IB INTERRUPTS, SUSPENDS SERVICING OF PORT 2A.
SERVICE COMPLETE SERVICE RESUMED
1lEI lEO HI lEI lEO HI lEI lEO LO lEI lEO LO
4. PORT IB SERVICE ROUTINE COMPLETE, "RETI" ISSUED, PORT 2A SERVICE RESUMED.
SERVICE COMPLETE
lEI lEO HI lEI lEO HI lEI lEO HI lEI lEO HI
5. SECOND "RETI" INSTRUCTION ISSUED ON COMPLETfON OF PORT 2A SERVICE ROUTINE.
FIGURE &0-2
DAISY CHAIN INTERRUPT SERVICING
16

7.0 APPLICATIONS
7.1 EXTENDING THE INTERRUPT DAISY CHAIN
Without any external logic, amaximum of four Z80-PIO devices may be daisy chained into apriority
interrupt structure. This limitation is required so that the interrupt enable status (lEO) ripples through the
entire chain between the beginning of Ml, and the beginning of lORQ during an interrupt acknowledge
cycle. Since the interrupt enable status cannot change during Ml, the vector address returned to the CPU
is assured to be from the highest priority device which requested an interrupt.
If more than four PIO devices must be accommodated, a"look-ahead" structure may be used as
shown in figure 7.0-1 .With this technique more than thirty PIO's may be chained together using standard
TTL logic.
no
El lEO
no
lEI lEO
no
lEI lEO
no
lEI lEOl—
ZID-CPU
no
lEO
no
El IE(
no
HIEO lEI
no
HEO lEI
>
DATA BUS >
FIGURE 7.0-1
AMETHOD OF EXTENDING THE INTERRUPT PRIORITY DAISY CHAIN
7.2 I/O DEVICE INTERFACE
In this example, the Z80-PIO is connected to an I/O terminal device which communicates over an
8bit parallel bidirectional data bus as illustrated in figure 7.0-2. Mode 2operation (bidirectional) is selected
by sending the following control word to Port A:
D7 D6 D5 04 D3 D2 Dl DO
1XX1111
Mode Control
17

ARDY
ASTB
BRDY
BSTB
Z80-CPU
MK 3880
.
CDATA BUS >
lORQ
Ml
INT
Z80-PIO
MK 3881
B/A c/D CE
ADDRESS BUC> ADDRESS
BUS
DECODER
CPOBT DATA BUS >
DDDD
SRRA
TQCV
BV
D
I/O
TERMINAL
FIGURE 7.0-2
EXAMPLE I/O INTERFACE
Next, the proper interrupt vector is loaded (refer to CPU Manual for details on the operation of the
interrupt).
V7 V6 V5 V4 V3 V2 VI
Interrupts are then enabled by the rising edge of the first after the interrupt mode word is set unless
that Ml defines an interrupt acknowledge cycle. If amask follows the interrupt mode word, interrupts are
enabled by the rising edge of the first Ml following the setting of the mask.
Data can now be transferred between the peripheral and the CPU. The timing for this transfer is as
described in Section 5.0.
18