N.A.T. NAT-MCH Product manual

NAT-MCH HUB-Module SRIO –Technical Reference Manual
NAT-MCH
TCA Telecom MCH Module
Technical Reference Manual V 1.5
HUB-Module SRIO HW Revision 2.2

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 2
The NAT-MCH Hub Module SRIO has been designed by:
N.A.T. GmbH
Konrad-Zuse-Platz 9
D-53227 Bonn-Oberkassel
Phone: +49 / 228 / 965 864 - 0
Fax: +49 / 228 / 965 864 - 10
Internet: http://www.nateurope.com

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 3
Disclaimer
The following documentation, compiled by N.A.T. GmbH (henceforth called N.A.T.),
represents the current status of the product’s development. The documentation is
updated on a regular basis. Any changes which might ensue, including those necessitated
by updated specifications, are considered in the latest version of this documentation.
N.A.T. is under no obligation to notify any person, organization, or institution of such
changes or to make these changes public in any other way.
We must caution you, that this publication could include technical inaccuracies or
typographical errors.
N.A.T. offers no warranty, either expressed or implied, for the contents of this
documentation or for the product described therein, including but not limited to the
warranties of merchantability or the fitness of the product for any specific purpose.
In no event will N.A.T. be liable for any loss of data or for errors in data utilization or
processing resulting from the use of this product or the documentation. In particular,
N.A.T. will not be responsible for any direct or indirect damages (including lost profits,
lost savings, delays or interruptions in the flow of business activities, including but not
limited to, special, incidental, consequential, or other similar damages) arising out of the
use of or inability to use this product or the associated documentation, even if N.A.T. or
any authorized N.A.T. representative has been advised of the possibility of such
damages.
The use of registered names, trademarks, etc. in this publication does not imply, even in
the absence of a specific statement, that such names are exempt from the relevant
protective laws and regulations (patent laws, trade mark laws, etc.) and therefore free
for general use. In no case does N.A.T. guarantee that the information given in this
documentation is free of such third-party rights.
Neither this documentation nor any part thereof may be copied, translated, or reduced to
any electronic medium or machine form without the prior written consent from N.A.T.
GmbH.
This product (and the associated documentation) is governed by the N.A.T. General
Conditions and Terms of Delivery and Payment.
Note:
The release of the Hardware Manual is related to a certain HW board revision
given in the document title. For HW revisions earlier than the one given in the
document title please contact N.A.T. for the corresponding older Hardware
Manual release.

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 4
Table of Contents
DISCLAIMER ....................................................................................................... 3
TABLE OF CONTENTS .......................................................................................... 4
LIST OF TABLES.................................................................................................. 5
LIST OF FIGURES................................................................................................ 5
CONVENTIONS.................................................................................................... 6
1INTRODUCTION ........................................................................................... 7
2OVERVIEW ................................................................................................... 9
2.1 MAJOR FEATURES......................................................................................... 9
2.2 BLOCK DIAGRAM ........................................................................................10
2.3 LOCATION DIAGRAM ....................................................................................11
3FUNCTIONAL BLOCKS ................................................................................ 12
3.1 SRIO SWITCHES ........................................................................................12
3.2 MICROCONTROLLER .....................................................................................15
3.3 INTERFACES ..............................................................................................16
3.4 UPLINK OPTION..........................................................................................16
4HARDWARE ................................................................................................ 17
4.1 CONNECTORS ............................................................................................17
4.1.1 CON1: HUB-Module SRIO Backplane Connector ....................................18
4.1.2 CON2: HUB-Module x48 Extender Connector........................................20
4.1.3 CON3: CLK-Module Connector............................................................22
4.1.4 CON4: Uplink-Module Connector.........................................................23
4.1.5 Uplink1: 1st Face Plate Interface .........................................................24
4.1.6 Uplink2: 2nd Face Plate Interface ........................................................24
5PROGRAMMING NOTES .............................................................................. 25
5.1 SPI INTERFACE ..........................................................................................25
5.2 I²C INTERFACE ..........................................................................................25
5.3 REGISTER.................................................................................................25
5.3.1 Board Identifier Register ...................................................................25
5.3.2 PCB Revision Register .......................................................................26
5.3.3 Firmware Version .............................................................................26
5.3.4 Hub Module SRIO Type .....................................................................26
5.3.5 Miscellaneous Control Register ...........................................................27
6BOARD SPECIFICATION ............................................................................. 28
7INSTALLATION .......................................................................................... 29
7.1 SAFETY NOTE ............................................................................................29
7.2 INSTALLATION PREREQUISITES AND REQUIREMENTS ...............................................29
7.2.1 Requirements ..................................................................................29
7.2.2 Power supply ...................................................................................29
7.2.3 Automatic Power Up..........................................................................29
7.3 STATEMENT ON ENVIRONMENTAL PROTECTION ......................................................30
7.3.1 Compliance to RoHS Directive ............................................................30
7.3.2 Compliance to WEEE Directive............................................................30
7.3.3 Compliance to CE Directive ................................................................31

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Version 1.5 © N.A.T. GmbH 5
7.3.4 Product Safety .................................................................................31
7.3.5 Compliance to REACH .......................................................................31
8KNOWN BUGS / RESTRICTIONS................................................................. 32
APPENDIX A: REFERENCE DOCUMENTATION .................................................... 33
APPENDIX B: DOCUMENT’S HISTORY ............................................................... 34
List of Tables
Table 1: List of used Abbreviations ...................................................................... 6
Table 2: 1st Switch to Fabric Port Mapping ...........................................................13
Table 3: 2nd Switch to Fabric Port Mapping ..........................................................13
Table 4: Switch Port Mapping.............................................................................14
Table 5: Switch Port Mapping NATIVE-R5 or NATIVE-C5 ........................................14
Table 6: CON1: HUB-Module SRIO Backplane Connector - Pin Assignment..............18
Table 7: CON2: HUB-Module x48 Extender Backplane Connector –Pin Assignment..20
Table 8: CON3: CLK-Module Connector –Pin Assignment ......................................22
Table 9: CON4: Uplink-Module Connector –Pin Assignment...................................23
Table 10: Uplink1: 1st Face Plate Interface –Pin Assignment ...................................24
Table 11: Uplink2: 2nd Face Plate Interface –Pin Assignment ..................................24
Table 12: Board Identifier Register .......................................................................25
Table 13: PCB_REV Register ................................................................................26
Table 14: FW_VERSION Register..........................................................................26
Table 15: SRIO_TYPE Register .............................................................................26
Table 16: MISC_CTL Register ..............................................................................27
Table 17: MISC_CTL - Register Bits ......................................................................27
Table 18: NAT-MCH HUB-Module SRIO Features ....................................................28
List of Figures
Arrangement of different NAT-MCH Modules ............................................. 7Figure 1:
NAT-MCH HUB-Module SRIO –Block Diagram .........................................10Figure 2:
NAT-MCH HUB-Module SRIO –Location diagram (top)..............................11Figure 3:
NAT-MCH HUB-Module SRIO –Location diagram (bottom) ........................11Figure 4:
NAT-MCH HUB-Module SRIO –Connectors (top) ......................................17Figure 5:
NAT-MCH HUB-Module SRIO –Connectors of the (bottom) .......................17Figure 6:

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 6
Conventions
If not otherwise specified, addresses and memory maps are written in hexadecimal
notation, identified by 0x.
The following table gives a list of the abbreviations used in this document:
Table 1: List of used Abbreviations
Abbreviation
Description
AMC
Advanced Mezzanine Card
b
bit, binary
B
Byte
ColdFire
MCF5470
CPU
Central Processing Unit
CU
Cooling Unit
DMA
Direct Memory Access
E1
2.048 Mbit G.703 Interface
FLASH
Programmable ROM
FRU
Field Replaceable Unit
J1
1,544 Mbit G.703 Interface (Japan)
K
kilo (factor 400 in hex, factor 1024 in decimal)
LIU
Line Interface Unit
M
mega (factor 10,0000 in hex, factor 1,048,576 in decimal)
MCH
µTCA Carrier Hub
MHz
1,000,000 Herz
µTCA
Micro Telecommunications Computing Architecture
PCIe
PCI Express
PCI
Peripheral Component Interconnect
PM
Power Manager
RAM
Random Access Memory
ROM
Read Only Memory
SDRAM
Synchronous Dynamic RAM
SRIO
Serial Rapid IO
SSC
Spread Spectrum Clock
T1
1,544 Mbit G.703 Interface (USA)

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 7
1Introduction
The NAT-MCH consists of a BASE-Module, which can be expanded with additional
PCBs. The BASE-Module satisfies the basic requirements of the MicroTCA Specification
for a MicroTCA Carrier Hub. The main capabilities of the BASE-Module are:
management of up to 12 AMCs, two cooling units (CUs) and one or more
power modules (PMs)
Gigabit Ethernet Hub Function for Fabric A (up to 12 AMCs) and for the
Update Fabric A to a second (redundant) NAT-MCH
To meet also the optional requirements of the MicroTCA specification, a CLK-Module and
different HUB Modules are available. With the CLK-Module the following functions can
be enabled:
generation and distribution of synchronized clock signals for up to 12 AMCs
Through the extension of the NAT-MCH with a HUB-Module, hub functions for fabric D
to G can be enabled. With the different versions the customers have the opportunity to
choose a HUB-Module that fits best to their applications. The versions differ in:
max. number of supported AMCs (up to 6 / up to 12)
supported protocols:
PCI Express
Serial Rapid IO
10Gigabit Ethernet
The features of the individual modules are described in more detail in the corresponding
Technical Reference Manuals.
A general arrangement of the different modules of a NAT-MCH is shown in the following
figure.
Arrangement of different NAT-MCH ModulesFigure 1:
LED Module
Basic Module CLK Module
Hub Module
This Technical Reference Manual describes the NAT-MCH HUB-Module SRIO. In
addition to the CLK-Module it can be mounted on the NAT-MCH BASE-Module. The
HUB-Module SRIO is in a 6 Slot (“x24”) and in a 12 slot (“x48”) option available. With
the HUB-Module SRIO the 3rd tongue of the NAT-MCH connector to the MicroTCA
backplane is always installed. With the x48 option, additional the 4th tongue is installed.
The NAT-MCH HUB-Module SRIO implements the following major features:
support of SRIO x4 switching function for fabrics D to G of up to 6 AMCs (HUB-
Module SRIO x24)
support of SRIO x4 switching function for fabrics D to G of up to 12 AMCs (HUB-
Module SRIO x48)

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 8
support of up to two SRIO x4 face plate uplinks and/or a SRIO x4 fabric update to
the second MCH (Uplink Option)
The HUB-Module SRIO contains out of two IDT CPS-1848 SRIO switches. The first SRIO
switch connects to AMC 1-6. This switch is subsequent referred as 1st switch or 1st CPS-
1848. The second SRIO switch connects to AMC 7-12. This switch is subsequent referred
as 2nd switch or 2nd CPS-1848.

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2Overview
2.1 Major Features
Configurable x1 or x4 SRIO interfaces to 12 AMC modules
backplane update fabric to second MCH
operation baud rate per data lane 1.25 Gbit/s, 2.5 Gbit/s, 3.125 Gbit/s, 5Gbit/s or
6.25Gbit/s
1
*
two optional face plate uplinks
transport layer error management
low latency packet transport
configuration interface via onboard microcontroller
3 onboard temperature sensors
1
Because of a chip bug 6.25Gbaud is not supported. Please refer to chapter “known bugs
and restrictions” for a more detailed description

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 10
2.2 Block Diagram
The following figure shows a block diagram of the NAT-MCH HUB-Module SRIO and
optional available extension modules.
NAT-MCH HUB-Module SRIO –Block DiagramFigure 2:
1st Serial
SRIO GenII
SWITCH
(CPS-1848)
backplane connector
tongue 3 (Harting Plug)
SPI/
I²C
NAT-MCH
HUB-Module SRIO
Gen II
fabric D to G
to AMC 1-6
x4 SRIO
Micro-
controller
Connector to
Basic-PCB
Temp.-
sensor
2nd Serial
SRIO GenII
SWITCH
(CPS-1848)
three x4
SRIO
backplane connector
tongue 4 (Harting Plug)
Temp.-
sensor
I²C
I²C
Only for x48
I²C
I²C
to AMC 7-12
x4 SRIO
Temp.-
sensor
I²C
Infiniband
Connector
Infiniband
Connector
X4 SRIO
Update Fabric*
On Face Plate
x4 SRIO
x4 SRIO
fabric D to G
to 2nd MCH
* Only the Update Fabrics for fabric D and E are connected via the tongue 3
backplane connector. The Update Fabrics for fabric F and G are connected via
the tongue 4 backplane connector. To simplify the diagram this is not shown.

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Version 1.5 © N.A.T. GmbH 11
2.3 Location Diagram
The following figures show the position of important components of the NAT-MCH HUB-
Module SRIO.
NAT-MCH HUB-Module SRIO –Location diagram (top)Figure 3:
NAT-MCH HUB-Module SRIO –Location diagram (bottom)Figure 4:

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3Functional Blocks
The NAT-MCH HUB-Module SRIO is divided into a number of functional blocks, which
are described in the following paragraphs.
3.1 SRIO Switches
The board is equipped with two IDT CPS-1848 Serial Rapid IO switches, which provide
non-blocking high performance data switching functionality. Data integrity and health
checks are performed by hardware. The CPS-1848 offers 12.5 Gbit/s bandwidth per port
(x4) combined with a low latency packet transport. Additional a flexible port width (x1 or
x4) and different operating baud rates (1.25Gbit/s, 2.5Gbit/s and 3.125Gbit/s) can be
selected.
Each of the twoCPS-1848 SRIO Switches supports 6 ports, each with 4 lanes (SRIO x4),
in order to connect 6 AMCs. Three ports with 4 lanes are used to connect the two
Switches. The first switch supports also a 4-lane port to connect to a second MCH via the
backplane update fabrics D-G. Furthermore two four lane ports of the first switch are
used to supports the optional face plate uplinks.
Both CPS-1848 can be configured by strapping pins, by loading an EEPROM, or by
accessing the TSI register interface via I²C from the microcontroller. A standard
configuration is done by the microprocessor and resistors, by setting the strapping pins.
The values of the strapping signals that are connected to the microcontroller can be
controlled by programming a register in the microcontroller.
These standard settings can be changed by reading the EEPROM after a reset, or by
changing the values of the TSI register interface with the help of the microcontroller (via
I²C interface).
The intended way of standard configuration is that the microcontroller performs the basic
setup via strapping. By default the EEPROM contains basic settings that need to be done
to configure the device regarding the board and system requirements. The MCH firmware
is then able to initialize (or terminate) each port to the needed speed and port width.
The first port of the switch is not connected to the first port of fabric D-G, and so on. To
ease routing of the differential fabrics between the switches and the backplane
connectors the following allocation has been selected.

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 13
Table 2: 1st Switch to Fabric Port Mapping
# AMC Slot Fabric D-G
# Port - 1st CPS-1848
AMC1
9
AMC2
1
AMC3
4
AMC4
11
AMC5
3
AMC6
6
MCH Update
(backplane connection to 2nd MCH)
5
1st switch interconnect:
connection to port # 2 of the
2nd CPS-1848
0
2nd switch interconnection:
connection to port # 10 of the
2nd CPS-1848
7
3rd switch interconnection:
connection to port # 5 of the
2nd CPS-1848
8
Face plate uplink 1
2
Face plate uplink 2
10
Table 3: 2nd Switch to Fabric Port Mapping
# AMC Slot Fabric D-G
#Port - 2nd CPS-1848
AMC7
1
AMC8
8
AMC9
0
AMC10
7
AMC11
11
AMC12
6
1st switch interconnect:
connection to port # 0 of the
1st CPS-1848
2
2nd switch interconnection:
connection to port # 7 of the
1st CPS-1848
10
3rd switch interconnection:
connection to port # 8 of the
1st CPS-1848
5

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 14
Under some conditions it might be more useful to have the ports mapping sorted by the
switch ports. Therefore the following table shows again the switch port mapping sorted
by the switch ports.
Table 4: Switch Port Mapping
Port #
Assignment –Switch 1
Assignment –Switch 2
0
1st switch interconnect
AMC9
1
AMC2
AMC7
2
Uplink1
1st switch interconnect
3
AMC5
-
4
AMC3
-
5
MCH update
3rd switch interconnect
6
AMC6
AMC12
7
2nd switch interconnect
AMC10
8
3rd switch interconnect
AMC8
9
AMC1
-
10
Uplink2
2nd switch interconnect
11
AMC4
AMC11
All previous ports mapping are considering a 1-to-1 connecting backplane. In case a
NATIVE-R5 or NATIVE-C5 chassis is used the following port mapping have to be
considered due to the backplane topology of these chassis.
Table 5: Switch Port Mapping NATIVE-R5 or NATIVE-C5
# AMC Slot Fabric D-G
SRIO ports
1-To-1
Connecting
Backplane
NATIVE-C5
NATIVE-R5
# Port - 1st CPS-
1848
9
AMC1
AMC2
1
AMC2
AMC3
4
AMC3
AMC4
11
AMC4
AMC5
3
AMC5
AMC6
6
AMC6
AMC7
#Port - 2nd CPS-
1848
1
AMC7
AMC1
8
AMC8
n/a
0
AMC9
n/a
7
AMC10
n/a
11
AMC11
n/a
6
AMC12
n/a

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Version 1.5 © N.A.T. GmbH 15
3.2 Microcontroller
An 8-bit Atmel microcontroller resides on the NAT-MCH HUB-Module SRIO. The
microcontroller can be updated by the CPU on the BASE-Module via the SPI interface.
Normal communication between the CPU and the microcontroller is done by IPMI
messages via the I²C interface.
The strapping options and the reset signal of the switches can be controlled through
programming registers in the microcontroller.
Furthermore each switch is connected to a separate I²C bus. Via these buses the
microcontroller has access to the register interface of the switches.
Also three temperature sensors are connected to the I²C bus that connects the 1st
Switch. The microcontroller makes these sensors and the register interfaces of the
switches accessible to the CPU on the BASE-Module via IPMI.

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 16
3.3 Interfaces
The NAT-MCH HUB-Module SRIO implements interfaces to connect fabrics D to G of up
to 12 AMCs. It also supports the Update Fabric D to G to the second MCH.
As an additional option the NAT-MCH Hub Module SRIO supports up to two x4 SRIO
uplinks on the face plate (see chapter 3.4 for details).
3.4 Uplink Option
With the uplink option it is possible to connect to the SRIO fabric up to two face plate
connectors. This is an assembly option and therefore need to be chosen when ordered.
If the uplink option is assembled the baud rate of each uplink connection can be
configured. The following options are available:
1.25Gbit/s
2.5 Gbit/s
3.125 Gbit/s
5 Gbit/s
6.25 Gbit/s
2
disabled (default setting)
The individual modes can configured within the NAT-MCH configuration settings (SRIO
setting). For a more detailed description of the MCH configuration please refer to the
NAT-MCH User’s manual.
2
Because of a chip bug 6.25Gbaud is not supported. Please refer to chapter “known bugs
and restrictions” for a more detailed description

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 17
4Hardware
4.1 Connectors
NAT-MCH HUB-Module SRIO –Connectors (top)Figure 5:
NAT-MCH HUB-Module SRIO –Connectors of the (bottom)Figure 6:
Please refer to the following tables to look up the pin assignment of the NAT-MCH HUB-
Module SRIO.

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Version 1.5 © N.A.T. GmbH 18
4.1.1 CON1: HUB-Module SRIO Backplane Connector
Table 6: CON1: HUB-Module SRIO Backplane Connector
- Pin Assignment
Pin #
MCH-Signal
MCH-Signal
Pin #
1
GND
GND
170
2
RSVD
RSVD
169
3
RSVD
RSVD
168
4
GND
GND
167
5
RSVD
RSVD
166
6
RSVD
RSVD
165
7
GND
GND
164
8
TxFUD+
RxFUD+
163
9
TxFUD-
RxFUD-
162
10
GND
GND
161
11
TxFUE+
RxFUE+
160
12
TxFUE-
RxFUE-
159
13
GND
GND
158
14
TxFD1+
RxFD1+
157
15
TxFD1-
RxFD1-
156
16
GND
GND
155
17
TxFE1+
RxFE1+
154
18
TxFE1-
RxFE1-
153
19
GND
GND
152
20
TxFF1+
RxFF1+
151
21
TxFF1-
RxFF1-
150
22
GND
GND
149
23
TxFG1+
RxFG1+
148
24
TxFG1-
RxFG1-
147
25
GND
GND
146
26
TxFD2+
RxFD2+
145
27
TxFD2-
RxFD2-
144
28
GND
GND
143
29
TxFE2+
RxFE2+
142
30
TxFE2-
RxFE2-
141
31
GND
GND
140
32
TxFF2+
RxFF2+
139
33
TxFF2-
RxFF2-
138
34
GND
GND
137
35
TxFG2+
RxFG2+
136
36
TxFG2-
RxFG2-
135
37
GND
GND
134
38
TxFD3+
RxFD3+
133
39
TxFD3-
RxFD3-
132
40
GND
GND
131
41
TxFE3+
RxFE3+
130
42
TxFE3-
RxFE3-
129
43
GND
GND
128
44
TxFF3+
RxFF3+
127
45
TxFF3-
RxFF3-
126

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 19
Pin #
MCH-Signal
MCH-Signal
Pin #
46
GND
GND
125
47
TxFG3+
RxFG3+
124
48
TxFG3+
RxFG3-
123
49
GND
GND
122
50
TxFD4+
RxFD4+
121
51
TxFD4-
RxFD4-
120
52
GND
GND
119
53
TxFE4+
RxFE4+
118
54
TxFE4-
RxFE4-
117
55
GND
GND
116
56
TxFF4+
RxFF4+
115
57
TxFF4-
RxFF4-
114
58
GND
GND
113
59
TxFG4+
RxFG4+
112
60
TxFG4-
RxFG4-
111
61
GND
GND
110
62
TxFD5+
RxFD5+
109
63
TxFD5-
RxFD5-
108
64
GND
GND
107
65
TxFE5+
RxFE5+
106
66
TxFE5-
RxFE5-
105
67
GND
GND
104
68
TxFF5+
RxFF5+
103
69
TxFF5-
RxFF5-
102
70
GND
GND
101
71
TxFG5+
RxFG5+
100
72
TxFG5-
RxFG5-
99
73
GND
GND
98
74
TxFD6+
RxFD6+
97
75
TxFD6-
RxFD6-
96
76
GND
GND
95
77
TxFE6+
RxFE6+
94
78
TxFE6-
RxFE6-
93
79
GND
GND
92
80
TxFF6+
RxFF6+
91
81
TxFF6+
RxFF6-
90
82
GND
GND
89
83
TxFG6+
RxFG6+
88
84
TxFG6-
RxFG6-
87
85
GND
GND
86

NAT-MCH HUB-Module SRIO –Technical Reference Manual
Version 1.5 © N.A.T. GmbH 20
4.1.2 CON2: HUB-Module x48 Extender Connector
Table 7: CON2: HUB-Module x48 Extender Backplane Connector
–Pin Assignment
Pin #
MCH-Signal
MCH-Signal
Pin #
1
GND
GND
170
2
RSVD
RSVD
169
3
RSVD
RSVD
168
4
GND
GND
167
5
RSVD
RSVD
166
6
RSVD
RSVD
165
7
GND
GND
164
8
TxFUF+
RxFUD+
163
9
TxFUF-
RxFUD-
162
10
GND
GND
161
11
TxFUG+
RxFUE+
160
12
TxFUG-
RxFUE-
159
13
GND
GND
158
14
TxFD7+
RxFD7+
157
15
TxFD7-
RxFD7-
156
16
GND
GND
155
17
TxFE7+
RxFE7+
154
18
TxFE7-
RxFE7-
153
19
GND
GND
152
20
TxFF7+
RxFF7+
151
21
TxFF7-
RxFF7-
150
22
GND
GND
149
23
TxFG7+
RxFG7+
148
24
TxFG7-
RxFG7-
147
25
GND
GND
146
26
TxFD8+
RxFD8+
145
27
TxFD8-
RxFD8-
144
28
GND
GND
143
29
TxFE8+
RxFE8+
142
30
TxFE8-
RxFE8-
141
31
GND
GND
140
32
TxFF8+
RxFF8+
139
33
TxFF8-
RxFF8-
138
34
GND
GND
137
35
TxFG8+
RxFG8+
136
36
TxFG8-
RxFG8-
135
37
GND
GND
134
38
TxFD9+
RxFD9+
133
39
TxFD9-
RxFD9-
132
40
GND
GND
131
41
TxFE9+
RxFE9+
130
42
TxFE9-
RxFE9-
129
43
GND
GND
128
44
TxFF9+
RxFF9+
127
45
TxFF9-
RxFF9-
126