National Semiconductor LMH1983 User manual

LMH1983 Evaluation Kit Users Guide
Page 1 of 25
LMH1983 Evaluation Kit Users Guide
Version 1.0
2/4/10

LMH1983 Evaluation Kit Users Guide
Page 2 of 25
INTRODUCTION
The LMH1983 Evaluation Kit (EVK) allows for the evaluation of the LMH1983
3G/HD/SD Video Clock Generator with Audio Clock. The LMH1983 device is
configured and controlled using National Semiconductor’s Analog Launch Pad (ALP)
software graphical user interface (GUI).
The GUI with the LMH1983 profile runs on Windows PC and can be used to program the
device’s control registers through the I2C interface. The Serial Peripheral Adapter (SPA)
board included in the kit provides I2C read/write control via the USB port of the PC with
the GUI. For more information about the GUI software and device register descriptions
and programming, please refer to the GUI software manual and LMH1983 datasheet.
Overview of LMH1983
The LMH1983 clock generator generates four video specific clocks. The device has four
PLLs in it.
PLL1 uses an external 27 MHz VCXO, and always generates a 27MHz reference
clock. This clock may be locked to an input reference which can be any of a
number of different types of reference – from video specific references to single
frequency reference signals.
PLL2 is dedicated to generating a 148.5 MHz clock (27 MHz * 5.5) , and is
locked to PLL1.
PLL3 is dedicated to generating a clock at 148.35 MHz (27 MHz * 5500/1001)
PLL4, by default is locked to PLL1, and generates a 24.576MHz clock which can
be used as an audio clock. PLL4 has a lot of versatility built in to it and can be
used for a broad variety of applications.

LMH1983 Evaluation Kit Users Guide
Page 3 of 25
LMH1983 EVALUATION BOARD OVERVIEW
The following block diagram shows an overview of the LMH1983 evaluation board and
general location of the main features, which will be discussed in the following sections of
this manual.
Applying power to the board:
The default configuration to apply power is to apply +5V across the top two pins on J8.
With a jumper on JP17, and on board LDO is used to generate the 3.3V rail that powers
the circuits on the evaluation board.
Alternately, JP17 may be removed, and a 3.3V rail may be applied directly to the bottom
two pins of J8.
LMH
1981
J2
LMH1983
Quad
2:1
MUX
VCXO
X2
J8
J1
J3
J7
J4
J6
J5
LP
3878
Power
Header
Analog
Ref. In BNC
Status LEDs
VCXO
X1
LPF
CLKout1
SMA
CLKout4
SMAs
CLKout3
SMA
CLKout2
SMA
HVF
in
p
uts
Syncs
EXT.HVF
CLK
(VCXO
or SMA)
CLK In
SMA
Power LEDs
J9
USB
Port

LMH1983 Evaluation Kit Users Guide
Page 4 of 25
Installing the software:
The evaluation kit contains a CD which has the control software on it. Running the
program on the CD will install the software on your computer.
Apply power to the Evaluation Board, and then attach a USB cable between the computer
and the board. Windows will recognize the board and pop up the
When this window comes up, select ‘No, not this time’ and ‘Next>’

LMH1983 Evaluation Kit Users Guide
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Select “Install from a list or specific location”

LMH1983 Evaluation Kit Users Guide
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LMH1983 Evaluation Kit Users Guide
Page 7 of 25
For the location, enter “C:\Program Files\National Semiconductor Corp\Analog
Launchpad Vxxx\DRIVERS” This directory was installed on your computer during the
ALP software installation.
The computer will warn you that the software has not passed Windows Logo Testing. Go
ahead and Continue Anyway.
The driver for the LMH1983 evaluation board will now be installed, and you can start the
ALP software.
When you start the Analog LaunchPAD software, it should recognize the evaluation
board and the screen will look like the figure below.
If the board is not connected properly, or not powered up, the ALP software will start up
in a demo mode which will look like the normal mode, but will not control the board.
Once the startup screen appears, click on the LMH1983 icon on the left side of the
window, and this will bring up the GUI:

LMH1983 Evaluation Kit Users Guide
Page 8 of 25
The status indications on the GUI are only updated when the Read Controls/Status button
is clicked. To have continuous updates, click the checkbox ‘Auto Refresh Status’, I also
like to check the ‘Perform ReadAll after write’ box – this will update all of the status
controls whenever something is written. In some cases, writing to one register will result
in multiple things changing, and checking this button will make sure that everything is
kept updated.
There are several panels in the GUI - the first is the main control panel and allows for
basic control over the board. Also very useful is the Registers tab, which will allow for
detailed manipulation of the various registers in the LMH1983.

LMH1983 Evaluation Kit Users Guide
Page 9 of 25
I2C SLAVE ADDRESS
The I2C address select jumper JP9 (3-way) can be configured as follows to select one of
the three I2C slave addresses offered by the LMH1983. The default for the board, and
for the ALP software is address ‘66h which corresponds to no jumper installed.
Table 1: LMH1983 I2C Slave Address Selection
7-bit I2C Slave Address JP1 Jumper Setting LMH1983 Address Input State
65’h (hex) Short Pins 1-2 Externally tied low
66’h Open Pins Internally biased to mid-supply
67’h Short Pins 2-3 Externally tied high
Observing the Outputs
The LMH1983 generates four clock signals (CLKout1, CLKout2, CLKout3, CLKout4)
and four timing signals (TOF1, TOF2, TOF3, TOF4). The LMH1983 outputs are
differential outputs, and can be observed directly at JP13, JP14, JP15 and JP16. There
are 100Ωtermination resistors situated near the connectors (R60,R66, R73 and R78). If
the differential signals are to be observed with a high impedance differential scope probe,
it can be attached directly to the pins. If it is desired that the differential outputs drive a
load, the load resistor should be moved to be adjacent to the final load. In addition to the
differential outputs, there are 50Ohm single ended outputs as well. These are provided
by using LMH0302 SDI cable drivers. On the initial version of the evaluation board
these outputs exhibit some undershoot and ringing at 4GHz which degrades the jitter
performance of these outputs.
Configuring the board for operation with an analog video
reference signal
The LMH1983 Evaluation board includes an LMH1981 sync separator which is able to
extract the timing signals from a broad range of analog sync signals. To use this feature,
install a jumper on JP4 (MUX ENABLE), and one on JP3 (Input Select). Supply the
reference signal to J1 (analog Ref In), and you can monitor the extracted H, V and F
signals at the yellow test points just to the left of the LMH1983.
The GUI will display what format is being detected under the PLL1
The LMH1983 can automatically detect and synchronize to the following reference input
formats received at its input pins:
HVF Sync timing from SMPTE standard video formats
o525i/29.97/30
o525p/59.94/60

LMH1983 Evaluation Kit Users Guide
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o625i/25
o625p/50
o720p/23.98/24/25/29.97/30/50/59.94/60
o1080i/25/29.97/30
o1080p/23.98/24/25/29.97/30/50/59.94/60
o1080pSf/23.98/24/25/29.97/30
Audio Word Clock
o32 kHz, 48 kHz, 96 kHz, 44.1 kHz
System Clock
o27 MHz
o10 MHz
Configuring the board for operation with a digital video
reference signal
An external digital reference signal, consisting of H,V and F may be applied to J2, a
jumper should installed on JP5, and the jumper on JP3 should be removed.
The GUI will display what format is being detected under the PLL1
For a comprehensive list of formats that can be detected, please refer to the LMH1983
datasheet. To determine format, the device measures the period of the Hsync input by
counting 27MHz clock pulses over several Hsync periods. There are some standards
where Hsync may be the same, in which case V and F are examined to determine if the
reference is an interlaced or progressive format before format detection is complete.
Configuring the board for operation in free-run mode, using
the on board reference oscillator
To operate the board in ‘stand-alone mode’, remove the jumper for JP3, make sure that
the jumper is removed from JP5, and in this mode, the frequency can be trimmed via R20
– the trim pot near the lower left corner of the board.
Configuring the board for operation, locked to an external
clock oscillator.
To operate the board locked to an external clock, supply the reference signal through the
SMA connector ‘J3’, remove the jumper form JP3 and install a jumper on JP5.
The automatic format detect algorithm in the LMH1983 will recognize reference clocks
of 27MHz or 10MHz. Other reference rates can be manually programmed.

LMH1983 Evaluation Kit Users Guide
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LMH1983 Evaluation Kit Users Guide
Page 12 of 25
PLL1 LOOP FILTER AND VCXO
The LMH1983’s primary phase lock loop, PLL1, provides the following key functions:
Synchronizes the 27 MHz VCXO clock to the reference input
Attenuates (cleans) input jitter
Provides a stable, low-jitter 27 MHz clock for PLLs 2, 3, 4
The external loop filter and 27 MHz VCXO are essential to the performance of PLL1,
which dominates the overall loop response of the LMH1983. The loop response of PLL1
is influenced by the external loop components and can be characterized by its loop
bandwidth and damping factor.
PLL1 is designed for a nominal loop bandwidth of about 3 Hz (min) and damping factor
of 0.70 (min). These were calculated using the approximations below, which assume
nominal ICP1 = 250uA and DIV_N1 = 1716 for the NTSC input format:
Loop Bandwidth (BW) = R47*ICP1*KVCO / DIV_N1
Damping Factor (DF) = 0.5*R47*sqrt[ (C33 || C39)*ICP1*KVCO / DIV_N1 ]
Loop Filter
The loop filter components include R47, C39 || C40, and C33. It’s recommended to
avoid use of ceramic capacitors in the loop filter since they exhibit piezoelectric
properties that can cause electrical noise when the board/component is subjected to
vibration or shock. This “shock noise” in the loop filter circuit can result in low-
frequency phase modulation on the VCXO output clock and thus on the downstream PLL
output clocks. Tantalum and film capacitors are used for the loop filter since they do not
exhibit piezo effects.

LMH1983 Evaluation Kit Users Guide
Page 13 of 25
Figure 1: Loop Filter and LMP7711 Buffer Schematic
Op Amp Buffer
The LMP7711 Precision, Low-Noise Op Amp (U4) is used as a buffer to isolate the
relatively low input impedance of the VCXO, which would otherwise be the dominant
source of leakage current for loop filter circuit. The op amp offers very high input
impedance to minimize this leakage current and high slew rate to ensure proper loop
operation. The VCXO input control voltage input can be measured at TP29 (VC_BUF).
Note that when the LMH1983 is operating in free run mode, the VC_LPF output set by
the user-defined free run voltage control register may be limited by the output voltage
range of the LMP7711, as it is not a rail-to-rail op amp.

LMH1983 Evaluation Kit Users Guide
Page 14 of 25
VCXO
The 27 MHz VCXO (X2) is specified for ±50 ppm APR (min) and ±50 ppm frequency
stability. The calculated VCXO gain is 1000 Hz/V (min). The VCXO gain parameter
(KVCO) affects the PLL1 loop response, so it must be considered when designing the
nominal loop bandwidth and damping factor.
The VCXO’s single-ended output clock can be measured at TP26 (XOclk+). The VCXO
clock is received at the XOin+ input of the LMH1983. XOin+ (pin 34) and XOin- (pin
33) are differential inputs for the internal op amp that drives the clock signal to the PLL
blocks. Because XOin is a differential input, the XOin- pin is biased to about 1.25V
using a voltage divider formed by R52 and R56. This input configuration presents a
pseudo-differential signal to the XOin pins.
Alternatively, the single-ended VCXO may be replaced with a different 27 MHz VCXO
with differential clock outputs (e.g. LVDS); in this case, R52, R56, and C48 should be
removed, R54 should be populated with 49.9R to match R55, and R37 should be
populated with a 100R differential load. Using a true differential input signal can provide
more common-mode rejection and reduce noise/crosstalk, and thus reduce sources of
deterministic jitter.
INDEPENDENT AUDIO CLOCK GENERATION
By default, the audio clock generated from PLL4 is phase-locked to the 27 MHz VCXO
clock reference from PLL1, and in turn, is synchronized to the reference input.
It is possible to have the audio clock independently generated from an external 27 MHz
clock source by changing the PLL4 input mux mode via register programming. Once the
PLL4 input mode is properly programmed, pin 17 (normally Fout4) is switched to an
input pin (OSCin) and can be driven with an external 27 MHz clock.
There are two options for an independent 27 MHz clock source. The first option is to use
an on-board 27 MHz VCXO in the footprint X2. The second option is to receive an
external 27 MHz via the SMA clock input, J3. Either one of the options can be used as
long as it’s not being used to drive the Hin reference of the LMH1983. To make use of
this option, populate R21 and R28, then to use the on board oscillator, enable it by
removing the jumper on JP5, and to use the external SMA, disable the oscillator with a
jumper on JP5 and provide the reference on J3.

LMH1983 Evaluation Kit Users Guide
Page 15 of 25
Appendix A
Schematics

1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Title
Number RevisionSize
C
Date: 11/3/2009 Sheet of
File: C:\Projects\..\LMH1983 Demo Board.SchDocDrawn By:
3V3
VDD_XO
100 O HM DIFF. IMPEDANCE
VDD_XO
LMH1983 Evaluation Board
10uF
C44
0
R51
0
R53
4.75k
R39
4.75k
R41
1 2
JP12
TP18
F_IN
TP17
V_IN
TP16
H_IN
TP20
ADDR
TP29
VC_BUF
OPEN
C40
TP19
INIT
1
2
3
JP9
I2C ADDR SEL
3V3
Fout1
Fout2
Fout3
Layout Note: JP Legend is
"Disable XO"
3V3
TP28
VDD_XO
Layout Note: XO Legend is
"27MHz VCXO"
Layout Note: TP Legend is
"VDD_XO"
Layout Note:
Pin legend is:
"65h = Pin 1-2"
"66h = Float Pin 2"
"67h = Pin 2-3"
VDD
Layout Note:
TP Legend is
"XO_CLK"
HIN
VIN
FIN
INIT
OPEN
R33
OPEN
R30
OPEN
R34
OPEN
R31
OPEN
R32
0.1uF
C32 33
R38
33
R42 33
R40
33R26
NOALIGN
NOREF
NOLOCK
0.1uF
C25
0.1uF
C23
0.1uF
C21
33R24
0.01uF
C43
0.1uF
C42
OPEN
C47
0.1uF
C46
250mA
220 ohm
L4
VC 1
OUT
4
GND
3
EN 2
VCC 6
OUTA
5
X2
357LB3I027M0000
OPEN
R37
49.9R55
OPENR54
0.1uF
C48
CLKout1_P
CLKout1_N
TP26
XOclk+
CLKout4_P
CLKout4_N
OPEN
R36
Note: XOin pair can be driven by a VCXO with LVCMOS clock
or LVDS clock.
-LVCMOS (default):
XOin+: Connect to VCXO's single-ended output.
XOin-: Bias to 1.65VDC via 1.00k divider resistors using the
VCXO's supply (VDD_XO) and local ground for optimal CMR.
OUTA (VCXO pin 5): No connect (N/C)
-LVDS:
XOin+/-: Connect to VCXO's LVDS output and terminated with
100R differential.
OUTA: Complementary LVDS output pin. Remove 1k resistors
and 0.1uF cap and install series resistor.
XOin_P
XOin_N
XOin_P XOin_N
4
1
2
3
JP11
I2C CONN
Layout Note: Place JP3
near edge of PCB.
Pin Legend is:
"GND" (pin 1)
"N/C" (pin 2)
"SCL" (pin 3)
"SDA" (pin 4)
NOLOCK
NOALIGN
NOREF
Rev. 1
TP12
Fout4
0
R44
1uF
C20
1uF
C22
1uF
C24
VDD
1uF
C45 1uF
C41
33
R43
33
R45
OPEN
C38
OPEN
C37
OPEN
C36
TP23
NO_LOCK
TP24
NO_ALIGN
TP25
NO_REF
OPEN
C30
OSCin
Fout433R27
TP13
Fout3
OPEN
C29
33R25
TP14
Fout2
OPEN
C27
TP15
Fout1
OPEN
C26
47uF
C39
OPEN
R49
TP21
SDA
TP22
SCL
OPEN
R28
Layout Note: Pin Legend is
"Fout1" (inline w/ JP11.2)
"Fout2" (inline w/ JP12.2)
"Fout3" (inline w/ JP13.2)
"Fout4" (inline w/ JP14.2)
"GND" (inline w/ pin 1 of JP11, JP12, JP13, JP14)
OPEN
C31
OPEN
C28
Layout Note: Unless otherwise noted, label all
ICs, Test Points, Jumpers and Headers per the
component comment. For jumpers and headers,
label pins according to the pin legend noted. All
labels should be present on top and bottom silk
screen (except for ICs).
PLL1 Loop Filter and VCXO
TP27
VC
OPEN
C34
OPEN
C35
GN D
18
GND
21
GND
39
DAP
VDD_PLL1 1
VDD_IO 2 VDD_IO 10
VDD_CLK4 16
VDD_PLL34 19
VDD_CLK3 20 VDD_CLK2 31
VDD_PLL2 32
VDD_CLK1 38
CLKout1+ 36
CLKout1- 35
Fout1 37
CLKout2+ 28
CLKout2- 29
Fout2 30
Fout3 22
CLKout3+ 23
CLKout3- 24
CLKout4- 14
CLKout4+ 15
Fout4/OSCin 17
Hin
3
Vin
4
Fin
5
INIT
6
ADDR
7
SDA
8
SCL
9
NO_LOCK 11
NO_ALIGN 12
NO_REF 13
Cbyp3 25 Cbyp4 26 Cbyp2 27
XOin-
33 XOin+
34
VC_LPF 40
U3
LMH1983SQ
OPEN
R29
OPEN
R35
OPEN
R46
CLKout2_N
CLKout2_P
CLKout3_N
CLKout3_P
CLKout1_P
CLKout1_N
CLKout2_N
CLKout3_N
CLKout4_N
CLKout4_P
CLKout3_P
CLKout2_P
VDD_PLL1
VDD_PLL2
VDD_PLL34
VDD_CLK4
VDD_CLK3
VDD_CLK2
VDD_CLK1
Layout Note: Pin 17 is a programmable I/O pin.
When the pin is an output, the resistor should be
populated for net "Fout4" (default). When the pin
is an input, the other resistor should be populated
for net "OSCin". Minimize trace stubs on this
pin.
4 3
2
1
6
5
V+
V-
U4
LMP7711MK
1uF
C33
Fout1
Fout2
Fout3
Fout4
10.0k
R48
OPEN
R50
VDD_XO
Layout Note: On Fout* pins and pins 11, 12, 13,
place direct components as close to LMH1983 as
possible.
1
2
JP6
1
2
JP7
1
2
JP8
1
2
JP10
3.0k
R52
1.82k
R56
17.4k
R47
SDA
SCL
LMH1983 Eval Board - LMH1983
B
Sauerwald
45
PIC2001
PIC2002
COC20
PIC2101
PIC2102
COC21
PIC2201
PIC2202
COC22
PIC2301
PIC2302
COC23
PIC2401
PIC2402
COC24
PIC2501
PIC2502
COC25
PIC2601
PIC2602
COC26
PIC2701
PIC2702
COC27
PIC2801
PIC2802
COC28
PIC2901
PIC2902
COC29
PIC3001
PIC3002
COC30
PIC3101
PIC3102
COC31
PIC3201
PIC3202
COC32
PIC3301 PIC3302
COC33
PIC3401
PIC3402
COC34
PIC3501
PIC3502
COC35
PIC3601
PIC3602
COC36
PIC3701
PIC3702
COC37
PIC3801
PIC3802
COC38
PIC3901 PIC3902
COC39
PIC4001 PIC4002
COC40
PIC4101
PIC4102
COC41
PIC4201
PIC4202
COC42
PIC4301
PIC4302
COC43
PIC4401
PIC4402
COC44
PIC4501
PIC4502
COC45
PIC4601
PIC4602
COC46
PIC4701
PIC4702
COC47
PIC4801
PIC4802
COC48
PIJP601
PIJP602
COJP6
PIJP701
PIJP702
COJP7
PIJP801
PIJP802
COJP8
PIJP901
PIJP902
PIJP903
COJP9
PIJP1001
PIJP1002
COJP10
PIJP1101
PIJP1102
PIJP1103
PIJP1104
COJP11
PIJP1201PIJP1202
COJP12
PIL401 PIL402
COL4
PIR2401 PIR2402
COR24
PIR2501 PIR2502
COR25
PIR2601 PIR2602
COR26
PIR2701 PIR2702
COR27
PIR2801 PIR2802
COR28
PIR2901
PIR2902
COR29
PIR3001
PIR3002
COR30
PIR3101
PIR3102
COR31
PIR3201
PIR3202
COR32
PIR3301
PIR3302
COR33
PIR3401
PIR3402
COR34
PIR3501
PIR3502
COR35
PIR3601
PIR3602
COR36
PIR3701 PIR3702
COR37
PIR3801 PIR3802
COR38
PIR3901 PIR3902
COR39
PIR4001 PIR4002
COR40
PIR4101 PIR4102
COR41
PIR4201 PIR4202
COR42
PIR4301 PIR4302
COR43
PIR4401
PIR4402
COR44
PIR4501 PIR4502
COR45
PIR4601
PIR4602
COR46
PIR4701PIR4702
COR47
PIR4801
PIR4802
COR48
PIR4901
PIR4902
COR49
PIR5001
PIR5002
COR50
PIR5101
PIR5102
COR51
PIR5201
PIR5202
COR52
PIR5301 PIR5302
COR53
PIR5401 PIR5402
COR54
PIR5501 PIR5502
COR55
PIR5601
PIR5602
COR56
PITP1201
COTP12
PITP1301
COTP13
PITP1401
COTP14
PITP1501
COTP15
PITP1601
COTP16
PITP1701
COTP17
PITP1801
COTP18
PITP1901
COTP19
PITP2001
COTP20
PITP2101
COTP21
PITP2201
COTP22
PITP2301
COTP23
PITP2401
COTP24
PITP2501
COTP25
PITP2601
COTP26
PITP2701
COTP27
PITP2801
COTP28
PITP2901
COTP29
PIU301PIU302
PIU303
PIU304
PIU305
PIU306
PIU307
PIU308
PIU309
PIU3010
PIU3011
PIU3012
PIU3013
PIU3014
PIU3015
PIU3016
PIU3017
PIU3018
PIU3019 PIU3020
PIU3021
PIU3022
PIU3023
PIU3024
PIU3025 PIU3026PIU3027
PIU3028
PIU3029
PIU3030
PIU3031 PIU3032
PIU3033
PIU3034
PIU3035
PIU3036
PIU3037
PIU3038
PIU3039
PIU3040
PIU3041
COU3
PIU401
PIU402
PIU403 PIU404PIU405
PIU406
COU4
PIX201
PIX202
PIX203
PIX204
PIX205
PIX206
COX2
PIC3201
PIC4401 PIC4501
PIJP903
PIL401
PIR3902
PIR4101
PIU3035
NLCLKout10N
PIU3036
NLCLKout10P
PIU3029
NLCLKout20N
PIU3028
NLCLKout20P
PIU3024
NLCLKout30N
PIU3023
NLCLKout30P
PIU3014
NLCLKout40N
PIU3015
NLCLKout40P
PIR3101
PIR3502
PITP1801
PIU305
PIJP602
PIR2401
NLFout1
PIJP702
PIR2501
NLFout2
PIJP802
PIR2601
NLFout3
PIJP1002
PIR2701
NLFout4
PIC2002 PIC2102
PIC2202 PIC2302
PIC2402 PIC2502
PIC2602
PIC2702
PIC2802
PIC2902
PIC3002
PIC3101
PIC3202
PIC3302
PIC3402 PIC3502 PIC3602 PIC3702 PIC3802
PIC4102 PIC4202 PIC4302
PIC4402 PIC4502 PIC4601
PIC4702
PIC4801
PIJP601
PIJP701
PIJP801
PIJP901
PIJP1001
PIJP1101
PIJP1201
PIR3301 PIR3401 PIR3501 PIR3601
PIR4602
PIR4702
PIR5002
PIR5601
PIU3018 PIU3021 PIU3039 PIU3041
PIU402
PIX203
PIR2902
PIR3302
PITP1601
PIU303
PIC2801
PIR3201
PIR3602
PITP1901
PIU306
PIR5501 PIX204
PIR5401 PIX205
PIR5102
PIU404
PIR4901
PIR5101
PIR5301
PIU401
PIR4802
PIR5001
PIU405
PIR4402
PIU3040
PIJP1202
PIX202
PIJP1102
PIR4601
PIC4701
PIR5302
PITP2901
PIX201
PIC3902
PIC4002PIR4701
PIC3801
PIR4001
PITP2301
PIU3011
PIC3701
PIR4301
PITP2401
PIU3012
PIC3601
PIR4501
PITP2501
PIU3013
PIC3501
PIJP1104
PIR3801 PIR3901
PIC3401
PIJP1103
PIR4102 PIR4201
PIC3301
PIC3901
PIC4001
PIR4401
PIR4902
PITP2701
PIU403
PIC3102
PIJP902
PITP2001
PIU307
PIC3001
PIR2702
PIR2802
PITP1201
PIU3017
PIC2901
PIR2602
PITP1301
PIU3022
PIC2701
PIR2502
PITP1401
PIU3030
PIC2601
PIR2402
PITP1501
PIU3037
PIC2401 PIC2501
PIU3025
PIC2201 PIC2301
PIU3026
PIC2001 PIC2101
PIU3027
PIR4302
NLNOALIGN
PIR4002
NLNOLOCK
PIR4502
NLNOREF
PIR2801
NLOSCin
PIR4202
PITP2201
PIU309
PIR3802
PITP2101
PIU308
PIR2901 PIR3001 PIR3102 PIR3202
PIU302 PIU3010 PIU3038 PIU3031 PIU3020 PIU3016 PIU301 PIU3032 PIU3019
PIC4101 PIC4201 PIC4301
PIC4602
PIL402
PIR4801
PIR5201
PITP2801
PIU406
PIX206
PIR3002
PIR3402
PITP1701
PIU304
PIC4802
PIR3702
PIR5202
PIR5402
PIR5602
PIU3033
NLXOin0N
PIR3701
PIR5502
PITP2601
PIU3034
NLXOin0P

1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
1 1Output
11/3/2009
Output.SchDoc
Sheet Title:
Size: Schematic:
Mod. Date:
File:
Rev:
Sheet: of
B
National Semiconductor and/or its licensors do not warrant the accuracy or completeness of
this specification or any information contained therein. National and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit
for any particular purpose, or will operate in an implementation. National and/or its licensors
do not warrant that the design is production worthy. You should completely validate and test
your design implementation to confirm the system functionality for your application.
© Copyright, National Semiconductor, 2009
http://www.national.com
Contact: TechSupport
PRJ_TitleProject:
Designed for: PRJ_Customer
870PRJ_BasePN
PADC: PRJ_PADC
SCH_Rev
Assembly Variant: variantName: No Variant Selected
100 OHM DIFF. IMPEDANCE
C64
0ohm (10nF)
C65
0ohm (10nF)
CLKout4_P
CLKout4_N
100 OHM DIFF. IMPEDANCE
C60
0ohm (10nF)
C61
0ohm (10nF)
CLKout3_P
CLKout3_N
100 OHM DIFF. IMPEDANCE
100 OHM DIFF. IMPEDANCE
C49
0ohm (10nF)
C50
0ohm (10nF)
C54
0ohm (10nF)
C56
0ohm (10nF)
CLKout1_P
CLKout1_N
CLKout2_P
CLKout2_N
LED Indicators for LMH1983 Status Flags
3V3
0.1uF
C51
NOALIGN
Layout Note: Place LEDs nearby
status flag pins.
LED Legend 'ALIGN'
CLKout4_P
CLKout4_N
CLKout3_N
CLKout3_P
CLKout1_P
CLKout1_N
CLKout2_N
CLKout2_P
1
2 3 4 5
J4
CLKout1
D1 LG M670-J2M1-1-0-10-R18-Z
150
R62
3V3
0.1uF
C55
NOREF
Layout Note: Place LEDs nearby
status flag pins.
LED Legend 'REF'
D2 LG M670-J2M1-1-0-10-R18-Z
150
R68
3V3
0.1uF
C59
NOLOCK
Layout Note: Place LEDs nearby
status flag pins.
LED Legend 'LOCK'
D3 LG M670-J2M1-1-0-10-R18-Z
150
R69
ENABLE
6
SDI
2
SD/HD
10
SDI
1
SDO 11
SDO 12
RREF 4
NC 5
NC 7
NC 8
NC 13
NC 14
NC 15
NC 16
VCC
9VEE 3
DAP 17
U5
LMH0302SQ
1
2
JP13
100
R60
Layout note: Place termination resistor, two pin header and
LMH0302 inputs as close together as possible. Place LMH0302
close to the board edge and the SMA connector connected to it's
output. Label SMAs on Silkscreen with CLKout1, CLKout 2 etc..
49.9
R59
49.9
R58
49.9
R57
VDD
0.1uF
C53
1uF
C52
VDD
750
R61
1
2 3 4 5
J5
CLKout2
ENABLE
6
SDI
2
SD/HD
10
SDI
1
SDO 11
SDO 12
RREF 4
NC 5
NC 7
NC 8
NC 13
NC 14
NC 15
NC 16
VCC
9VEE 3
DAP 17
U6
LMH0302SQ
1
2
JP14
100
R66
49.9
R65
49.9
R64
49.9
R63
VDD
0.1uF
C58
1uF
C57
VDD
750
R67
1
2 3 4 5
J6
CLKout3
ENABLE
6
SDI
2
SD/HD
10
SDI
1
SDO 11
SDO 12
RREF 4
NC 5
NC 7
NC 8
NC 13
NC 14
NC 15
NC 16
VCC
9VEE 3
DAP 17
U7
LMH0302SQ
1
2
JP15
100
R73
49.9
R72
49.9
R71
49.9
R70
VDD
0.1uF
C63
1uF
C62
VDD
750
R74
1
2 3 4 5
J7
CLKout4
ENABLE
6
SDI
2
SD/HD
10
SDI
1
SDO 11
SDO 12
RREF 4
NC 5
NC 7
NC 8
NC 13
NC 14
NC 15
NC 16
VCC
9VEE 3
DAP 17
U8
LMH0302SQ
1
2
JP16
100
R78
49.9
R77
49.9
R76
49.9
R75
VDD
0.1uF
C67
1uF
C66
VDD
750
R79
0.1uF
C118
0.1uF
C119
0.1uF
C116
0.1uF
C117
PIC4901 PIC4902
COC49
PIC5001 PIC5002
COC50
PIC5101
PIC5102
COC51
PIC5201
PIC5202
COC52
PIC5301
PIC5302
COC53
PIC5401 PIC5402
COC54
PIC5501
PIC5502
COC55
PIC5601 PIC5602
COC56
PIC5701
PIC5702
COC57
PIC5801
PIC5802
COC58
PIC5901
PIC5902
COC59
PIC6001 PIC6002
COC60
PIC6101 PIC6102
COC61
PIC6201
PIC6202
COC62
PIC6301
PIC6302
COC63
PIC6401 PIC6402
COC64
PIC6501 PIC6502
COC65
PIC6601
PIC6602
COC66
PIC6701
PIC6702
COC67
PIC11601PIC11602
COC116
PIC11701PIC11702
COC117
PIC11801PIC11802
COC118
PIC11901PIC11902
COC119
PID101
PID102
COD1
PID201
PID202
COD2
PID301
PID302
COD3
PIJ401
PIJ402PIJ403PIJ404PIJ405
COJ4
PIJ501
PIJ502PIJ503PIJ504PIJ505
COJ5
PIJ601
PIJ602PIJ603PIJ604PIJ605
COJ6
PIJ701
PIJ702PIJ703PIJ704PIJ705
COJ7
PIJP1301
PIJP1302
COJP13
PIJP1401
PIJP1402
COJP14
PIJP1501
PIJP1502
COJP15
PIJP1601
PIJP1602
COJP16
PIR5701
PIR5702
COR57
PIR5801
PIR5802
COR58
PIR5901
PIR5902
COR59
PIR6001 PIR6002
COR60
PIR6101 PIR6102
COR61
PIR6201 PIR6202
COR62
PIR6301
PIR6302
COR63
PIR6401
PIR6402
COR64
PIR6501
PIR6502
COR65
PIR6601 PIR6602
COR66
PIR6701 PIR6702
COR67
PIR6801 PIR6802
COR68
PIR6901 PIR6902
COR69
PIR7001
PIR7002
COR70
PIR7101
PIR7102
COR71
PIR7201
PIR7202
COR72
PIR7301 PIR7302
COR73
PIR7401 PIR7402
COR74
PIR7501
PIR7502
COR75
PIR7601
PIR7602
COR76
PIR7701
PIR7702
COR77
PIR7801 PIR7802
COR78
PIR7901 PIR7902
COR79
PIU501
PIU502
PIU503
PIU504
PIU505
PIU506
PIU507
PIU508
PIU509
PIU5010 PIU5011
PIU5012
PIU5013
PIU5014
PIU5015
PIU5016
PIU5017
COU5
PIU601
PIU602
PIU603
PIU604
PIU605
PIU606
PIU607
PIU608
PIU609
PIU6010 PIU6011
PIU6012
PIU6013
PIU6014
PIU6015
PIU6016
PIU6017
COU6
PIU701
PIU702
PIU703
PIU704
PIU705
PIU706
PIU707
PIU708
PIU709
PIU7010 PIU7011
PIU7012
PIU7013
PIU7014
PIU7015
PIU7016
PIU7017
COU7
PIU801
PIU802
PIU803
PIU804
PIU805
PIU806
PIU807
PIU808
PIU809
PIU8010 PIU8011
PIU8012
PIU8013
PIU8014
PIU8015
PIU8016
PIU8017
COU8
PIC5101
PIC5501
PIC5901
PID102
PID202
PID302
PIC5001
NLCLKout10N
PIC4901
NLCLKout10P
PIC5401
NLCLKout20N
PIC5601
NLCLKout20P
PIC6001
NLCLKout30N
PIC6101
NLCLKout30P
PIC6501
NLCLKout40N
PIC6401
NLCLKout40P
PIC5102
PIC5202 PIC5302
PIC5502
PIC5702 PIC5802
PIC5902
PIC6202 PIC6302
PIC6602 PIC6702
PIJ402PIJ403PIJ404PIJ405
PIJ502PIJ503PIJ504PIJ505
PIJ602PIJ603PIJ604PIJ605
PIJ702PIJ703PIJ704PIJ705
PIU503
PIU5010
PIU5017
PIU603
PIU6010
PIU6017
PIU703
PIU7010
PIU7017
PIU803
PIU8010
PIU8017
PIU8016
PIU8015
PIU8014
PIU8013
PIU808
PIU807
PIU805
PIU7016
PIU7015
PIU7014
PIU7013
PIU708
PIU707
PIU705
PIU6016
PIU6015
PIU6014
PIU6013
PIU608
PIU607
PIU605
PIU5016
PIU5015
PIU5014
PIU5013
PIU508
PIU507
PIU505
PIR7901 PIU804
PIR7502 PIR7602
PIU8011
PIR7401 PIU704
PIR7002 PIR7102
PIU7011
PIR6701 PIU604
PIR6302 PIR6402
PIU6011
PIR6101 PIU504
PIR5702 PIR5802
PIU5011
PID301
PIR6902
PID201
PIR6802
PID101
PIR6202
PIC11902
PIR6502
PIU6012 PIC11901 PIJ501
PIC11802
PIR5902
PIU5012 PIC11801 PIJ401
PIC11702
PIR7702
PIU8012 PIC11701 PIJ701
PIC11602
PIR7202
PIU7012 PIC11601 PIJ601
PIC6502
PIJP1601
PIR7802
PIU802
PIC6402
PIJP1602
PIR7801
PIU801
PIC6102
PIJP1501
PIR7302
PIU702
PIC6002
PIJP1502
PIR7301
PIU701
PIC5602
PIJP1401
PIR6602
PIU602
PIC5402
PIJP1402
PIR6601
PIU601
PIC5002
PIJP1301
PIR6002
PIU502
PIC4902
PIJP1302
PIR6001
PIU501
PIR6201
PIR6901
PIR6801
PIC5201 PIC5301
PIC5701 PIC5801
PIC6201 PIC6301
PIC6601 PIC6701
PIR5701 PIR5801 PIR5901
PIR6102
PIR6301 PIR6401 PIR6501
PIR6702
PIR7001 PIR7101 PIR7201
PIR7402
PIR7501 PIR7601 PIR7701
PIR7902
PIU506
PIU509
PIU606
PIU609
PIU706
PIU709
PIU806
PIU809

1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Title
Number RevisionSize
B
Date: 11/3/2009 Sheet of
File: C:\Projects\..\LMH1981.SchDoc Drawn By:
J1
Ref. In
VCC
HSYNC_B
VSYNC_A
1
1
2
2
3
3
4
4
88
77
66
55
J2
EXT HVF IN
GND
HSYNC_A
10.0k 1%
R1
BPOUT 13
Video In
4
VFOUT 9
GND
5
VSOUT 8
CSOUT 12
VCC 11
GND
2
VCC
6
VCC
3
Rext
1
HSOUT
7
GND 10
OEOUT 14
U1
LMH1981MT
TP2
VCC
FSYNC_A
VSYNC_B
FSYNC_B
INIT
1
2
JP1
75R TERM
1
2
JP2
LPF ENAB
TP1
VIDEO IN
VC
1OUT 4
GND
3
EN 2
VCC 6
X1
ASVV-27.000MHZ-N152-T
TP3
Vtune
R20
5K
1
2
JP5
XO DISAB
HSYNC_A
HSYNC_B
HIN
VIN
VSYNC_A
FIN
FSYNC_A
HSYNC_B
VSYNC_B
FSYNC_B
Layout Note: JP Legend is
"Short = LMH1981"
"Open = 27M/EXT HVF"
Layout Note: Place U4 on
bottom side of PCB, and
do not label IC.
Layout Note:
Pot Legend is
"VCXO TUNE"
Note:
Short = Enable
Open = Hi-Z
1
2
JP3
INPUT SEL
1
2
JP4
MUX ENAB
Layout Note:
XO Legend is
"27 MHz VCXO Source"
Layout Note: IC Legend is
"LMH1981 Sync Separator"
OSCin
3V3
3V3
3V3
OPEN
R18
Analog Input and LMH1981 Sync Separator
External HVF+INIT Input Header
27 MHz Clock Source from VCXO or SMA Input
Quad SPDT Input MUX with Output Hi-Z
Layout Note: Pin Legend is
"EXT INIT" (inline w/ pin 8)
"EXT F " (inline w/ pin 7)
"EXT V" (inline w/ pin 6)
"EXT H" (inline w/ pin 5)
"GND" (inline w/ pins 1-4)
75.0
R4
33
R2
33
R5
33
R6
33
R10
33
R13
OPEN
R15
33
R8
33
R19
OPEN
R21
0.1uF
C2
0.1uF
C8
0.1uF
C3
0.1uF
C14
0.1uF
C10
560pF
C9
C0G/NP0: 0.1uF
C18
10uF
C6
10uF
C13
10uF
C17
10.0k
R7
10.0k
R9
IN
1
NC1
2
NO1
3
COM1
4
NC2
5
NO2
6
COM2
7
GND
8
V+ 16
EN 15
NC4 14
NO4 13
COM4 12
NC3 11
NO3 10
COM3 9
U2
TS3A5018PW
250mA
220 ohm
L1
250mA
220 ohm
L2
250mA
220 ohm
L3
FIN
VIN
HIN
OPEN
R23
OPEN
R22
3V3
0.1uF
C19
Note: 27 MHz Clock Source can come from
either the on-board VCXO or the SMA Input.
If the SMA Input is used, the VCXO output
should be disabled. The SMA input signal
can be AC or DC coupled, and terminated
and.or biased as needed using the available
resistor options.
Layout Note: Minimize
stub length of the traces
on 27M net.
OPEN
R12
OPEN
R11
OPEN
R14
Layout Note: Minimize stub
length of HSYNC_B
INIT
27M
OPEN
R16
OPEN
R17
Note: If U4 is not populated,
shorts can be installed to
directly connect the HVF
signals to the LMH1983 inputs.
3V3
50-OHM CONTROLLED IMPEDANCE
1uF
C15
1uF
C16
1uF
C12
1uF
C11
1uF
C4
1uF
C5
0
R3
VCC
VCC
Layout Note: Unless otherwise noted, label all
ICs, Test Points, Jumpers and Headers per the
component comment. For jumpers and headers,
label pins according to the pin legend noted. All
labels should be present on top and bottom silk
screen (except for ICs).
TP4
GND
Layout Note: Distribute GND test
points around the PCB.
TP5
GND
TP6
GND
TP7
GND
TP8
GND
TP9
GND
TP10
GND
TP11
GND
1
2 4
3
SW1
FSM2JSMA
1uF
C1
OPEN
C7
1
2 3 4 5
J3
27MHz SMA In
LMH1983 Eval Board - LMH1981
B
Sauerwald
4 5
PIC101PIC102
COC1
PIC201PIC202
COC2
PIC301
PIC302
COC3
PIC401
PIC402
COC4
PIC501
PIC502
COC5
PIC601
PIC602
COC6
PIC701PIC702
COC7
PIC801PIC802
COC8
PIC901
PIC902
COC9
PIC1001
PIC1002
COC10
PIC1101
PIC1102
COC11
PIC1201
PIC1202
COC12
PIC1301
PIC1302
COC13
PIC1401
PIC1402
COC14
PIC1501
PIC1502
COC15
PIC1601
PIC1602
COC16
PIC1701
PIC1702
COC17
PIC1801
PIC1802
COC18
PIC1901PIC1902
COC19
PIJ101
PIJ102PIJ103
COJ1
PIJ201
PIJ202
PIJ203
PIJ204 PIJ205
PIJ206
PIJ207
PIJ208
COJ2
PIJ301
PIJ302 PIJ303 PIJ304 PIJ305
COJ3
PIJP101
PIJP102
COJP1
PIJP201
PIJP202
COJP2
PIJP301
PIJP302
COJP3
PIJP401
PIJP402
COJP4
PIJP501
PIJP502
COJP5
PIL101PIL102
COL1
PIL201PIL202
COL2
PIL301PIL302
COL3
PIR101PIR102
COR1
PIR201PIR202
COR2
PIR301 PIR302
COR3
PIR401
PIR402
COR4
PIR501PIR502
COR5
PIR601PIR602
COR6
PIR701 PIR702
COR7
PIR801PIR802
COR8
PIR901
PIR902
COR9
PIR1001PIR1002
COR10
PIR1101PIR1102
COR11
PIR1201
PIR1202
COR12
PIR1301PIR1302
COR13
PIR1401PIR1402
COR14
PIR1501PIR1502
COR15
PIR1601
PIR1602
COR16
PIR1701
PIR1702
COR17
PIR1801PIR1802
COR18
PIR1901PIR1902
COR19
PIR2001
PIR2002
PIR2003
COR20
PIR2101PIR2102
COR21
PIR2201
PIR2202
COR22
PIR2301
PIR2302
COR23
PISW101
PISW102
PISW103
PISW104
COSW1
PITP101
COTP1
PITP201
COTP2
PITP301
COTP3
PITP401
COTP4
PITP501
COTP5
PITP601
COTP6
PITP701
COTP7
PITP801
COTP8
PITP901
COTP9
PITP1001
COTP10
PITP1101
COTP11
PIU101
PIU102
PIU103
PIU104
PIU105
PIU106
PIU107 PIU108
PIU109
PIU1010
PIU1011
PIU1012
PIU1013
PIU1014
COU1
PIU201
PIU202
PIU203
PIU204
PIU205
PIU206
PIU207
PIU208 PIU209
PIU2010
PIU2011
PIU2012
PIU2013
PIU2014
PIU2015
PIU2016
COU2
PIX101
PIX102
PIX103
PIX104
PIX106
COX1
PIC501 PIC601
PIC1201 PIC1301
PIC1601 PIC1701
PIL101
PIL201
PIL301
PIR2201
PISW103
PISW104
PIC1901
PIR1902
PIR2102
PIR2202
PIR2301
PIX104
NL27M
PIR1701
PIU209
NLFIN
PIR201
PIR1702
PIU2011
NLFSYNC0A
PIR1001
PIU2010
NLFSYNC0B
PIC202
PIC302 PIC402 PIC502 PIC602
PIC802
PIC902
PIC1002 PIC1102 PIC1202 PIC1302
PIC1402 PIC1502 PIC1602 PIC1702
PIC1801
PIJ102PIJ103
PIJ201
PIJ202
PIJ203
PIJ204
PIJ302 PIJ303 PIJ304 PIJ305
PIJP301
PIJP401
PIJP501
PIR102
PIR402
PIR1101
PIR1401
PIR2003
PIR2302
PITP401 PITP501 PITP601 PITP701 PITP801 PITP901 PITP1001 PITP1101
PIU102
PIU105 PIU1010
PIU208
PIX103
PIR1201
PIU204
NLHIN
PIR601
PIR1202
PIU202
NLHSYNC0A
PIR1501
PIR1901
PIU203
NLHSYNC0B
PIR801
PISW101
PISW102
NLINIT
PIU1013
PIU1012
PIU109
PIR1402 PIU2012
PIR1102
PIU2013
PIU2014
PIR602
PIU107 PIR502 PIU108
PIR202 PIU1014 PIR101 PIU101
PIJP502
PIR1802
PIX102
PIJP402
PIR902
PIU2015
PIJP302 PIR702
PIU201
PIJP101
PIR401
PIJ208 PIR802
PIJ207 PIR1002
PIJ206 PIR1302
PIJ205 PIR1502
PIJ101
PIJP102
PIR302
PIC1902 PIJ301
PIC1802
PIR2002
PITP301
PIX101
PIC1401 PIC1501
PIL302
PIR1801
PIR2001
PIX106
PIC1001 PIC1101
PIL202PIR701
PIR901
PIU2016
PIC901
PIJP201
PIC102
PIC702 PIJP202
PIR301
PITP101
PIC101
PIC701
PIU104
PIR2101
NLOSCin
PIC201
PIC301 PIC401
PIC801
PIL102
PITP201
PIU103
PIU106
PIU1011
PIR1601
PIU207
NLVIN
PIR501
PIR1602
PIU205
NLVSYNC0A
PIR1301
PIU206
NLVSYNC0B

1
1
2
2
3
3
4
4
D D
C C
B B
A A
Title
Number RevisionSize
A
Date: 11/3/2009 Sheet of
File: C:\Projects\..\POWER SUPPLY.SchDoc Drawn By:
3V35V
IN
4
ADJ 6
GND 3
NC
7
SD
8
DAP
9
OUT 5
BYP 1 NC
2
U9
LP3878MR-ADJ
1800pF
C73
C0G/NP0: 0.01uF
C74
D5
LG M670-J2M1-1-0-10-R18-Z
Layout Note: LED
Legend is "5V IN"
D6
LG M670-J2M1-1-0-10-R18-Z
150
R82
Layout Note: LED
Legend is "3.3V"
1
1
2
2
3
3
4
4
88
77
66
55
J8
POWER
3V3
LDO_3V3
LDO_3V3
Layout Note: Pin Legend is
"5V IN" (pin 8)
"N/C" (pin 7)
"LDO 3.3V" (pin 6)
"3.3V" (pin 5)
"GND" (pins 1-4)
10uF
C69
10uF
C70
0
R80
1uF
C71
1uF
C72
0.34V
D4
5V
TP30
3V3
1 2
JP17
LDO ENAB
10K
R84
10uF
C68
16V
Power Supply Input and Low-Noise 3.3V LDO Regulator
Layout Note: Unless otherwise noted, label all
ICs, Test Points, Jumpers and Headers per the
component comment. For jumpers and headers,
label pins according to the pin legend noted. All
labels should be present on top and bottom silk
screen (except for ICs).
Note: LDO output voltage
Vout 1V*(1+R_hi/R_lo) = 3.30V
Note: Remove 0R resistor when
applying an external 3.3V power
supply to the 3V3 input.
0.1uF
C106
0.1uF
C108
1uF
C107
1uF
C105
VDD
Layout Note: Distribute caps around the 4 sides of
LMH1983 for decoupling the VDD power supply
plane.
VDD
3V3
10uF
C90
10uF
C91
10uF
C95
10uF
C96
10uF
C97
10uF
C98
TP31
VDD
1uF
C92
1 2
JP18
IDD(U1)
0.01uF
C83
250mA
220 ohm
L6
1uF
C77
1uF
C80
VDD
0.01uF
C86
250mA
220 ohm
L8
1uF
C84
1uF
C85
VDD
0.01uF
C101
250mA
220 ohm
L10
1uF
C99
1uF
C100
VDD
VDD
0.01uF
C79
1uF
C78
250mA
220 ohm
L7
1uF
C75
0.01uF
C89
VDD
1uF
C88
250mA
220 ohm
L9
1uF
C87
VDD
0.01uF
C104
1uF
C103
250mA
220 ohm
L11
1uF
C102
1uF
C81
VDD
0.01uF
C82
250mA
220 ohm
L5
1uF
C76
VDD_PLL1
VDD_PLL2
VDD_PLL34
VDD_CLK4 VDD_CLK3
VDD_CLK2
VDD_CLK1
1uF
C93
10uF
C94
Pin 2 Pin 10
348
R81
1.10k
R83
475
R85
LMH1983 Eval Board - Power
B
Sauerwald
55
PIC6801
PIC6802
COC68
PIC6901
PIC6902
COC69
PIC7001
PIC7002
COC70
PIC7101
PIC7102
COC71
PIC7201
PIC7202
COC72
PIC7301
PIC7302
COC73
PIC7401
PIC7402
COC74
PIC7501
PIC7502
COC75
PIC7601
PIC7602
COC76
PIC7701
PIC7702
COC77
PIC7801
PIC7802
COC78
PIC7901
PIC7902
COC79
PIC8001
PIC8002
COC80
PIC8101
PIC8102
COC81
PIC8201
PIC8202
COC82
PIC8301
PIC8302
COC83
PIC8401
PIC8402
COC84
PIC8501
PIC8502
COC85
PIC8601
PIC8602
COC86
PIC8701
PIC8702
COC87
PIC8801
PIC8802
COC88
PIC8901
PIC8902
COC89
PIC9001
PIC9002
COC90
PIC9101
PIC9102
COC91
PIC9201
PIC9202
COC92
PIC9301
PIC9302
COC93
PIC9401
PIC9402
COC94
PIC9501
PIC9502
COC95
PIC9601
PIC9602
COC96
PIC9701
PIC9702
COC97
PIC9801
PIC9802
COC98
PIC9901
PIC9902
COC99
PIC10001
PIC10002
COC100
PIC10101
PIC10102
COC101
PIC10201
PIC10202
COC102
PIC10301
PIC10302
COC103
PIC10401
PIC10402
COC104
PIC10501
PIC10502
COC105
PIC10601
PIC10602
COC106
PIC10701
PIC10702
COC107
PIC10801
PIC10802
COC108
PID401PID402
COD4
PID501
PID502
COD5
PID601
PID602
COD6
PIJ801
PIJ802
PIJ803
PIJ804 PIJ805
PIJ806
PIJ807
PIJ808
COJ8
PIJP1701 PIJP1702
COJP17
PIJP1801 PIJP1802
COJP18
PIL501PIL502
COL5
PIL601 PIL602
COL6
PIL701 PIL702
COL7
PIL801 PIL802
COL8
PIL901PIL902
COL9
PIL1001 PIL1002
COL10
PIL1101 PIL1102
COL11
PIR8001PIR8002 COR80
PIR8101
PIR8102
COR81
PIR8201
PIR8202
COR82
PIR8301
PIR8302
COR83
PIR8401
PIR8402
COR84
PIR8501
PIR8502
COR85
PITP3001
COTP30
PITP3101
COTP31
PIU901 PIU902
PIU903
PIU904 PIU905
PIU906
PIU907
PIU908
PIU909
COU9
PIC7001 PIC7101 PIC7201
PIC9001 PIC9101 PIC9201
PIJ805
PIJP1802
PIR8001
PIR8201
PITP3001
PIC6801
PID402
PIJ808
PIJP1701
PIR8101
PIU904
PIC6802 PIC6902 PIC7002 PIC7102 PIC7202
PIC7402
PIC7502PIC7602 PIC7702 PIC7802 PIC7902PIC8002
PIC8102 PIC8202 PIC8302
PIC8402 PIC8502 PIC8601 PIC8702 PIC8802 PIC8902
PIC9002 PIC9102 PIC9202 PIC9302 PIC9402 PIC9502 PIC9602 PIC9702 PIC9802
PIC9902 PIC10002 PIC10102
PIC10202 PIC10302 PIC10402
PIC10502 PIC10602 PIC10702 PIC10802
PID501 PID601
PIJ801
PIJ802
PIJ803
PIJ804
PIR8402
PIR8502
PIU903 PIU909
PIC6901
PIC7301
PID401
PIJ806
PIR8002
PIR8301
PIU905
PIU907
PIU902
PIJP1702
PIR8401
PIU908
PIJ807
PID602
PIR8202
PID502
PIR8102
PIC7401
PIU901
PIC7302
PIR8302
PIR8501
PIU906
PIC7501PIC7601 PIC8001
PIC8401 PIC8701
PIC9301 PIC9401 PIC9501 PIC9601 PIC9701 PIC9801
PIC10001
PIC10201
PIC10501 PIC10601 PIC10701 PIC10801
PIJP1801
PIL502 PIL601 PIL701
PIL802 PIL902
PIL1001 PIL1102
PITP3101
PIC9901
PIC10101
PIL1002
PIC8501 PIC8602
PIL801
PIC7701
PIC8301
PIL602
PIC8101 PIC8201
PIL501
PIC7801 PIC7901
PIL702
PIC8801 PIC8901
PIL901
PIC10301 PIC10401
PIL1101

1
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2
2
3
3
4
4
D D
C C
B B
A A
Title
Number RevisionSize
A
Date: 11/3/2009 Sheet of
File: C:\Projects\..\USB Interface.SchDoc Drawn By:
PE6 (INT.6/AIN.0)
1
PE7 (INT.7/AIN.1/UVcon)
2
UVcc
3
D-
4
D+
5
UGnd
6
UCap
7
VBus
8
PE3 (IUID)
9
PB0 (SS)
10
PB1 (SCK)
11
PB2 (MOSI)
12
PB3 (MISO)
13
PB4 (OC0)
14
PB5 (OC1A)
15
PB6 (OC1B)
16
PB7 (OC2/OC1C)
17
PE4
18
PE5
19
RESET
20
VCC 21
GND 22
XTAL2
23
XTAL1
24
PD0 (SCL/INT0)
25
PD1 (SDA/INT1)
26
PD2 (RXD1/INT2)
27
PD3 (TXD1/INT3)
28
PD4 (IC1)
29
PD5 (XCK1)
30
PD6 (T1)
31
PD7 (T0)
32
PE0 (WR)
33
PE1 (RD)
34
PC0 (A8) 35
PC1 (A9) 36
PC2 (A10 37
PC3 (A11) 38
PC4 (A12) 39
PC5 (A13) 40
PC6 (A14) 41
PC7 (A15) 42
PE2 (ALE / HWB)
43
PA7 (AD7) 44
PA6 (AD6) 45
PA5 (AD5) 46
PA4 (AD4) 47
PA3 (AD3) 48
PA2 (AD2) 49
PA1 (AD1) 50
PA0 (AD0) 51
VCC 52
GND 53
PF7 (ADC7/TDI) 54
PF6 (ADC6/TDO) 55
PF5 (ADC5/TMS) 56
PF4 (ADC4/TCK) 57
PF3 (ADC3) 58
PF2 (ADC2) 59
PF1 (ADC1) 60
PF0 (ADC0) 61
AREF 62
GND 63
AVCC 64
U10
AT90USB128/64
VBUS 1
D- 2
D+ 3
GND 4
J9
1-1470156-2
12
F2594CT-ND
D7
12
D8
GND
535-9103-1-ND
Y1
16 MHz XTAL Osc.
15pF
C114
15pF
C115
GND
SDA
SCL
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
P1
Header 8X2
GND
VDD
GND
0.1uF
C110
1uF
C111
0.1uF
C112
1
2 4
3
SW3
RESET Interface
GND
47k
R87
0.22uF
C113
1
2 4
3
SW2
HWB
47k
R86
0.22uF
C109
VDD
VDD
LMH1983 Eval Board - USB Interface
B
Sauerwald
45
1
2
3
4
5
6
P2
Header 6
GND
VDD
PIC10901 PIC10902
COC109
PIC11001
PIC11002
COC110
PIC11101
PIC11102
COC111
PIC11201
PIC11202
COC112
PIC11301 PIC11302
COC113
PIC11401
PIC11402
COC114
PIC11501
PIC11502
COC115
PID701
PID702
COD7
PID801
PID802
COD8
PIJ901
PIJ902
PIJ903
PIJ904
PIJ905
PIJ906
COJ9
PIP101 PIP102
PIP103 PIP104
PIP105 PIP106
PIP107 PIP108
PIP109 PIP1010
PIP1011 PIP1012
PIP1013 PIP1014
PIP1015 PIP1016
COP1
PIP201
PIP202
PIP203
PIP204
PIP205
PIP206
COP2
PIR8601
PIR8602
COR86
PIR8701
PIR8702
COR87
PISW201
PISW202
PISW203
PISW204
COSW2
PISW301
PISW302
PISW303
PISW304
COSW3
PIU1001
PIU1002
PIU1003
PIU1004
PIU1005
PIU1006
PIU1007
PIU1008
PIU1009
PIU10010
PIU10011
PIU10012
PIU10013
PIU10014
PIU10015
PIU10016
PIU10017
PIU10018
PIU10019
PIU10020
PIU10021
PIU10022
PIU10023
PIU10024
PIU10025
PIU10026
PIU10027
PIU10028
PIU10029
PIU10030
PIU10031
PIU10032
PIU10033
PIU10034
PIU10035
PIU10036
PIU10037
PIU10038
PIU10039
PIU10040
PIU10041
PIU10042
PIU10043
PIU10044
PIU10045
PIU10046
PIU10047
PIU10048
PIU10049
PIU10050
PIU10051
PIU10052
PIU10053
PIU10054
PIU10055
PIU10056
PIU10057
PIU10058
PIU10059
PIU10060
PIU10061
PIU10062
PIU10063
PIU10064
COU10
PIY101PIY102
COY1
PIC10902
PIC11002 PIC11102
PIC11202
PIC11302
PIC11402 PIC11502
PID702 PID802
PIJ905
PIJ906
PIP102
PIP104
PIP106
PIP108
PIP1010
PIP1012
PIP1014
PIP1016
PIP201
PISW201
PISW202
PISW301
PISW302
PIU10022
PIU10053
PIU10063
PIU10061
PIU10060
PIU10059
PIU10058
PIU10057
PIU10056
PIU10055
PIU10054
PIU10042
PIU10041
PIU10040
PIU10039
PIU10038
PIU10037
PIU10036
PIU10035
PIU10034
PIU10033
PIU10028
PIU10027
PIU10019
PIU10018
PIU10017
PIU10016
PIU10015
PIU10014
PIU10013
PIU10012
PIU10011
PIU10010
PIU1009
PIU1008
PIU1007
PIU1002
PIU1001
PIP205
PIU10029
PIP204
PIU10030
PIP203
PIU10031
PIP202
PIU10032
PIP1015 PIU10044
PIP1013 PIU10045
PIP1011 PIU10046
PIP109 PIU10047
PIP107 PIU10048
PIP105 PIU10049
PIP103 PIU10050
PIP101 PIU10051
PIJ904 PIU1006
PIJ901 PIU1003
PID801
PIJ902 PIU1004
PID701
PIJ903 PIU1005
PIC11501
PIU10023 PIY101
PIC11401
PIU10024
PIY102
PIC11301
PIR8701
PISW303
PISW304
PIU10020
PIC11201
PIU10062
PIC10901
PIR8601
PISW203
PISW204
PIU10043
PIU10025
PIU10026
PIC11001 PIC11101
PIP206
PIR8602
PIR8702
PIU10021
PIU10052
PIU10064