National Semiconductor DS25CP104 User manual

February 2008
Rev. 0.2
3.125 Gbps 4x4 LVDS Crosspoint Switch
with Transmit Pre-emphasis
and Receive Equalization
DS25CP104 Evaluation Kit
USER MANUAL
Part Number: DS25CP104EVK
For the latest documents concerning these products and evaluation kit, visit lvds.national.com.
Schematics and gerber files are also available at lvds.national.com.

DS25CP104EVK User Manual
Table of Contents
Table of Contents…..........................................................................................................2
Overview………………………………………………………………………………...3
DS25CP104 EVK Description …………………………………………………………4
CP104 Evaluation ………………………………………………………………………6
SMBus Evaluation ……………………………………………………………………..12
Typical Performance …………………………………………………………………...16
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DS25CP104EVK User Manual
Overview
The DS25CP104EVK is an evaluation kit designed for demonstrating performance of
DS25CP104, a 3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit Pre-emphasis
and Receive Equalization. The evaluation kit is comprised of the DS25CP104 with its
associated input and output SMA connectors and jumpers to manually select the desired
pre-emphasis or equalization, a USB to SMBus conversion circuit to control the SMBus
with a PC, and three FR4 striplines (15” (38.1cm), 30” (76.2cm), and 60” (152.4cm) ) to
exercise the devices’ signal conditioning features (pre-emphasis and equalization).
The purpose of this document is to familiarize the user with the DS25CP104EVK, to
suggest test setup procedures and instrumentation to test the device optimally, and to
guide the user through some typical measurements that demonstrate the performance of
the DS25CP104 in typical applications.
Figure 1. Photo of the DS25CP104EVK
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DS25CP104EVK User Manual
DS25CP104EVK Description
Figure 2 shows the top layer drawing of the PCB with the silkscreen annotations. The 4.5
by 4.5 inch, eight-layer PCB is designed to evaluate the functions of the DS25CP104.
Figure 2. Top Layer DS25CP104EVK
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DS25CP104EVK User Manual
For descriptive purposes the DS25CP104EVK can be broken into three parts:
1. The DS25CP104 IC with associated connectors and jumpers is the main part of the
board. The block diagram of the DS25CP104 is shown in Figure 3. The receive buffers
can be set to Off and Low equalization by the external pins EQ0 – EQ3; the transmit
buffers can be set to Off and Med. levels of pre-emphasis by the external pins PE0 – PE3.
Since data capabilities are 3.125 Gbps, SMA connectors are used to ensure minimal loss.
More information can be found about the DS25CP104 on the data sheets.
2. A USB to SMBus converter has been added to the evaluation kit to implement
SMBus switch configuration to control the signal conditioning. Through the SMBus the
DS25CP104 currently features four levels (Off, Low, Medium, and High) of pre-
emphasis and two levels (Off, Low) of equalization.
3. Three channels of stripline have been added to the evaluation kit to test the pre-
emphasis and equalization functions (15” (38.1cm), 30” (76.2cm), and 60” (152.4cm) ).
In practical applications, devices often drive long backplanes or cables. To help reduce
jitter caused from long backplanes or cables, pre-emphasis can be used for the drivers and
equalization for the receivers.
SDA
SCL
EN_smb
ADDRn
Figure 3. DS25CP104 Block Diagram
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DS25CP104EVK User Manual
DS25CP104 Evaluation
The DS25CP104 is a 3.125 Gbps LVDS Crosspoint Switch with four levels of transmit
pre-emphasis and two levels of receive equalization configured in the SMBus Mode and
two levels of transmit pre-emphasis and two levels of receive equalization configured via
external jumpers on the evaluation board in the Pin Mode.
Initial Pin Settings for Pin Mode Testing
Pin Setting Note
SMBus Enable L Disable SMbus
EQ0 – EQ 3 L Equalization off,
See table
PE0 – PE3 L Pre-Emphasis off,
See table
PWDN H Power Down off
Switch Configuration Truth Tables
S01 S00 Input Selected
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
Table 1. Input Select Pins Configuration for the Output OUT0
S11 S10 Input Selected
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
Table 2. Input Select Pins Configuration for the Output OUT1
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DS25CP104EVK User Manual
S21 S20 Input Selected
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
Table 3. Input Select Pins Configuration for the Output OUT2
S31 S30 Input Selected
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
Table 4. Input Select Pins Configuration for the Output OUT3
Signal Conditioning Tables
Output OUTn, n={0,1,2,3}
Pre-Emphasis Control Pin (PEn) State Pre-Emphasis Level
0 Off
1 Medium
Table 5. Transmit Pre-emphasis Truth Table
Input INn, n={0,1,2,3}
Equalization Control Pin (EQn) State Equalization Level
0 Off
1 Low
Table 6. Receive Equalization Truth Table
Stripline Length Table (also known as Test Channels)
Stripline Length Loss (dB) @ 1250 MHz
L1 15” (38.1cm) -3.6
L2 30” (76.2cm) -8.2
L3 60” (152.4cm) -14.5
Table 7. Stripline length table
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DS25CP104EVK User Manual
Jitter Performance Testing with No Signal Conditioning
1. Configure the test setup as shown in Figure 4.
2. Set the desired INn to OUTn drivers by selecting S00, S01, S10, S11, S20, S21,
S30, S31 according to Tables 1 – 4.
3. Select the PEn and EQn jumpers to 0, according to tables 5 and 6.
4. Apply + supply (3.3V typical) to the VDD and – supply (ground) to the VSS
connectors.
5. Connect a signal source (signal generator, data source, or an LVDS driver) to the
desired INn inputs on the board and adjust the signal parameters (VOH, VOL,
VCM) so that they comply with the device input recommendations.
6. Connect an oscilloscope to the selected OUTn outputs and view the output signals
with an oscilloscope with the bandwidth of at least 5 GHz.
Figure 4. Jitter Performance Test Circuit
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DS25CP104EVK User Manual
Pre-Emphasis Performance Testing
In applications where data transmits over cables or long backplanes, the pre-emphasis
feature on the DS25CP104 transmitter helps to overcome media loss and reduce bit
errors; hence the DS25CP104EVK has three lengths of stripline to test the pre-emphasis
function.
1. Configure the test setup as shown in figure 5; select the desired test channel
lengths in Table 7.
2. Set the desired INn to OUTn drivers by selecting S00, S01, S10, S11, S20, S21
according to Tables 1 – 4.
3. Select the PEn jumpers to 1 and the EQn jumpers to 0, according to Tables 5 and
6.
4. Apply + supply (3.3V typical) to the VDD and – supply (ground) to the VSS
connectors.
5. Connect a signal source (signal generator, data source, or an LVDS driver) to the
desired INn inputs on the board and adjust the signal parameters (VOH, VOL,
VCM) so that they comply with the device input recommendations.
6. Connect an oscilloscope to the selected OUTn outputs and view the output signals
with an oscilloscope with a bandwidth of at least 5 GHz.
Figure 5. Pre-Emphasis Performance Test Circuit
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DS25CP104EVK User Manual
Equalization Performance Testing
In some applications, data transmits over cables or long backplanes. The equalization
function on the DS25CP104 receivers helps to compensate for loss of certain media;
hence the DS25CP104EVK has three lengths of stripline to test the equalization function.
1. Configure the test setup as shown in Figure 6; select the desired test channel,
lengths in Table 7.
2. Set the desired INn to OUTn drivers by selecting S00, S01, S10, S11, S20, S21,
S30, S31 according to Tables 1 – 4.
3. Select the PEn jumpers to 0 and the EQn jumpers to 1, according to Tables 5 and
6.
4. Apply + supply (3.3V typical) to the VDD and – supply (ground) to the VSS
connectors.
5. Connect a signal source (signal generator, data source, or an LVDS driver) to the
desired INn inputs on the board and adjust the signal parameters (VOH, VOL,
VCM) so that they comply with the device input recommendations.
6. Connect an oscilloscope to the selected OUTn outputs and view the output
signals with an oscilloscope with a bandwidth of at least 5 GHz.
Figure 6. Equalization Performance Test Circuit
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