National Semiconductor LMX2531LQ2820E User manual

LMX2531LQ2820E
Evaluation Board Operating Instructions
National Semiconductor Corporation
Timing Devices Business Group
10333 North Meridian
Suite 400
Indianapolis, IN 46290
LMX25312820EVAL Instructions Rev 6.24.2009

LMX2531LQ2820E EVALUATION BOARD OPERATING INSTRUCTIONS
Table of Contents
Table of Contents................................................................................................................ 2
Loop Filter .......................................................................................................................... 3
Quick Setup......................................................................................................................... 3
Troubleshooting.................................................................................................................. 4
SOFTWARE DOES NOT COMMUNICATE WITH THE EVALUATION BOARDS....................................................... 4
PART RESPONDS TO PROGRAMMING,BUT DOES NOT LOCK TO THE CORRECT FREQUENCY............................ 4
CLOSE-IN PHASE NOISE IS WORSE THAN EVALUATION BOARD INSTRUCTIONS SHOW .................................... 4
FAR-OUT PHASE NOISE IS WORSE THAN EVALUATION BOARD INSTRUCTIONS SHOW .................................... 5
Device Data......................................................................................................................... 5
PHASE NOISE ............................................................................................................................................... 6
FREE-RUNNING VCO PHASE NOISE (INTERNAL DIVIDE BY 2DISABLED).................................................... 7
FREE-RUNNING VCO PHASE NOISE (INTERNAL DIVIDE BY 2ENABLED)..................................................... 8
FRACTIONAL SPURS (INTERNAL DIVIDE BY 2DISABLED)............................................................................ 9
FRACTIONAL SPURS (INTERNAL DIVIDE BY 2ENABLED)........................................................................... 10
INTEGER SPURS (INTERNAL DIVIDE BY 2DISABLED)................................................................................. 11
INTEGER SPURS (INTERNAL DIVIDE BY 2ENABLED).................................................................................. 12
IN-BAND FACTIONAL SPURS INTEGER SPURS (INTERNAL DIVIDE BY 2DISABLED).................................... 13
IN-BAND FACTIONAL SPURS INTEGER SPURS (INTERNAL DIVIDE BY 2ENABLED)..................................... 14
Inter-modulation Spurs ............................................................................................. 15
CodeLoader Settings......................................................................................................... 16
SELECT DEVICE.......................................................................................................................................... 16
BITS/PINS................................................................................................................................................... 18
PLL/VCO.................................................................................................................................................. 19
REGISTERS ................................................................................................................................................. 20
PORT SETUP ............................................................................................................................................... 21
Schematic.......................................................................................................................... 22
Bill of Materials................................................................................................................ 23
Top Layer.......................................................................................................................... 24
Mid Layer 1 "Ground Plane"............................................................................................ 25
Mid Layer 2 "Power"........................................................................................................ 26
Bottom Layer "Signal"...................................................................................................... 27
Top Build Diagram........................................................................................................... 28
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LMX2531LQ2820E EVALUATION BOARD OPERATING INSTRUCTIONS
Loop Filter
Loop Bandwidth 14 kHz Kφ1440 uA (16X)
Phase Margin 54.1 ° FPD 10 MHz
Crystal Frequency 10 MHz Output Frequency 2710 to 2925 MHz (DIV2=0)
1355 to 1462 MHz (DIV2=1)
Supply Voltage 3.0 Volts VCO Gain 12 to 28 MHz/Volt
VCO
CPout
open
100 nF
1KΩ
100 pF 100 pF
20 KΩ20 KΩ
Vtune
Quick Setup
•Install the CodeLoader software which is available at www.national.com/timing/software/.
•Attach the parallel cable or USB <--> uWire cable to the computer and the evaluation board.
•Connect 3.0 volts to the Vcc connector.
•Connect the Fout connector to a spectrum analyzer or phase noise analyzer.
•Connect a clean 10 MHz source to the OSCin pin. Typically, the 10 MHz output from the back
of the RF test equipment is a good source. Signal generators tend to be very noisy and should
be used with caution. If a signal generator is used, the signal generator phase noise
contribution can be reduced by setting the signal to 80 MHz and dividing this down to a phase
detector frequency of 10 MHz.
•Set up the CodeLoader software.
oSelect the proper part from the menu as Select Part->PLL+VCO->LMX2531LQ2820E
oSelect the proper mode from the Mode menu.
oLoad the part by pressing Ctrl+L or selecting Keyboard Controls->Load Device from
the menu.
•It is recommended to ensure proper communication with the device.
oClick the REG_RST bit on the bits/pins page and observe the current go to 0 mA.
oUnclick the REG_RST bit AND press Ctrl+L. The current should be approximately
35 mA.
oIf device does not respond to this, consult the troubleshooting section.
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LMX2531LQ2820E EVALUATION BOARD OPERATING INSTRUCTIONS
Troubleshooting
Software does not communicate with the evaluation boards
LPT or USB Mode
•Ensure a valid signal is presented to the OSCin connector. If a signal generator is used,
ensure the RF is ON.
•Consult the CodeLoader instructions for more detailed information on communication issues.
LPT Mode (Uses Parallel Port Cable)
•Ensure that CodeLoader is selected to LPT mode on the Port Setup tab
•Ensure the proper port number is selected (LPT1, LPT2, LPT3). CodeLoader does NOT
automatically detect this.
•Ensure the LPT cable is securely connected to the computer and board.
•Exit and Restart CodeLoader.
•Ensure the parallel port is in the correct mode.
oWindows often requires Administrative access to write to the parallel port.
oEnsure that the parallel port is set to “Enabled” in windows device manager.
oA reboot upon installation of CodeLoader is sometimes necessary to get the parallel
port to work.
oStandard mode is the most reliable. This can be set in the BIOS mode of the
computer as “Normal”, “Output Only”, or “AT.”
USB Mode (Uses USB <--> uWire Interface Board, NSID = USB2UWIRE)
•On the menu, select LPT/USB->Version to verify communication with the board.
•Ensure the Green LEDs are lit on the USB board.
•Ensure there are no conflicts with other USB devices and reinstall the board.
Part responds to programming, but does not lock to the correct
frequency
•Ensure that there is a valid signal presented to the OSCin connector. If a signal generator is
used, ensure that the RF is set to ON.
•If using the lower frequency band (DIV2=1), the VCO frequency in CodeLoader should be
twice the frequency at the Fout pin.
•Ensure that the VCO FREQUENCY CAL bits on the Bits/Pins tab are correct.
•Ensure that the loop filter is optimized if the charge pump current, phase detector frequency, or
loop filter values have been changed from their original settings. Ensure that the integrated
loop filter components on CodeLoader are set to their proper settings.
Close-in phase noise is worse than evaluation board instructions
show
•Ensure the signal presented to OSCin connector is clean. Try another source, or if it is a
signal generator, try using a higher frequency and dividing it down to the phase detector
frequency.
•Ensure the OSCin signal after the connecting cable provides sufficient power level.
•If the phase detector frequency or charge pump current are lowered from their original settings,
the in-band phase noise can be degraded, even if the loop filter is re-designed for the same
loop bandwidth.
•If the loop bandwidth is decreased, in-band phase noise can be degraded.
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LMX2531LQ2820E EVALUATION BOARD OPERATING INSTRUCTIONS
Far-out Phase noise is worse than evaluation board instructions
show
•Ensure the measurement equipment noise floor is not limiting the measurement. For
spectrum analyzers, the noise floor at a particular setting can be measured by removing the
RF input signal
•If the settings are changed from what the board was designed for, ensure the delta-sigma
modulator is not increasing the far-out noise. To determine this, tune to an integer channel
and set the ORDER bit to “Reset Modulator”. The far out phase noise should not decrease. If
it does, try a loop filter with more attenuation or select a lower order delta-sigma modulator.
Device Data
The next few pages show data collected from the LMX2531LQ2820 evaluation board.
5

LMX2531LQ2820E EVALUATION BOARD OPERATING INSTRUCTIONS
Phase Noise
Output Frequency = 2820.25 MHz
Internal Divide by 2 Disabled (DIV2=0)
Output Frequency = 1410.125 MHz
Internal Divide by 2 Enabled (DIV2=1)
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LMX2531LQ2820E EVALUATION BOARD OPERATING INSTRUCTIONS
Free-Running VCO Phase Noise (Internal Divide by 2 Disabled)
Fout = ~2710 MHz
The plots to the left show the true phase
noise capability of the VCO. In order to
take these plots, the E5052 phase nose
analyzer was used. The method was to
lock the PLL to the proper frequency, then
disable the EN_PLL, EN_PLLLDO1,
EN_PLLLDO2, EN_DIGLDO, and
EN_OSC bits. The equipment needs to be
able to track the VCO phase noise to
measure in this way, and one can not let
the VCO drift too far off in frequency. If this
kind of equipment is not available, the
VCO phase noise can also be measured
by making a very narrow loop bandwidth
filter.
Fout = ~2820 MHz
Fout = ~2920 MHz
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LMX2531LQ2820E EVALUATION BOARD OPERATING INSTRUCTIONS
Free-Running VCO Phase Noise (Internal Divide by 2 Enabled)
Fout = ~1355 MHz (~2710 MHz/2)
The plots to the left show the true phase
noise capability of the VCO. In order to
take these plots, the E5052 phase nose
analyzer was used. The method was to
lock the PLL to the proper frequency, then
disable the EN_PLL, EN_PLLLDO1,
EN_PLLLDO2, EN_DIGLDO, and
EN_OSC bits. The equipment needs to be
able to track the VCO phase noise to
measure in this way, and one can not let
the VCO drift too far off in frequency. If this
kind of equipment is not available, the
VCO phase noise can also be measured
by making a very narrow loop bandwidth
filter.
When divide by 2 is enabled, the phase
noise at lower offsets is about 6 dB better;
but at high offsets, the phase noise
improvement may be less because the
divider is noise floor is adding to the phase
noise.
Fout = ~1410 MHz (~2820 MHz/2)
Fout = ~1460 MHz (~2920 MHz/2)
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LMX2531LQ2820E EVALUATION BOARD OPERATING INSTRUCTIONS
Fractional Spurs (Internal Divide by 2 Disabled)
The -58.9 dBc fractional spur at 250 kHz offset is
at a worst case frequency of 2710.25 MHz. The
-76.0 dBc sub-fractional spur at 125 kHz offset is
also visible.
Worst case channels occur at exactly one
channel spacing above or below a multiple of the
crystal frequency.
The -67.5 dBc fractional spur at 250 kHz offset is
at a worst case frequency of 2820.25 MHz. The
-71.8 dBc sub-fractional spur at 125 kHz offset is
also visible.
Worst case channels occur at exactly one
channel spacing above or below a multiple of the
crystal frequency.
The -63.1 dBc fractional spur at 250 kHz offset is
at a worst case frequency of 2920.25 MHz. The
-74.2 dBc sub-fractional spur at 125 kHz offset is
also visible.
Worst case channels occur at exactly one
channel spacing above or below a multiple of the
crystal frequency.
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LMX2531LQ2820E EVALUATION BOARD OPERATING INSTRUCTIONS
Fractional Spurs (Internal Divide by 2 Enabled)
The -66.2 dBc fractional spur at 250 kHz offset is
at a worst case frequency of 1355.125 MHz. The
-82.2 dBc sub-fractional spur at 125 kHz offset is
also visible.
The -72.6 dBc fractional spur at 250 kHz offset is
at a worst case frequency of 1410.125 MHz. The
-56.7 dBc sub-fractional spur at 125 kHz offset is
also visible.
The -68.2 dBc fractional spur at 250 kHz offset is
at a worst case frequency of 1460.125 MHz. The
-59.5 dBc sub-fractional spur at 125 kHz offset is
also visible.
10