National Semiconductor SERDES05-40USB User manual

SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 1 of 37
SERDES Demonstration Kit
User Manual
NSID: SERDES05-40USB
(DS99R105/106)
Rev 0.1

SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 2 of 37
Table of Contents
TABLE OF CONTENTS ........................................................................................................................................... 2
INTRODUCTION:..................................................................................................................................................... 3
CONTENTS OF THE EVALUATION KIT:........................................................................................................... 4
SERDES TYPICAL APPLICATION:...................................................................................................................... 4
HOW TO SET UP THE EVALUATION KIT:........................................................................................................ 6
POWER CONNECTION: ......................................................................................................................................... 6
SERDES SERIALIZER BOARD DESCRIPTION:................................................................................................ 7
C ONFIGURATION S ETTINGS FOR THE T X B OARD ....................................................................................................... 8
T X LVCMOS AND FPD-LINKII P INOUT BY IDC C ONNECTOR ............................................................................. 11
BOM (B ILL OF M ATERIALS ) S ERIALIZER PCB:...................................................................................................... 12
RX SERDES DE-SERIALIZER BOARD:............................................................................................................. 13
C ONFIGURATION S ETTINGS FOR THE R X B OARD .................................................................................................... 14
R X FPD-LINKII P INOUT AND LVCMOS BY IDC C ONNECTOR ............................................................................. 16
BOM (B ILL OF M ATERIALS ) D E - SERIALIZER PCB: ................................................................................................ 17
TYPICAL CONNECTION AND TEST EQUIPMENT........................................................................................ 18
TROUBLESHOOTING........................................................................................................................................... 20
APPENDIX................................................................................................................................................................ 22
SERIALIZER (TX) PCB SCHEMATIC:............................................................................................................... 22
DE-SERIALIZER (RX) PCB SCHEMATIC:........................................................................................................ 26
SERIALIZER (TX) PCB LAYOUT:...................................................................................................................... 30
SERIALIZER (TX) PCB STACKUP:.................................................................................................................... 33
DESERIALIZER (RX) PCB LAYOUT:................................................................................................................. 34
DESERIALIZER (RX) PCB STACKUP:............................................................................................................... 37

SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 3 of 37
Introduction:
National Semiconductor’s SERDES evaluation kit contains one (1) DS99R105 Serializer
(Tx) board, one (1) DS99R106 De-serializer (Rx) board, and one (1) two (2) meter high
speed USB 2.0 cable.
Note: the demo boards are not for EMI testing. The demo boards were designed for
easy accessibility to device pins with tap points for monitoring or applying signals,
additional pads for termination, and multiple connector options.
The DS99R105/106 chipset supports a variety of display applications. The single FPD-
LINKII (FPD-LinkII) interface is well-suited for any display system interface. Typical
applications include: navigation displays, automated teller machines (ATMs), POS,
video cameras, global positioning systems (GPS), portable equipment/instruments,
factory automation, etc.
The DS99R105 and DS99R106 can be used as a 24-bit general purpose FPD-LinkII
Serializer and De-serializer chipset designed to transmit data at clocks speeds ranging
from 3 to 40 MHz.
The Serializer board accepts LVCMOS input signals. The FPD-LinkII Serializer converts
the LVCMOS parallel lines into a single serialized FPD-LINKII data pair with an
embedded FPD-LINKII clock. The serial data stream toggles at 28 times the base
clock rate. With an input clock at 40 MHz, the transmission rate for FPD-LinkII line is
960Mbps.
The De-serializer board accepts the FPD-LinkII serialized data stream with embedded
clock and converts the data back into parallel LVCMOS signals and clock. Note that
NO reference clock is needed to prevent harmonic lock as with other devices currently
on the market.
Suggested equipment to evaluate the chipset, an LVCMOS signal source such as a
video generator or word generator or pulse generator and oscilloscope with a bandwidth
of at least 40 MHz will be needed.
The user needs to provide the proper LVCMOS/RGB inputs and LVCMOS/clock to the
Serializer and also provide a proper interface from the De-serializer output to an LCD
panel or test equipment. The Serializer and De-serializer boards can also be used to
evaluate device parameters. A cable conversion board or harness scramble may be
necessary depending on type of cable/connector interface used on the input to the
DS99R105 and to the output of the DS99R106.
Example of suggested display setup:
1) video generator with LVCMOS output
2) 6-bit LCD panel with a LVCMOS input interface.

SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 4 of 37
Contents of the Evaluation Kit:
1) One Serializer board with the DS99R105
2) One De-serializer board with the DS99R106
3) One 2-meter high speed USB 2.0 cable (4-pin USB A to 5-pin mini USB)
4) Evaluation Kit Documentation (this manual)
5) DS99R105/106 Datasheet
SERDES Typical Application:
Figure 1a. Typical SERDES Application (18-bit RGB Color)
Figure 1b. Typical SERDES System Diagram

SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 5 of 37
Figures 1a and 1b illustrate the use of the Chipset (Tx/Rx) in a Host to Flat Panel
Interface.
The chipsets support up to 18-bit color depth TFT LCD Panels.
Refer to the proper datasheet information on Chipsets (Tx/Rx) provided on each board
for more detailed information.

SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 6 of 37
How to set up the Evaluation Kit:
The PCB routing for the Tx input pins (DIN) have been laid out to accept incoming
LVCMOS signals from 50-pin IDC connector. The TxOUT/RxIN (DOUT/RIN) interface
uses a single twisted pair cable (provided). The PCB routing for the Rx output pins
(ROUT) are accessed through a 50-pin IDC connector. Please follow these steps to set
up the evaluation kit for bench testing and performance measurements:
1) A two (2) meter high speed USB 2.0 cable has been included in the kit. A two (2)
meter USB connector / cable assembly has been included in the kit. Connect 4-pin
USB A side of cable harness to the serializer board and the other side
5-pin mini USB jack to the de-serializer board. This completes the FPD-
LINKII interface connection.
NOTE: The DS99R105 and DS99R106 are NOT USB compliant and should not
be plugged into a USB device nor should a USB device be plugged into the
demo boards.
2) Jumpers and switches have been configured at the factory; they should not require
any changes for immediate operation of the chipset. See text on Configuration
settings for more details.
3) From the Video Decoder board, connect a flat cable (not supplied) to the Serializer
board and connect another flat cable (not supplied) from the De-serializer board to
the panel. Note: For non 50 ohm signal sources, provide 3.3V LVCMOS input signal
levels into DIN[23:0] and TCLK or remove the 49.9 ohm parallel termination
resistors R1-R25 on the DS99R105 Serializer board.
4) Power for the Tx and Rx boards must be supplied externally through Power Jack
(VDD). Grounds for both boards are connected through Power Jack (VSS) (see
section below).
Power Connection:
The Serializer and De-serializer boards must be powered by supplying power externally
through J4 (VDD) and J5 (VSS) on Serializer Board and J4 (VDD) and J5 (VSS) on De-
serializer board. Note +4V is the MAXIMUM voltage that should ever be applied to the
SERDES Serializer (DS99R105) or De-serializer (DS99R106) VDD terminal. Damage
to the device(s) can result if the voltage maximum is exceeded.
1 3 42
A
1 2 3 4 MIN

SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 7 of 37
SERDES Serializer Board Description:
The 50-pin IDC connector J1 accepts 24 bits of LVCMOS RGB data along with the
clock input.
The SERDES Serializer board is powered externally from the J4 (VDD) and J5 (VSS)
connectors shown below. For the Serializer to be operational, the Power Down (S1-
TPWDNB) and Data Enable (S1-DEN) switches on S1 must be set HIGH. The board is
factory configured (with series capacitors on the FPD-LINKII outputs) in AC coupled
mode: S1- RESVRDA, RESVRDB, and VODSEL must be set LOW. Rising or falling
edge reference clock is also selected on S1-TRFB: HIGH (rising) or LOW (falling).
The USB connector P2 (USB-A side) on the bottom side of the board provides the
interface connection to the FPD-LINKII signals to the De-serializer board. Note: P1
(mini USB) on the top side is un-stuffed and not to be used with the cable provided in
the kit.
Note:
VDD and VSS MUST
be applied externally
from here.
c
P2
(BACKSIDE)
fJ4
,
J5
cFPD-LINKII OUTPUTS
dLVCMOS INPUTS
eFUNCTION CONTROLS
fPOWER SUPPLY
g 49.9ΩINPUT TERMINATION
(For 50
Ω signal sources,
remove otherwise if populated.)
e
JP3
J1 d
S1 e
g
g
g
g
cP1 (TOPSIDE)
(UNSTUFFED)
Note:
Connect cable
(USB A side)
to P2 on BACKSIDE.

SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 8 of 37
Configuration Settings for the Tx Board
S1: Serializer Input Features Selection
Reference Description Input = L Input = H S1
RESVRDA DCAOFF MUST be
tied low for
normal
operation
(Default)
-
RESVRDB DCBOFF MUST be
tied low for
normal
operation
(Default)
-
TPWDNB PoWerDowNBar Powers
Down Operational (Default)
TRFB Latch input data
on Rising or
Falling edge of
TCLK
Falling
Edge
(Default)
Rising Edge
VODSEL FPD-LINKII
output VOD
SELect
≈350mV
(Default) ≈700mV
RESVRD RESeRVeD MUST be
tied low for
normal
operation
(Default)
DEN Output Data
ENabled Disabled Enabled
(Default)
UNUSED UNUSED Don’t care Don’t care

SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 9 of 37
JP3: Pre-Emphasis Feature Selection
Reference Description OPEN
(tied H) CLOSED
(tied L)
JP3 Pre-Emphasis* – helps to
increase the eye pattern
opening in the FPD-LINKII
stream
Disabled –
no jumper
(Default)
Enabled –
With jumper
*Note: Pre-emphasis is only needed for lossy cables and/or long cable runs
JP1, JP2: USB Red and Black wire
Reference Description VDD VSS OPEN
JP1 Power wire in USB cable
thru P2 (and P1 not
mounted) connector
Jumper RED to VSS –
recommended
Note: Normally VDD in USB application
Red wire tied
to VDD
Red wire
tied to VSS
(Default)
Red wire
floating
(not
recommended)
JP2 Power wire in USB cable
thru P2 (and P1 not
mounted) connector
Jumper BLACK to VSS –
recommended
Note: Normally VSS in USB application
Black wire
tied to VDD
Black wire
tied to VSS
(Default)
Black wire
floating
(not
recommended)
pin 2
RED WIRE
+
BLACK WIRE
_
pin 4
P2
USB A
pin 3
pin 1
top side thru the board view
(mounted on solder side)

SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 10 of 37
The following picture depicts a typical example of the FPD-Link II serial stream. This
snapshot was taken with a differential probe across the 100 ohm termination resistor R1
on the DS99R106 Rx evaluation board. R1 is the termination resistor to the RxIN +/-.
Note: The scope was triggered, with a separate probe, on TCLK, the input clock into the
DS99R105 Tx. To view the serial stream correctly, do not trigger on the probe
monitoring the serial stream.