National Semiconductor LMK03002C User manual

LMK03002C
Precision Clock Conditioner with Integrated VCO
Evaluation Board Operating Instructions
7-23-2007
National Semiconductor Corporation
Interface
2900 Semiconductor Dr.
MS A2-600
Santa Clara, CA, 95052-8090

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T ABLE OF C ONTENTS
GENERAL DESCRIPTION ............................................................................................................................... 3
LOOP FILTER #1........................................................................................................................................... 3
READ FIRST,BASIC OPERATION................................................................................................................... 4
BOARD INFORMATION.................................................................................................................................. 8
OSCin ................................................................................................................................................... 8
Fout....................................................................................................................................................... 8
Loop Filter ............................................................................................................................................ 8
Features of the board............................................................................................................................. 9
Other Important Notes .......................................................................................................................... 9
RECOMMENDED EQUIPMENT...................................................................................................................... 10
PHASE NOISE ............................................................................................................................................. 11
DELAYS...................................................................................................................................................... 12
CODELOADER SETTINGS............................................................................................................................ 13
APPENDIX A: VCO PERFORMANCE............................................................................................................ 17
Loop Filter #2 ..................................................................................................................................... 17
APPENDIX B: IMPACT OF REFERENCE ON PHASE NOISE............................................................................. 19
APPENDIX C: SCHEMATICS ........................................................................................................................ 20
APPENDIX D: BILL OF MATERIALS............................................................................................................. 23
APPENDIX E: BUILD DIAGRAM .................................................................................................................. 25

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General Description
The LMK03002C Evaluation Board simplifies evaluation of the LMK03002C Precision Clock
Conditioner with Integrated VCO. The package consists of an evaluation board and CodeLoader
software. The CodeLoader software will run on a Windows 2000 or Windows XP PC. The purpose of
the CodeLoader software is to program the internal registers of the LMK03002C device through a
MICROWIRE
TM
interface.
The LMK0300xC PCB works for many LMK0300xC devices. Because of this the silkscreen on
the board is different from actual clock outputs in the datasheet and in CodeLoader. Refer to the
table below for the correct mapping.
Datasheet / CodeLoader LMK0300xC EVB PCB
CLKout0 / CLKout0* CLKout4 / CLKout4*
CLKout1 / CLKout1* CLKout5 / CLKout5*
CLKout2 / CLKout2* CLKout6 / CLKout6*
CLKout3 / CLKout3* CLKout7 / CLKout7*
Loop Filter #1
Phase Margin 63º Kφ
φφ
φ3200 uA
Loop Bandwidth 105 kHz Fcomp 16 MHz
Crystal Frequency 16 MHz Output Frequency 1566 to 1724 MHz
Supply Voltage 3.3 Volts VCO Gain 13 MHz/Volt
VCO
open
12 nF1.8 kΩ
Ω Ω
Ω
100 pF 110 pF
600 Ω
ΩΩ
Ω200 Ω
ΩΩ
Ω
CPout
Charge Pump
C1
C2R2
R3 R4
C3 C4
(Loop filter #1 is selected by placing a 0 ohm resistor on pad R22)

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Read first, Basic Operation
Read the document, “Installing CodeLoader 4 & USB Driver” for instructions to prepare the computer
for usage with the evaluation board before continuing with the hardware setup.
For basic operation…
1. Connect a low noise 3.3 V power supply to the Vcc connector located at the top left of the
board
2. Connect the CodeLoader cable to the uWire header located in the lower left.

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Read first, Basic Operation (Continued)
3. Connect…
•PC directly to the evaluation board with the LPT to uWire cable, plugging the cable
into an LPT port on the computer and then the 10 pin ribbon connector to the
evaluation board. This setup is shown below. The cable can be removed after
programming to minimize noise and EMI.
or
•Available separately, the USB <--> uWire board to the PC with the USB cable and the
USB <--> uWire board to the evaluation board with the 10 pin ribbon cable.
LPT Setup

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Read first, Basic Operation (Continued)
4. Start CodeLoader 4.
5. Select the USB or LPT Communication Mode on the Port Setup tab as appropriate.
6. Select the default mode by clicking “Mode” “16 MHz OSCin”

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Read first, Basic Operation (Continued)
7. Enable output to be measured, any of CLKout(0-7) or EN_Fout from either Clock Outputs or
Bits/Pins tab.
8. Program the part by clicking “Keyboard Controls” “LoadDevice” or by pressing Ctrl+L.
9. Make measurements… After programming, the uWire cable can be unplugged from the
evaluation board to minimize noise and EMI.

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Board Information
OSCin
By default the board is configured to use the on-board crystal oscillator. It is also possible to use the
board with a single ended or differential reference source at the OSCin port. Below are several
possible configurations for driving OSCin.
OSCin using on board crystal oscillator [default]
0 ohm R8, R11, R20 [power to crystaloscillator], R109
39ohm R9 [can also be 0 ohm – depends on oscillator output power, 39 ohms
to be a voltage divider]
51 ohm R15
0.1 uF C35, C36 (C5 is a 0.1 uF 0402 cap which may be moved to C36)
Open C4, C5
R7, R10, R12, R13, R14, R16, R17, R79, R112
Differential OSCin setup
0 ohm R7, R8, R10, R13
100 ohm R17
0.1 uF C5, C35 (C36 is a 0.1 uF 0402 cap which may be moved to C5)
Open C4, C36
R11, R12, R14, R15, R16, R79
R20 [remove power from crystal oscillator for noise reasons]
Single ended OSCin setup
0 ohm R7, R8
51 ohm R15
0.1 uF C35, C36 (C5 is a 0.1 uF 0402 cap which may be moved to C36)
Open C4, C5
R10, R11, R12, R13, R14, R16, R17, R79
R20 [remove power from crystal oscillator for noise reasons]
Fout
Fout allows direct access to the internal VCO before the clock distribution section. The EN_Fout bit
must be selected to enable Fout. A 3 dB pad is placed on R80, R81, and R82.
Loop Filter
R22 and R5 form a “resistor switch” which allows either one of two different loop filters to be
selected.
Loop Filter Resistor
Switch Loop Filter Components Default Loop Bandwidth
Loop Filter #1
[default] R22 Shorted C1, C2, C2p, R2 105 kHz
Loop Filter #2 R5 Shorted C1_AUX, C2_AUX,
C2p_AUX, R2_AUX 55 Hz

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Features of the board
•Either one of two loop filters can be selected by shorting either R22 or R5. More info
about each loop filter can be found in the General Description and Appendix A.
•Test points for each of the uWire lines are scattered in the lower left corner of the board
and include: GOE_TP, DATAuWire, CLKuWire, LEuWire, SYNC_TP, and LD_TP.
•Ground is located on the unstuffed 10 pin header on the left side of the board.
•Ground is located on the GND_tp2 in the upper left corner of the board and GND_tp1
located to the right of the Vcc SMA connector.
•Ground is located on the bottom side of the board on each pad of the unstuffed 10 pin
header GND_J2.
•Vcc is located on the unstuffed 10 pin header on the upper left side of the board.
•Vcc is located on VccPlane test point located to the right of the Vcc SMA.
•Vcc is located on the bottom side of the board on each pad of the unstuffed 10 pin
header VCC_J2
Other Important Notes
•When changing the OSCin frequency, the OSCin frequency register needs to be changed
to match.
•Toggle the SYNC* pin to synchronize the clock outputs when in divided mode.
•For both loop filters, a helper silkscreen is offset from the loop filters to help identify the
components according to National Semiconductor’s traditional reference designators
associated with loop filters.
•The LMK0300xC PCB works for many LMK0300xC devices. Because of this the
silkscreen on the board is different from actual clock outputs in the datasheet and in
CodeLoader. Refer to the table below for the correct mapping.
Datasheet / CodeLoader LMK0300xC EVB PCB
CLKout0 / CLKout0* CLKout4 / CLKout4*
CLKout1 / CLKout1* CLKout5 / CLKout5*
CLKout2 / CLKout2* CLKout6 / CLKout6*
CLKout3 / CLKout3* CLKout7 / CLKout7*

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Recommended Equipment
Power Supply
The Power Supplyshould be a low noise power supply. An Agilent 6623A Triple power supply with LC
filters on the output to reduce noise was used in creating these evaluation board instructions.
Phase Noise / Spectrum Analyzer
For measuring phase noise an Agilent E5052A is recommended. An Agilent E4445A PSA Spectrum
Analyzer with the PhaseNoise option is also usable althoughthe architecture of the E5052Ais superior
for phase noise measurements. At frequencies less than 100 MHz the local oscillator noise of the PSA
is too high and measurements will be of the localoscillator, not the device under test.
Oscilloscope
For measuring delay an Agilent Infiniium DSO81204A was used.
Reference Oscillator
The on board crystal oscillator will provide a low noise reference signal to the device at offsets greater
than 1 kHz.
Note: The default loop filter has a loop bandwidth of ~105 kHz. Inside the loop bandwidth of a PLL the
noise is greatly affected by any noise on the reference oscillator (OSCin). Therefore any noise on the
oscillator less than ~105 kHz will be passed through and seen on the outputs. For this reason the main
output of a Signal Generator is not recommended for driving OSCin in this setup.

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Phase Noise
Output Frequency = 1632 MHz
Internal VCO, Fout output
Reference source is on board 16 MHz crystal
Below ~1 kHz phase noise is dominated by the crystal
10 Hz – 20 MHz integrated RMS jitter = 474 fs
100 Hz – 20 MHz integrated RMS jitter = 202 fs
12 kHz – 20 MHz integrated RMS jitter = 188 fs (shown)
LVPECL output CLKout0 (Labeled CLKout4on EVB)
VCO Frequency = 1632 MHz, VCO_DIV=2, CLKout0_div=4
LVPECL output (204 MHz)
Reference source is on board 16 MHz crystal
Below ~1 kHz phase noise is dominated by the crystal
10 Hz – 20 MHz integrated RMS jitter = 636 fs
100 Hz – 20 MHz integrated RMS jitter = 205 fs
12 kHz – 20 MHz integrated RMS jitter = 193 fs (shown)

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Delays
These delay measurements illustrate how skew errors due to different length traces may betuned out.
The delaymay be adjusted in steps of 150 ps.
Delays 150, 300, 450, 600, 750
CLKout0_DLY = 0 ps
CLKout1_DLY = all delays
programmed:0, 150, 300, 450,
600, 750, 900, 1050, 1200,
1350, 1500, 1650, 1800,1950,
2100, and 2250 ps

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CodeLoader Settings
The Port Setup tab tells CodeLoader what signals are assigned to which pins. If this is wrong,
the part will not program.
Part setup can be restored to the default state by clicking Mode “16 MHz OSCin” The default
reference oscillator used for these instructions is 16 MHz and the restored mode expects a 16
MHz OSCin signal. For the loaded mode to take affect the device must be loaded by
pressing Ctrl+L.

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The Bits/Pins tab shows some of the internal registers which are not accessible from any of the
other visual tabs like “PLL” and “Clock Outputs.” Right click on any of the bits for description.
Program Bits
POWERDOWN Powers the part down.
EN_Fout Turns on the Fout pin for measuring the internal VCO.
OSCin_FREQ Must be set to the OSCin frequency in MHz.
PLL_MUX Programmable to many different values to support Lock Detect or aid
troubleshooting.
DIV4 Shall be checked for OSCin frequencies greater than 20 MHz.
RESET The registers can be defaulted by checking and unchecking RESET.
Software bits will not reflect this.
VCO_R3_LF
VCO_R4_LF
VCO_C3_C4_LF Internal loop filter values, also accessible from Clock Outputs tab.
EN_CLKout0..3 Enable CLKout bits from CLKout0 to CLKout7. Also accessible from Clock
Outputs tab.
EN_CLKout_Global
Enable all clock outs. If unselected then the EN_CLKouts are overridden
and the outputs are all disabled.
Program Pins
GOE Set Global Output Enable to high or low logic level. GOE is not used.
See Board Information section for usage of this pin.
SYNC* Set SYNC* pin to high or low logic level.
TRIGGER Set auxiliary trigger pin to high or low logic level.

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The Registers tab shows the raw bits which will be programmed when device is loaded by
clicking Keyboard Controls Load Device or Ctrl+L.
The Clock Outputs tab allows the user to visualize the clock distribution portions of the device.
From this tab the device’s dividers, delays, clock output muxes, and output drivers can be
programmed along with internal loop filter values. The PLL block shows the R and N divider
values however to change these values either click on the PLL tab or the blue PLL box to access
the PLL tab to make changes to the PLL.

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The PLL tab shows a conventional PLL diagram along with the VCO Divider. It is important to
realize that the total effective N value is PLL N Counter * VCO Divider. This means that the
“channel spacing” is the Phase Detector Frequency * VCO Divider. Depending on the
situation, this may require the R Counter multiplied up by the value of the VCO Divider to achieve
desired VCO output frequencies.
Example: If the desired VCO output frequency was 1648 MHz, R would need to be increased to
2 before 1648 MHz could be programmed because of the VCO Divider of 2 would only allow
programming of 1600, 1632, 1664, etc. with a 16 MHz phase detector frequency – because
changing the N counter from 51 to 52 changes to total N by two, 102 to 104!

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AppendixA: VCO Performance
The internal VCO performance is measured by using a narrow bandwidth loop filter. By default
the narrow loop bandwidth filter is stuffed as Loop Filter #2 in positions C1_AUX, C2_AUX,
C2p_AUX, and R2_AUX and has a loop bandwidth of 55 Hz.
See the Loop Filter section in Board Options for more detail about switching between the two
different loop filters.
Loop Filter #2
Phase Margin 58º Kφ
φφ
φ100 uA
Loop Bandwidth 55 Hz Fcomp 500 kHz
Crystal Frequency 16 MHz Output Frequency 1566 to 1724 MHz
Supply Voltage 3.3 Volts VCO Gain 13 MHz/Volt
VCO
820 nF
10 uF820 Ω
Ω Ω
Ω
150 pF 110 pF
600 Ω
ΩΩ
Ω200 Ω
ΩΩ
Ω
CPout
Charge Pump
C1
C2R2
R3 R4
C3 C4
This loop filter is located on the top side of the PCB and is selected by placing a
0 ohm resistor on pad R5.
This loop filter has been designed with a very small loop bandwidth to minimize
the PLL from interacting with the noise of the VCO to permit a VCO phase noise
measurement.

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VCO Phase Noise – Narrow Loop Bandwidth
This plot shows the noise of the VCO at 1632 MHz using a 500 kHz Phase
Detector Frequency. An external oscillator was used for this plot, since the VCO
noise dominates, reference oscillator noise is not critical.
The loop bandwidth has been minimized so that the VCO is the dominant noise
contributor.
10 Hz – 20 MHz integrated RMS jitter = 107.6 ps
100 Hz – 20 MHz integrated RMS jitter = 28.1 ps (shown)
1 kHz – 20 MHz integrated RMS jitter = 2.7 ps
12 kHz – 20 MHz integrated RMS jitter = 0.303 ps

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Appendix B: Impact of Reference on Phase Noise
Inside the loop bandwidth of a PLL the phase noise is set by the quality of the
reference oscillator used. For this reason it is important to select a reference
oscillator suitable for the application.
Test Setup
Using the same loop filter as described in the General Description and by driving
the OSCin frequency with an ultra low jitter 100 MHz Wetzel Crystal (501-
04517D) and setting R = 5 to achieve a phase detector frequency of 20 MHz. A
very low integrated RMS jitter of 201 fs is measured vs. the 474 fs measured in
the Phase Noise section with 16 MHz crystal in the bandwidth of 10 Hz to 20
MHz.
10 Hz – 20 MHz integrated RMS jitter = 201 fs (shown)
100 Hz – 20 MHz integrated RMS jitter = 197 fs
1 kHz – 20 MHz integrated RMS jitter = 196 fs
12 kHz – 20 MHz integrated RMS jitter = 188 fs
Conclusion
This diagram illustrates how the phase noise inside the loop bandwidth is set by
the quality of the reference oscillator used. Phase noise outside the loop
bandwidth is set by the VCO noise level.

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Appendix C: Schematics
LMK0300x - Main Board
LMK0300x - Main Board.sch LMK0300x -Outputs LMK0300x -Outputs.sch F1
PCB_LMK0300x
1 2
3 4
5 6
7 8
9 10
J2
GND_HDR
1 2
3 4
5 6
7 8
9 10
J3
VCC_HDR
Vcc Vcc
1 2
3 4
5 6
7 8
9 10
J4
GND_HDR
1 2
3 4
5 6
7 8
9 10
J5
VCC_HDR
Vcc Vcc