Nintendo DMG-01 - Game Boy Console User manual

Sources by: Pan of Anthrox, GABY, Marat Fayzullin,
Pascal Felber, Paul Robson, Martin Korth, kOOPa, Bowser
Contents:
Assembly Language Commands, Timings and Opcodes, and
everything you always wanted to know about GB but were
afraid to ask.
THIS DOCUMENT IS PRINTED ON DIN A5 SIZE PAPER
(148mm x 210mm)!
Note: Game BoyTM, Game Boy PocketTM, Super Game BoyTM and Game
Boy ColorTM are registered trademarks of Nintendo CO., LTD.
© 1989 to 1999 by Nintendo CO., LTD.
Version: 1.01 by DP
Game BoyTM
CPU Manual

1. Foreword Game BoyTM CPU Manual
Table of Contents
1. Foreword...........................................4
2. Hardware specifications............................5
2.1. Forward:.......................................5
2.2. Terms..........................................5
2.3. Game Boy Specs.................................6
2.4. Processor......................................6
2.5. Memory Map.....................................8
2.5.1. General memory map.........................8
2.5.2. Echo of 8kB Internal RAM...................9
2.5.3. User I/O...................................9
2.5.4. Reserved Memory Locations.................10
2.6. Cartridge Types...............................13
2.7. Special modi..................................17
2.7.1. Power Up Sequence.........................17
2.7.2. Stop Mode.................................19
2.7.3. Low-Power Mode............................19
2.8. Video.........................................22
2.8.1. Tiles.....................................22
2.8.2. Sprites...................................25
2.8.3. Sprite RAM Bug............................27
2.9. Sound.........................................28
2.10. Timer........................................30
2.11. Serial I/O...................................31
2.12. Interrupts...................................32
2.12.1. Interrupt Procedure......................32
2.12.2. Interrupt Descriptions...................34
2.13. Special Registers............................35
2.13.1. I/O Registers............................35
Page 2V 1.01

Game BoyTM CPU Manual 1. Foreword
3. Game Boy command overview.........................61
3.1. Foreword......................................61
3.2. CPU Registers.................................61
3.2.1. Generally.................................61
3.2.2. Flag Register.............................62
3.2.3. Program Counter...........................63
3.2.4. Stack Pointer.............................63
3.3. Commands......................................65
3.3.1. 8-Bit Loads...............................65
3.3.2. 16-Bit Loads..............................76
3.3.3. 8-Bit ALU.................................80
3.3.4. 16-Bit Arithmetic.........................90
3.3.5. Miscellaneous.............................94
3.3.6. Rotates & Shifts..........................99
3.3.7. Bit Opcodes..............................108
3.3.8. Jumps....................................111
3.3.9. Calls....................................114
3.3.10. Restarts................................116
3.3.11. Returns.................................117
4. Super Game Boy commands..........................119
4.1. Foreword.....................................119
4.2. Palettes.....................................119
4.3. SGB Border...................................120
4.4. Main Action Window...........................121
4.5. Commands.....................................122
5. Appendix A.......................................134
5.1. Emulator Notes...............................134
5.2. Typical timing diagram.......................137
by DP Page 3

1. Foreword Game BoyTM CPU Manual
1. Foreword
This Document was designed to help you programming the
Game BoyTM Classic,Game BoyTM Pocket,Super Game BoyTM
and Game BoyTM Color (basics - you will need additional
documents for GBC specific programming). It was ment to
be a complete handbook to start right off coding for
the hardware. The documents consists of three major
parts.
The first is the 'GBSpec.txt' (also known as the Pan
Document) by Pan of Anthrox,Marat Fayzullin,Pascal
Felber,Paul Robson,Martin Korth,kOOPa. This will be
found in paragraph 1.
The second is a mixture of several documents from
'Game Boy Assembly Language Primer (GALP) V1.0'by GABY
(GAmeBoY). It contains opcodes, time duration and the
affected flags per ASM command and the. This can be
found in paragraph 2.
The third is a summary of specifications and commands
for Nintendo Super Game Boy speciffic programming by
kOOPa and Bowser. See paragraph 3.
Information on how to get your emulator proved
programs run on a real Game Boy can be found in the
Appendix (thanks to kOOPa). Also, a timing diagram of a
typical read and write operation on the classic GB bus
can be found here (thanks to Philippe Pouliquen).
On the last page a quick reference of ASM commands is
included.
Have fun!
DP
Page 4V 1.01

Game BoyTM CPU Manual 2. Hardware specifications
2. Hardware specifications
2.1. Forward:
The following was typed up for informational purposes
regarding the inner workings on the hand-held game
machine known as Game Boy, manufactured and designed by
Nintendo Co., LTD. This info is presented to inform a
user on how their Game Boy works and what makes it
"tick". GameBoy is copyrighted by Nintendo Co., LTD.
Any reference to copyrighted material is not presented
for monetary gain, but for educational purposes and
higher learning.
2.2. Terms
GB = Original GameBoy (GameBoy Classic)
GBP = GameBoy Pocket/GameBoy Light
GBC = GameBoy Color
SGB = Super GameBoy
by DP Page 5

2.3. Game Boy Specs Game BoyTM CPU Manual
2.3. Game Boy Specs
•CPU: 8-bit (Similar to the Z80 processor.)
•Main RAM: 8K Byte
•Video RAM: 8K Byte
•Screen Size 2.6"
•Resolution: 160x144 (20x18 tiles)
•Max # of sprites: 40
•Max # sprites/line: 10
•Max sprite size: 8x16
•Min sprite size: 8x8
•Clock Speed: 4.194304 MHz
(4.295454 SGB, 4.194/8.388MHz GBC)
•Horiz Sync: 9198 KHz (9420 KHz for SGB)
•Vert Sync: 59.73 Hz (61.17 Hz for SGB)
•Sound: 4 channels with stereo sound
•Power: DC6V 0.7W (DC3V 0.7W for GB Pocket)
Nintendo documents describe the CPU & instructions
speed in machine cycles while this document describes
them in clock cycles. Here is the translation:
1 machine cycle = 4 clock cycles
GB CPU Speed NOP Instruction
Machine Cycles 1.05MHz 1 cycle
Clock Cycles 4.19MHz 4 cycles
2.4. Processor
The GameBoy uses a computer chip similar to an Intel
8080. It contains all of the instructions of an 8080
except there are no exchange instructions. In many
ways the processor is more similar to the Zilog Z80
processor. Compared to the Z80, some instructions
Page 6V 1.01

Game BoyTM CPU Manual 2.4. Processor
have been added and some have been taken away.
The following are added instructions:
ADD SP,nn ;nn = signed byte
LDI (HL),A ;Write A to (HL) and increment HL
LDD (HL),A ;Write A to (HL) and decrement HL
LDI A,(HL) ;Write (HL) to A and increment HL
LDD A,(HL) ;Write (HL) to A and decrement HL
LD A,($FF00+nn)
LD A,($FF00+C)
LD ($FF00+nn),A
LD ($FF00+C),A
LD (nnnn),SP
LD HL,SP+nn ;nn = signed byte
STOP ;Stop processor & screen until
button press
SWAP r ;Swap high & low nibbles of r
The following instructions have been removed:
Any command that uses the IX or IY registers.
All IN/OUT instructions.
All exchange instructions.
All commands prefixed by ED (except remapped RETI).
All conditional jumps/calls/rets on parity/overflow
and sign flag.
The following instructions have different opcodes:
LD A,[nnnn]
LD [nnnn],A
RETI
by DP Page 7

2.5. Memory Map Game BoyTM CPU Manual
2.5. Memory Map
2.5.1. General memory map
Interrupt Enable Register
--------------------------- FFFF
Internal RAM
--------------------------- FF80
Empty but unusable for I/O
--------------------------- FF4C
I/O ports
--------------------------- FF00
Empty but unusable for I/O
--------------------------- FEA0
Sprite Attrib Memory (OAM)
--------------------------- FE00
Echo of 8kB Internal RAM
--------------------------- E000
8kB Internal RAM
--------------------------- C000
8kB switchable RAM bank
--------------------------- A000
8kB Video RAM
--------------------------- 8000 --
16kB switchable ROM bank |
--------------------------- 4000 |= 32kB Cartrigbe
16kB ROM bank #0 |
--------------------------- 0000 --
* NOTE: b = bit, B = byte
Page 8V 1.01

Game BoyTM CPU Manual 2.5.2. Echo of 8kB Internal RAM
2.5.2. Echo of 8kB Internal RAM
The addresses E000-FE00 appear to access the internal
RAM the same as C000-DE00. (i.e. If you write a byte to
address E000 it will appear at C000 and E000.
Similarly, writing a byte to C000 will appear at C000
and E000.)
2.5.3. User I/O
There are no empty spaces in the memory map for
implementing input ports except the switchable RAM bank
area (not an option on the Super Smart Card since it's
RAM bank is always enabled). An output only port may be
implemented anywhere between A000-FDFF. If implemented
in a RAM area care should be taken to use an area of
RAM not used for anything else. (FE00 and above can't
be used because the CPU doesn't generate an external
/WR for these locations.)
If you have a cart with an MBC1, a ROM 4Mbit or
smaller, and a RAM 8Kbyte or smaller (or no RAM) then
you can use pins 6 & 7 of the MBC1 for 2 digital output
pins for whatever purpose you wish. To use them you
must first put the MBC1 into 4MbitROM/32KbyteRAM mode
by writing 01 to 6000. The two least significant bits
you write to 4000 will then be output to these pins.
by DP Page 9

2.5.4. Reserved Memory Locations Game BoyTM CPU Manual
2.5.4. Reserved Memory Locations
0000 Restart $00 Address
(RST $00 calls this address.)
0008 Restart $08 Address
(RST $08 calls this address.)
0010 Restart $10 Address
(RST $10 calls this address.)
0018 Restart $18 Address
(RST $18 calls this address.)
0020 Restart $20 Address
(RST $20 calls this address.)
0028 Restart $28 Address
(RST $28 calls this address.)
0030 Restart $30 Address
(RST $30 calls this address.)
0038 Restart $38 Address
(RST $38 calls this address.)
0040 Vertical Blank Interrupt Start Address
0048 LCDC Status Interrupt Start Address
0050 Timer Overflow Interrupt Start Address
0058 Serial Transfer Completion Interrupt
Start Address
0060 High-to-Low of P10-P13 Interrupt
Start Address
An internal information area is located at 0100-014F in
each cartridge. It contains the following values:
0100-0103 This is the begin code execution point in a
cart. Usually there is a NOP and a JP
instruction here but not always.
Page 10 V 1.01

Game BoyTM CPU Manual 2.5.4. Reserved Memory
Locations
0104-0133 Scrolling Nintendo graphic:
CE ED 66 66 CC 0D 00 0B 03 73 00 83 00 0C 00 0D
00 08 11 1F 88 89 00 0E DC CC 6E E6 DD DD D9 99
BB BB 67 63 6E 0E EC CC DD DC 99 9F BB B9 33 3E
( PROGRAM WON'T RUN IF CHANGED!!!)
0134-0142 Title of the game in UPPER CASE ASCII. If it
is less than 16 characters then the
remaining bytes are filled with 00's.
0143 $80 = Color GB, $00 or other = not Color GB
0144 Ascii hex digit, high nibble of licensee
code (new).
0145 Ascii hex digit, low nibble of licensee
code (new). (These are normally $00 if
[$014B] <> $33.)
0146 GB/SGB Indicator (00 = GameBoy, 03 = Super
GameBoy functions)
(Super GameBoy functions won't work
if <> $03.)
0147 Cartridge type:
0-ROM ONLY 12-ROM+MBC3+RAM
1-ROM+MBC1 13-ROM+MBC3+RAM+BATT
2-ROM+MBC1+RAM 19-ROM+MBC5
3-ROM+MBC1+RAM+BATT 1A-ROM+MBC5+RAM
5-ROM+MBC2 1B-ROM+MBC5+RAM+BATT
6-ROM+MBC2+BATTERY 1C-ROM+MBC5+RUMBLE
8-ROM+RAM 1D-ROM+MBC5+RUMBLE+SRAM
9-ROM+RAM+BATTERY 1E-ROM+MBC5+RUMBLE+SRAM+BATT
B-ROM+MMM01 1F-Pocket Camera
C-ROM+MMM01+SRAM FD-Bandai TAMA5
D-ROM+MMM01+SRAM+BATT FE - Hudson HuC-3
by DP Page 11

2.5.4. Reserved Memory Locations Game BoyTM CPU Manual
F-ROM+MBC3+TIMER+BATT FF - Hudson HuC-1
10-ROM+MBC3+TIMER+RAM+BATT
11-ROM+MBC3
0148 ROM size:
0 - 256Kbit = 32KByte = 2 banks
1 - 512Kbit = 64KByte = 4 banks
2 - 1Mbit = 128KByte = 8 banks
3 - 2Mbit = 256KByte = 16 banks
4 - 4Mbit = 512KByte = 32 banks
5 - 8Mbit = 1MByte = 64 banks
6 - 16Mbit = 2MByte = 128 banks
$52 - 9Mbit = 1.1MByte = 72 banks
$53 - 10Mbit = 1.2MByte = 80 banks
$54 - 12Mbit = 1.5MByte = 96 banks
0149 RAM size:
0 - None
1 - 16kBit = 2kB = 1 bank
2 - 64kBit = 8kB = 1 bank
3 - 256kBit = 32kB = 4 banks
4 - 1MBit =128kB =16 banks
014A Destination code:
0 - Japanese
1 - Non-Japanese
014B Licensee code (old):
33 - Check 0144/0145 for Licensee code.
79 - Accolade
A4 - Konami
(Super GameBoy function won't work
if <> $33.)
014C Mask ROM Version number (Usually $00)
Page 12 V 1.01

Game BoyTM CPU Manual 2.5.4. Reserved Memory
Locations
014D Complement check
(PROGRAM WON'T RUN ON GB IF NOT CORRECT!!!)
(It will run on Super GB, however,
if incorrect.)
014E-014F Checksum (higher byte first) produced by
adding all bytes of a cartridge except for
two checksum bytes and taking two lower
bytes of the result. (GameBoy ignores this
value.)
2.6. Cartridge Types
The following define the byte at cart location 0147:
•ROM ONLY
This is a 32kB (256kb) ROM and occupies 0000-7FFF.
•MBC1 (Memory Bank Controller 1)
MBC1 has two different maximum memory modes:
16Mbit ROM/8KByte RAM or 4Mbit ROM/32KByte RAM.
The MBC1 defaults to 16Mbit ROM/8KByte RAM mode
on power up. Writing a value (XXXXXXXS - X = Don't
care, S = Memory model select) into 6000-7FFF area
will select the memory model to use. S = 0 selects
16/8 mode. S = 1 selects 4/32 mode.
Writing a value (XXXBBBBB - X = Don't cares, B =
bank select bits) into 2000-3FFF area will select
an appropriate ROM bank at 4000-7FFF. Values of 0
and 1 do the same thing and point to ROM bank 1.
by DP Page 13

2.6. Cartridge Types Game BoyTM CPU Manual
Rom bank 0 is not accessible from 4000-7FFF and can
only be read from 0000-3FFF.
If memory model is set to 4/32:
Writing a value (XXXXXXBB - X = Don't care, B =
bank select bits) into 4000-5FFF area will select
an appropriate RAM bank at A000-C000. Before you
can read or write to a RAM bank you have to enable
it by writing a XXXX1010 into 0000-1FFF area*. To
disable RAM bank operations write any value but
XXXX1010 into 0000-1FFF area. Disabling a RAM bank
probably protects that bank from false writes
during power down of the GameBoy. (NOTE: Nintendo
suggests values $0A to enable and $00 to disable
RAM bank!!)
If memory model is set to 16/8 mode:
Writing a value (XXXXXXBB - X = Don't care, B =
bank select bits) into 4000-5FFF area will set the
two most significant ROM address lines.
* NOTE: The Super Smart Card doesn't require this
operation because it's RAM bank is ALWAYS enabled.
Include this operation anyway to allow your code
to work with both.
•MBC2 (Memory Bank Controller 2):
This memory controller works much like the MBC1
controller with the following exceptions:
MBC2 will work with ROM sizes up to 2Mbit.
Writing a value (XXXXBBBB - X = Don't cares, B =
bank select bits) into 2000-3FFF area will select
an appropriate ROM bank at 4000-7FFF.
RAM switching is not provided. Unlike the MBC1
which uses external RAM, MBC2 has 512 x 4 bits of
Page 14 V 1.01

Game BoyTM CPU Manual 2.6. Cartridge Types
RAM which is in the controller itself. It still
requires an external battery to save data during
power-off though.
The least significant bit of the upper address
byte must be zero to enable/disable cart RAM. For
example the following addresses can be used to
enable/disable cart RAM:
0000-00FF, 0200-02FF, 0400-04FF, ..., 1E00-1EFF.
enable/disable is 0000-00FF. The suggested address
range to use for MBC2 ram
The least significant bit of the upper address
byte must be one to select a ROM bank. For example
the following addresses can be used to select a ROM
bank: 2100-21FF, 2300-23FF, 2500-25FF, ..., 3F00-
3FFF. The suggested address range to use for MBC2
rom bank selection is 2100-21FF.
•MBC3 (Memory Bank Controller 3):
This controller is similar to MBC1 except it
accesses all 16mbits of ROM without requiring any
writes to the 4000-5FFF area.
Writing a value (XBBBBBBB - X = Don't care, B =
bank select bits) into 2000-3FFF area will select
an appropriate ROM bank at 4000-7FFF.
Also, this MBC has a built-in battery-backed Real
Time Clock (RTC) not found in any other MBC. Some
MBC3 carts do not support it (WarioLand II non
color version) but some do (Harvest Moon/Japanese
version.)
•MBC5 (Memory Bank Controller 5):
This controller is the first MBC that is guaranteed
to run in GameBoy Color double-speed mode but it
appears the other MBC's run fine in GBC double
speed mode as well.
by DP Page 15

2.6. Cartridge Types Game BoyTM CPU Manual
It is similar to the MBC3 (but no RTC) but can
access up to 64mbits of ROM and up to 1mbit of RAM.
The lower 8 bits of the 9-bit rom bank select is
written to the 2000-2FFF area while the upper bit
is written to the least significant bit of the
3000-3FFF area.
Writing a value (XXXXBBBB - X = Don't care, B =
bank select bits) into 4000-5FFF area will select
an appropriate RAM bank at A000-BFFF if the cart
contains RAM. Ram sizes are 64kbit,256kbit, &
1mbit.
Also, this is the first MBC that allows rom bank 0
to appear in the 4000-7FFF range by writing $000
to the rom bank select.
•Rumble Carts:
Rumble carts use an MBC5 memory bank controller.
Rumble carts can only have up to 256kbits of RAM.
The highest RAM address line that allows 1mbit of
RAM on MBC5 non-rumble carts is used as the motor
on/off for the rumble cart.
Writing a value (XXXXMBBB - X = Don't care, M =
motor, B = bank select bits) into 4000-5FFF area
will select an appropriate RAM bank at A000-BFFF
if the cart contains RAM. RAM sizes are 64kbit or
256kbits. To turn the rumble motor on set M = 1,
M = 0 turns it off.
•HuC1 (Memory Bank / Infrared Controller):
This controller made by Hudson Soft appears to be
very similar to an MBC1 with the main difference
being that it supports infrared LED input / output.
The Japanese cart "Fighting Phoenix" (internal cart
name: SUPER B DAMAN) is known to contain this chip.
Page 16 V 1.01

Game BoyTM CPU Manual 2.7. Special modi
2.7. Special modi
2.7.1. Power Up Sequence
When the GameBoy is powered up, a 256 byte program
starting at memory location 0 is executed. This
program is located in a ROM inside the GameBoy. The
first thing the program does is read the cartridge
locations from $104 to $133 and place this graphic of
a Nintendo logo on the screen at the top. This image
is then scrolled until it is in the middle of the
screen. Two musical notes are then played on the
internal speaker. Again, the cartridge locations $104
to $133 are read but this time they are compared with
a table in the internal rom.
If any byte fails to compare, then the GameBoy stops
comparing bytes and simply halts all operations.
GB & GB Pocket:
Next, the GameBoy starts adding all of the bytes
in the cartridge from $134 to $14d. A value of 25
decimal is added to this total. If the least
significant byte of the result is a not a zero,
then the GameBoy will stop doing anything.
Super GB:
Even though the GB & GBP check the memory
locations from $134 to $14d, the SGB doesn't.
If the above checks pass then the internal ROM is
disabled and cartridge program execution begins at
location $100 with the following register values:
AF=$01-GB/SGB, $FF-GBP, $11-GBC
F =$B0
by DP Page 17

2.7.1. Power Up Sequence Game BoyTM CPU Manual
BC=$0013
DE=$00D8
HL=$014D
Stack Pointer=$FFFE
[$FF05] = $00 ; TIMA
[$FF06] = $00 ; TMA
[$FF07] = $00 ; TAC
[$FF10] = $80 ; NR10
[$FF11] = $BF ; NR11
[$FF12] = $F3 ; NR12
[$FF14] = $BF ; NR14
[$FF16] = $3F ; NR21
[$FF17] = $00 ; NR22
[$FF19] = $BF ; NR24
[$FF1A] = $7F ; NR30
[$FF1B] = $FF ; NR31
[$FF1C] = $9F ; NR32
[$FF1E] = $BF ; NR33
[$FF20] = $FF ; NR41
[$FF21] = $00 ; NR42
[$FF22] = $00 ; NR43
[$FF23] = $BF ; NR30
[$FF24] = $77 ; NR50
[$FF25] = $F3 ; NR51
[$FF26] = $F1-GB, $F0-SGB ; NR52
[$FF40] = $91 ; LCDC
[$FF42] = $00 ; SCY
[$FF43] = $00 ; SCX
[$FF45] = $00 ; LYC
[$FF47] = $FC ; BGP
[$FF48] = $FF ; OBP0
[$FF49] = $FF ; OBP1
[$FF4A] = $00 ; WY
[$FF4B] = $00 ; WX
[$FFFF] = $00 ; IE
Page 18 V 1.01

Game BoyTM CPU Manual 2.7.1. Power Up Sequence
It is not a good idea to assume the above values
will always exist. A later version GameBoy could
contain different values than these at reset.
Always set these registers on reset rather than
assume they are as above.
Please note that GameBoy internal RAM on power up
contains random data. All of the GameBoy emulators
tend to set all RAM to value $00 on entry.
Cart RAM the first time it is accessed on a real
GameBoy contains random data. It will only contain
known data if the GameBoy code initializes it to
some value.
2.7.2. Stop Mode
The STOP command halts the GameBoy processor
and screen until any button is pressed. The GB
and GBP screen goes white with a single dark
horizontal line. The GBC screen goes black.
2.7.3. Low-Power Mode
It is recommended that the HALT instruction be used
whenever possible to reduce power consumption & extend
the life of the batteries. This command stops the
system clock reducing the power consumption of both
the CPU and ROM.
The CPU will remain suspended until an interrupt
occurs at which point the interrupt is serviced and
then the instruction immediately following the HALT
by DP Page 19

2.7.3. Low-Power Mode Game BoyTM CPU Manual
is executed. If interrupts are disabled (DI) then
halt doesn't suspend operation but it does cause
the program counter to stop counting for one
instruction on the GB,GBP, and SGB as mentioned below.
Depending on how much CPU time is required by a game,
the HALT instruction can extend battery life anywhere
from 5 to 50% or possibly more.
WARNING: The instruction immediately following the
HALT instruction is "skipped" when interrupts are
disabled (DI) on the GB,GBP, and SGB. As a result,
always put a NOP after the HALT instruction. This
instruction skipping doesn't occur when interrupts
are enabled (EI).
This "skipping" does not seem to occur on the
GameBoy Color even in regular GB mode. ($143=$00)
EXAMPLES from Martin Korth who documented this
problem:
(assuming interrupts disabled for all examples)
1) This code causes the 'a' register to be
incremented TWICE.
76 halt
3C inc a
2) The next example is a bit more difficult.
The following code
76 halt
FA 34 12 ld a,(1234)
is effectively executed as
76 halt
Page 20 V 1.01