Nintendo DMG-01 - Game Boy Console User manual

Sources by: Pan of Anthrox, GABY, Marat Fayzullin,
Pascal Felber, Paul Robson, Martin Korth, kOOPa, Bowser
Contents:
Assembly Language Commands, Timings and Opcodes, and
everything you always wanted to know about GB but were
afraid to ask.
THIS DOCUMENT IS PRINTED ON DIN A5 SIZE PAPER
(148mm x 210mm)!
Note: Game BoyTM, Game Boy PocketTM, Super Game BoyTM and Game
Boy ColorTM are registered trademarks of Nintendo CO., LTD.
© 1989 to 1999 by Nintendo CO., LTD.
Version: 1.01 by DP
Game BoyTM
CPU Manual

1. Foreword Game BoyTM CPU Manual
Table of Contents
1. Foreword...........................................4
2. Hardware specifications............................5
2.1. Forward:.......................................5
2.2. Terms..........................................5
2.3. Game Boy Specs.................................6
2.4. Processor......................................6
2.5. Memory Map.....................................8
2.5.1. General memory map.........................8
2.5.2. Echo of 8kB Internal RAM...................9
2.5.3. User I/O...................................9
2.5.4. Reserved Memory Locations.................10
2.6. Cartridge Types...............................13
2.7. Special modi..................................17
2.7.1. Power Up Sequence.........................17
2.7.2. Stop Mode.................................19
2.7.3. Low-Power Mode............................19
2.8. Video.........................................22
2.8.1. Tiles.....................................22
2.8.2. Sprites...................................25
2.8.3. Sprite RAM Bug............................27
2.9. Sound.........................................28
2.10. Timer........................................30
2.11. Serial I/O...................................31
2.12. Interrupts...................................32
2.12.1. Interrupt Procedure......................32
2.12.2. Interrupt Descriptions...................34
2.13. Special Registers............................35
2.13.1. I/O Registers............................35
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Game BoyTM CPU Manual 1. Foreword
3. Game Boy command overview.........................61
3.1. Foreword......................................61
3.2. CPU Registers.................................61
3.2.1. Generally.................................61
3.2.2. Flag Register.............................62
3.2.3. Program Counter...........................63
3.2.4. Stack Pointer.............................63
3.3. Commands......................................65
3.3.1. 8-Bit Loads...............................65
3.3.2. 16-Bit Loads..............................76
3.3.3. 8-Bit ALU.................................80
3.3.4. 16-Bit Arithmetic.........................90
3.3.5. Miscellaneous.............................94
3.3.6. Rotates & Shifts..........................99
3.3.7. Bit Opcodes..............................108
3.3.8. Jumps....................................111
3.3.9. Calls....................................114
3.3.10. Restarts................................116
3.3.11. Returns.................................117
4. Super Game Boy commands..........................119
4.1. Foreword.....................................119
4.2. Palettes.....................................119
4.3. SGB Border...................................120
4.4. Main Action Window...........................121
4.5. Commands.....................................122
5. Appendix A.......................................134
5.1. Emulator Notes...............................134
5.2. Typical timing diagram.......................137
by DP Page 3

1. Foreword Game BoyTM CPU Manual
1. Foreword
This Document was designed to help you programming the
Game BoyTM Classic,Game BoyTM Pocket,Super Game BoyTM
and Game BoyTM Color (basics - you will need additional
documents for GBC specific programming). It was ment to
be a complete handbook to start right off coding for
the hardware. The documents consists of three major
parts.
The first is the 'GBSpec.txt' (also known as the Pan
Document) by Pan of Anthrox,Marat Fayzullin,Pascal
Felber,Paul Robson,Martin Korth,kOOPa. This will be
found in paragraph 1.
The second is a mixture of several documents from
'Game Boy Assembly Language Primer (GALP) V1.0'by GABY
(GAmeBoY). It contains opcodes, time duration and the
affected flags per ASM command and the. This can be
found in paragraph 2.
The third is a summary of specifications and commands
for Nintendo Super Game Boy speciffic programming by
kOOPa and Bowser. See paragraph 3.
Information on how to get your emulator proved
programs run on a real Game Boy can be found in the
Appendix (thanks to kOOPa). Also, a timing diagram of a
typical read and write operation on the classic GB bus
can be found here (thanks to Philippe Pouliquen).
On the last page a quick reference of ASM commands is
included.
Have fun!
DP
Page 4V 1.01

Game BoyTM CPU Manual 2. Hardware specifications
2. Hardware specifications
2.1. Forward:
The following was typed up for informational purposes
regarding the inner workings on the hand-held game
machine known as Game Boy, manufactured and designed by
Nintendo Co., LTD. This info is presented to inform a
user on how their Game Boy works and what makes it
"tick". GameBoy is copyrighted by Nintendo Co., LTD.
Any reference to copyrighted material is not presented
for monetary gain, but for educational purposes and
higher learning.
2.2. Terms
GB = Original GameBoy (GameBoy Classic)
GBP = GameBoy Pocket/GameBoy Light
GBC = GameBoy Color
SGB = Super GameBoy
by DP Page 5

2.3. Game Boy Specs Game BoyTM CPU Manual
2.3. Game Boy Specs
•CPU: 8-bit (Similar to the Z80 processor.)
•Main RAM: 8K Byte
•Video RAM: 8K Byte
•Screen Size 2.6"
•Resolution: 160x144 (20x18 tiles)
•Max # of sprites: 40
•Max # sprites/line: 10
•Max sprite size: 8x16
•Min sprite size: 8x8
•Clock Speed: 4.194304 MHz
(4.295454 SGB, 4.194/8.388MHz GBC)
•Horiz Sync: 9198 KHz (9420 KHz for SGB)
•Vert Sync: 59.73 Hz (61.17 Hz for SGB)
•Sound: 4 channels with stereo sound
•Power: DC6V 0.7W (DC3V 0.7W for GB Pocket)
Nintendo documents describe the CPU & instructions
speed in machine cycles while this document describes
them in clock cycles. Here is the translation:
1 machine cycle = 4 clock cycles
GB CPU Speed NOP Instruction
Machine Cycles 1.05MHz 1 cycle
Clock Cycles 4.19MHz 4 cycles
2.4. Processor
The GameBoy uses a computer chip similar to an Intel
8080. It contains all of the instructions of an 8080
except there are no exchange instructions. In many
ways the processor is more similar to the Zilog Z80
processor. Compared to the Z80, some instructions
Page 6V 1.01

Game BoyTM CPU Manual 2.4. Processor
have been added and some have been taken away.
The following are added instructions:
ADD SP,nn ;nn = signed byte
LDI (HL),A ;Write A to (HL) and increment HL
LDD (HL),A ;Write A to (HL) and decrement HL
LDI A,(HL) ;Write (HL) to A and increment HL
LDD A,(HL) ;Write (HL) to A and decrement HL
LD A,($FF00+nn)
LD A,($FF00+C)
LD ($FF00+nn),A
LD ($FF00+C),A
LD (nnnn),SP
LD HL,SP+nn ;nn = signed byte
STOP ;Stop processor & screen until
button press
SWAP r ;Swap high & low nibbles of r
The following instructions have been removed:
Any command that uses the IX or IY registers.
All IN/OUT instructions.
All exchange instructions.
All commands prefixed by ED (except remapped RETI).
All conditional jumps/calls/rets on parity/overflow
and sign flag.
The following instructions have different opcodes:
LD A,[nnnn]
LD [nnnn],A
RETI
by DP Page 7

2.5. Memory Map Game BoyTM CPU Manual
2.5. Memory Map
2.5.1. General memory map
Interrupt Enable Register
--------------------------- FFFF
Internal RAM
--------------------------- FF80
Empty but unusable for I/O
--------------------------- FF4C
I/O ports
--------------------------- FF00
Empty but unusable for I/O
--------------------------- FEA0
Sprite Attrib Memory (OAM)
--------------------------- FE00
Echo of 8kB Internal RAM
--------------------------- E000
8kB Internal RAM
--------------------------- C000
8kB switchable RAM bank
--------------------------- A000
8kB Video RAM
--------------------------- 8000 --
16kB switchable ROM bank |
--------------------------- 4000 |= 32kB Cartrigbe
16kB ROM bank #0 |
--------------------------- 0000 --
* NOTE: b = bit, B = byte
Page 8V 1.01

Game BoyTM CPU Manual 2.5.2. Echo of 8kB Internal RAM
2.5.2. Echo of 8kB Internal RAM
The addresses E000-FE00 appear to access the internal
RAM the same as C000-DE00. (i.e. If you write a byte to
address E000 it will appear at C000 and E000.
Similarly, writing a byte to C000 will appear at C000
and E000.)
2.5.3. User I/O
There are no empty spaces in the memory map for
implementing input ports except the switchable RAM bank
area (not an option on the Super Smart Card since it's
RAM bank is always enabled). An output only port may be
implemented anywhere between A000-FDFF. If implemented
in a RAM area care should be taken to use an area of
RAM not used for anything else. (FE00 and above can't
be used because the CPU doesn't generate an external
/WR for these locations.)
If you have a cart with an MBC1, a ROM 4Mbit or
smaller, and a RAM 8Kbyte or smaller (or no RAM) then
you can use pins 6 & 7 of the MBC1 for 2 digital output
pins for whatever purpose you wish. To use them you
must first put the MBC1 into 4MbitROM/32KbyteRAM mode
by writing 01 to 6000. The two least significant bits
you write to 4000 will then be output to these pins.
by DP Page 9

2.5.4. Reserved Memory Locations Game BoyTM CPU Manual
2.5.4. Reserved Memory Locations
0000 Restart $00 Address
(RST $00 calls this address.)
0008 Restart $08 Address
(RST $08 calls this address.)
0010 Restart $10 Address
(RST $10 calls this address.)
0018 Restart $18 Address
(RST $18 calls this address.)
0020 Restart $20 Address
(RST $20 calls this address.)
0028 Restart $28 Address
(RST $28 calls this address.)
0030 Restart $30 Address
(RST $30 calls this address.)
0038 Restart $38 Address
(RST $38 calls this address.)
0040 Vertical Blank Interrupt Start Address
0048 LCDC Status Interrupt Start Address
0050 Timer Overflow Interrupt Start Address
0058 Serial Transfer Completion Interrupt
Start Address
0060 High-to-Low of P10-P13 Interrupt
Start Address
An internal information area is located at 0100-014F in
each cartridge. It contains the following values:
0100-0103 This is the begin code execution point in a
cart. Usually there is a NOP and a JP
instruction here but not always.
Page 10 V 1.01