NS LMX2306TM User manual

LMX2306TM EVALUATION BOARD INSTRUCTIONS
LMX2306TM Evaluation Board Operating Instructions
General Description
The LMX2306TM Evaluation Board simplifies the evaluation of the LMX2306TM 550 MHz PLLatinum™ frequency
synthesizer. It enables all performance measurements, with no additional support circuitry. The board consists of a
LMX2306TM device, a VCO module and a loop filter built by discrete components. The SMA flange mount connectors
are provided for external reference input, RF output and the power & grounding connection. A cable assembly is
bundled with the evaluation board for connecting to PC through the parallel printer port. By means of MICROWIRE™
serial port emulation, the Codeloader software included can be run on PC to facilitate the LMX2306 internal register
programming for the evaluation and measurement.
Quick Start
Recommended Test Equipment
• Spectrum Analyzer
• Modulation Domain Analyzer
• DC power supply with adjustable voltage output
• Ultra low noise 10 MHz Signal Source
PLL Loop Filter Design
The table below summarizes the loop filter that is implemented on the LMX2306TM Evaluation Board. These results are
based on theoretical calculations, not measured results.
PLL LOOP FILTER DESIGN SUMMARY
Phase Margin 51.3 deg Pole Ratio T3 /T1 0.0 %
Loop Bandwidth 4.8 kHz Spur Gain
@ 50 kHz
47.9 dB
Lock Time 436 - 465 MHz to 1 kHz
tolerance in 625 µs
Spur Gain
@ 100 kHz
36.1 dB
Settings for Operation
KΦ1 mA (High Gain )
Comparison
Frequency
50 kHz
VCO Output
Frequency
435 - 465 MHz
VCO Supply 3 Volts
Other Information
VCO Used VARIL LVCO 4279U
VCO Gain 20 MHz/Volt
VCO
Kφ
680 pF
5600 pF
15 KΩOPEN
0 Ω
VCO Input
Capacitance
100 pF
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LMX2306TM EVALUATION BOARD INSTRUCTIONS
Connection and Setup
1. Connect the J2 (RF_OUT) output port to the input of a spectrum analyzer for Phase Noise and Reference Spur
measurement or the input of a modulation analyzer for Lock Time measurement.
2. Connect an oscillator reference to the J7 (OSCin) input port. It is advised to use a high quality reference source for
an accurate and low noise measurement. A 10 MHz reference is generally available from most of the spectrum
analyzer at the reference output port.
3. Plug the DB25 connector end of the cable assembly to the parallel port of the PC. Connect the other end of the
cable to the on-board 3x2 pin header JP1. Pin #1 is position towards center of PC Board. Refer to Top Layer
Layout.
4. Insure that jumpers are installed to shunt pins 1 & 2 and 3 & 4 on header JP2.
5. Connect a power supply that has been adjusted to 3 Volts to J8 (Vcc) output port. Excessive voltage will damage
the board. When board is powered up, this board should draw a little less than 9 mA. A current clamp can
optionally be set to 20 mA. If the board draws more than 20 mA, check that the board is connected properly.
6. Run the Codeloader software on the PC to facilitate device programming.
Phase Noise Measurement Using a Spectrum Analyzer
1. Use the Codeloader software to set the desired frequency and to program the LMX2306 device.
2. The spectrum analyzer is set to the desired center frequency and the span is adjusted so the appropriate offset
frequency can be viewed. Turn on Marker Noise to get phase noise in dBc/Hz. Turn ON the video averaging
feature of the spectrum analyzer for a more accurate determination of the noise level.
3. For spectrum analyzers without a Marker Noise function, phase noise is the difference between the level of the
carrier and the noise level minus 10[log (resolution bandwidth)] and is expressed dBc/Hz. The resolution bandwidth
can be read directly from the spectrum analyzer.
Reference Spur Measurement Using a Spectrum Analyzer
1. Use the Codeloader software to set the desired frequency and to program the LMX2306 device. (Please reference
the Codeloader User Manual for details.) The VCO operating frequency range is listed in the table on page 1.
2. The spectrum analyzer is set to the desired center frequency and the span is set to allow the reference sidebands
to be viewed. For example, the span can be set to 200kHz during the measurement as its loop filter design is
based on 50kHz reference frequency.
3. The spurious output is the difference between the level of the PLL tone (at the center frequency) and the level of the
reference spur (at the center frequency ± the reference frequency).
Lock Time Measurement Using a Modulation Domain Analyzer
1. Decide the maximum and minimum frequency to be switched to and from. The VCO operating frequency range is
listed in the table on page 1. Enter Burst Mode menu of Codeloader software to create a macro to program the
LMX2306 to the maximum and minimum frequency alternatively over time. Beware of putting long enough delay
between the PLL programming. (Please reference Codeloader User Manual for details.)
2. Set the center frequency of the modulation domain analyzer to be half the way from the maximum and minimum
frequency. Set the frequency span to cover the entire frequency range from maximum to minimum. Then a
switching signal should be seen on the screen.
3. The lock time is the time difference between the point the frequency starts to change and the point that the PLL
frequency settles within ± 1kHz range.
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LMX2306TM EVALUATION BOARD INSTRUCTIONS
LMX2306 Performance Measurement Result – A Typical Example
The plot on the left shows the close in
phase noise of –83.0 dBc/Hz at an
output frequency of 435 MHz. Note that
this spectrum analyzer has a “Marker
Noise” function. For spectrum
analyzers without this feature, you can
convert the noise level in dBc to
dBc/Hz by subtracting 10*log10
(Resolution Bandwidth). Since this
phase noise is very low, many
spectrum analyzers have difficulty
measuring this phase noise at such a
close offset to the carrier. They may
give more accurate measurements at
farther offsets (i.e. 1 kHz) from the
carrier. Phase Noise levels were
measured with an Agilent E4445A
Spectrum Analyzer.
Here is another plot of the phase noise.
Note that this phase noise
measurement is very close to the
measurement above. This plot is taken
at an output frequency of 465MHz.
This shows phase noise of –82.8
dBc/Hz.
The loop bandwidth is measured by
finding the offset frequency where the
noise is the same value as the close-in
noise. This is an approximation to the
true loop bandwidth and typically is
larger than the calculated value. The
measured 0 dB loop bandwidth is 7.8
kHz, yet the calculated loop bandwidth
is 4.8 kHz. The effects of Phase
Margin less than 60 degrees and VCO
Phase Noise will lengthen the observed
loop bandwidth. This plot was done at
449 MHz.
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LMX2306TM EVALUATION BOARD INSTRUCTIONS
Reference Spur Measurement Results
Measured Spur level of –74.7 dBc
at an offset frequency of 50 kHz
when the PLL is tuned to 435 MHz.
The slight amount of “cupping”
around the spur is caused by
having the loop bandwidth wide
relative to the comparison
frequency (50 kHz). Spur levels
were measured with an Agilent
E4445A Spectrum Analyzer.
Measured Spur level of better than
–75.5 dBc at an offset frequency of
50 kHz when the PLL is tuned to
449 MHz.
Measured Spur level of better than
–75.9 dBc at an offset frequency of
50 kHz when the PLL is tuned to
465 MHz. The spur level is about
the same across the band of 435
MHz to 465 MHz. This indicates
that the Charge Pump leakage
current does not change much with
the Charge Pump tuning range,
which means Spur levels should be
close to constant.
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LMX2306TM EVALUATION BOARD INSTRUCTIONS
Lock Time Measurements
This shows the positive frequency switching
waveform. The switching transition is from 435
MHz to 465 MHz. The peak time is approximately
229 µs and the overshoot is about 9 MHz. Note the
jagged edges caused by the discrete sampling
action of the phase detector. These occur with a
period of 20 µs, which corresponds to the 50 kHz
comparison frequency. These effects start to
appear when the loop bandwidth gets on the order
of 1/10th of the comparison frequency or larger.
This shows a positive lock time of 604 µs to 1 kHz
tolerance switching 435 MHz to 465 MHz. This is
lock time is slightly less than the simulated of 625
µs. The dielectric characteristic of a X7R capacitor
can increase the lock time from the theoretical lock
time.
This shows the negative frequency switching
waveform. The switching transition is from 465
MHz to 435 MHz. The peak time is approximately
93 µs and the undershoot is about 12 MHz. Note
the jagged edges caused by the discrete sampling
action of the phase detector. These occur with a
period of 20 µs, which corresponds to the 50 kHz
comparison frequency. These effects start to
appear when the loop bandwidth gets on the order
of 1/10th of the comparison frequency or larger.
This shows a negative lock time of 774 µs to 1 kHz
tolerance switching 465 MHz to 435 MHz. This is
within measurement tolerances of the simulated
value of 625 µs. How close the tuning voltage is at
435 MHz to the lower rail can effect lock time. The
dielectric characteristic of a X7R capacitor can
increase the lock time from the theoretical lock time.
Lock time can easily increase over process,
voltage, and temperature.
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LMX2306TM EVALUATION BOARD INSTRUCTIONS
Appendix A - LMX2306TM Evaluation Board Schematic Diagram
123456
A
B
C
D
6
54321
D
C
B
A
Title
Number RevisionSize
B
Date: 5-Dec-2001 Sheet of
File: C:\LMX2306TM.ddb Drawn By:
OSCin
8
Vcc1
7
Fin
6
Finb
5
GND
4
GND
3
CPo
2
FLo
1Vp 16
Vcc2 15
Fo/LD 14
LE 13
Data 12
Clock 11
CE 10
GND 9
U1
LMX2306TM
C14
1.0uF
C7
0.01uF
C15
1.0uF
C8
0.01uF
C4
100pF
C13
0.01uF
C11
0.01uF
C9
1000pF
C6
100pF
C10
1.0uF C16
100pF
CX
C2
1
J3
Vcc VCO
1
J2
RF OUT
1
J7
OSCin
1
J4
Fo/LD
1
J1
Vp
1
J8
Vcc
R12
18Ω
R13
18Ω
R8
10ΚΩ
R7
10ΚΩ
R9
22ΚΩ
R6
10ΚΩ
R17
22ΚΩ
R10
22ΚΩ
R1
10ΚΩ
R15
27Ω
R14
39Ω
R4
10Ω
R16
27Ω
R2
RX
R5
51
1 2
3 4
JP2
Power Options
1 2 3 4 5 6
JP1
uWire
Vt 1
G2
Vcc 3
G
4
Fout
5
G
6
NC
7
G8
U2
VCO
R11
22ΚΩ
C5
100pF
C3
R3
C1
R18
OPEN
LMX2306TMEBPCB 3.0
Steve Hoffman
LMX2306TM Evaluation Board
DATA
CLOCK
CE
LE
Vcc
Vcc
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LMX2306TM EVALUATION BOARD INSTRUCTIONS
Appendix B - LMX2306TM Evaluation Board Layout
Top Layer
1. JP1 Pin 1 is in lower left hand corner as shown by dot. This matches red strip on Codeloader Cable.
2. VARIL VCO is attached with the writing and square dot as shown.
Bottom Layer (As seen through the Printed Circuit board)
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LMX2306TM EVALUATION BOARD INSTRUCTIONS
Appendix C - LMX2306TM Evaluation Board - Bill of Materials
Item
# QTY Part Number Description Reference
Designators Preferred Vendor
0 7 N/A Open, No component CX, C3, RX, R18,
J1, J3, J4 N/A
1 4 C0603C103J4RAC CAP, 0.01 µF, Ceramic, 5%,
X7R, 0603 C7, C8, C11, C13 Kemet
2 4 C1206C105J8RAC CAP, 1.0 µF, Ceramic, 5%,
X7R, 1206 C10, C14, C15 Kemet
3 4 C0603C101J5GAC CAP, 100 pF, Ceramic, 5%,
NP0, 0603 C4, C5, C6, C16 Kemet
4 1 C0805C102J5GAC CAP, 1000 pF, Ceramic,
5%, NP0, 0805 C9 Kemet
5 1 C0603C681J3GAC CAP, 680 pF, Ceramic, 5%,
NP0, 0603 C1 Kemet
6 1 C0603C562J3RAC CAP, 5600 pF, Ceramic,
5%, X7R, 0603 C2 Kemet
7 1 CRCW0603000ZRT1
RES, 0 Ω, 0603 R3 Vishay
8 1 CRCW0603100JRT1
RES, 10 Ω, 5%, 0603 R4 Vishay
9 4 CRCW0603103JRT1
RES, 10.0 K Ω, 5%, 0603 R1, R6, R7, R8 Vishay
10 2 CRCW0603180JRT1
RES, 18 Ω, 5%, 0603 R12, R13 Vishay
11 4 CRCW0603223JRT1
RES, 22 K Ω, 5%, 0603 R9, R10, R11, R17 Vishay
12 1 CRCW0603510JRT1
RES, 51 Ω, 5%, 0603 R5 Vishay
13 2 CRCW0603270JRT1
RES, 27 Ω, 5%, 0603 R15, R16 Vishay
14 1 CRCW0603390JRT1
RES, 39 Ω, 5%, 0603 R14 Vishay
15 1 CRCW0603153JRT1
RES, 15 K Ω, 5%, 0603 R2 Vishay
16 1 HTSM3203-4G2 HEADER, 4 Pin JP2 Comm Con
Connectors
17 1 HTSM3203-6G2 HEADER, 6 Pin JP1 Comm Con
Connectors
18 1 LMX2306TM IC, PLL U1 National
Semiconductor
19 1 LMX2306TMEBPCB PCB National
Semiconductor
20 3 5762SF CONNECTOR, SMA, 50 ΩJ2, J7, J8 CDI
21 2 CCIJ255G SHUNT, Single, .100"
Center, Closed Top Comm Con
Connectors
22 1 LVCO 4279U VCO U2 VARIL
23 1 LMXOGTSP FRAME, 2" x 1.5" Lux
Manufacturing
24 4 OF12SHCA SCREW, 0-80x1/8 Orlander Inc
25 6 2C18PPMZZ SCREW, 2-56x3/16, Philips,
pan-head Orlander Inc
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LMX2306TM EVALUATION BOARD INSTRUCTIONS
Appendix D – How to Setup Codeloader Software
Port Setup
This allows the user to control, which
signals go to which pins on the board.
The port set up is:
Clock: 1
Data: 2
LE: 4
CE: 32
Trigger: C2
For most desktop computers, LPT1,
but LPT3 is common for many laptop
computers. Codeloader does not
auto-detect the correct port.
Bits/Pins
This allows the user to change the
value for various bits and pins. Be sure
that the CE pin (Chip Enable) is
checked, or else the PLL will be
powered down.
Main PLL Tab
This controls the output frequency of
the PLL. Be sure that the charge pump
gain and phase detector are correct, or
else the phase noise measurement will
be off.
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