ON Semiconductor KAI-2093 User manual

©Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 2 1Publication Order Number:
EVBUM2277/D
EVBUM2277/D
KAI-2093 Image Sensor
Evaluation Timing
Specification
12-bit 20 MHz AFE
Altera Code Version Description
The Altera code described in this document is intended for
use in the KSC−1000 Timing Boar. The code is developed
specifically for use with the following system configuration:
Table 1. SYSTEM CONFIGURATION
Evaluation Board Kit PN 4H0706
Timing Generator Board PN 3F5051 (AD9845A 20 MHz)
KAI−2001/KAI−2020/KAI−2093 CCD Imager Board PN 3F5121
Framegrabber Board National Instruments Model PCI−1424
The 3F5051 Timing Generator Board features the
KSC−1000 Timing Generator chip. The KSC−1000
provides all of the signals necessary for an imaging system
using Full Frame (KAF) or Interline (KAI) family of image
sensors. It also provides the signals necessary for operation
of two analog front-end (AFE) chips, enabling independent
optimization of the AFE chips for dual channel readout
devices.
ALTERA CODE FEATURES/FUNCTIONS
The Altera Programmable Logic Device (PLD) serves as
a state machine, which performs a variety of functions.
Three basic functions are required, common to all CCD
image sensor configurations: serial input steering, AFE
default programming, and KSC−1000 default
programming. In addition, certain other functions specific to
the KAI−2093 Image Sensor are implemented.
Serial Input Steering
The 3-wire serial interface enters the Timing Board
through the DIO Interface connector, and is routed to the
PLD. The Altera PLD decodes the addressing of the serial
input, and steers the datastream to the correct device.
The serial input must be formatted so that the Altera PLD
can correctly decode and steer the data to the correct device.
The serial interface can be used to dynamically change the
operating conditions of the AFE or KSC−1000 chips by
reprogramming the appropriate registers. Reprogramming
these registers through the serial interface will have no effect
on the default settings that are automatically programmed
into these devices on power-up or board reset.
Table 2. SERIAL INPUT DEVICE SELECT
Device Select DS[2..0] Serial Device
000 PLD
001 AFE1
010 AFE2
011 KSC−1000
100 (Not Used)
101 (Not Used)
110 (Not Used)
111 (Not Used)
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Figure 1. Serial Input Timing
SLOAD_INPUT
SDATA_INPUT
SCLK_INPUT
DS2 DS1 DS0 R/W A0 A1 A2 A3 (or Test) D0 D1 D2 D3 D4 Dn
…
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
(decoded PLD output)
SLOAD_xxx
The first 3 bits in the datastream are the Device Select bits
DS[2..0], sent MSB first, as shown in Figure 1. The Device
Select bits are decoded as shown in Table 2.
The next bit in the datastream is the Read/Write bit (R/W).
Only writing is supported; therefore this bit is always LOW.
The definition of next four bits in the datastream depends
on the device being addressed with the Device Select bits.
For the KSC−1000 device, they are Register address bits
A[0..3], LSB first. For the AD9845A AFE, they are Register
Address bits A[0..2], LSB first, followed by a Test bit which
is always set LOW.
The remaining bits in the bitstream are Data bits, LSB
first, with as many bits as are required to fill the appropriate
register.
AFE Default Initialization
Upon power up, or when the BOARD_RESET button is
pressed, the PLD programs the registers of the two AFE
chips on the Timing Generator Board to their default settings
via the 3-wire serial interface. See Table 9 for details.
The AD9845A AFE must be reprogrammed on power-up,
as it does not retain register settings when power is removed.
Figure 2. AFE Initialization Timing
R/W A0 A1 A2 Test D0 D1 D3 D4
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
SLOAD_AFE_x
SDATA
SCLK
D5 D6 D7 D8 D9 D10 D2
The data for each AFE register is formatted into two bytes
of data, as shown in Figure . The Read/Write bit is always
low, and the Address bits specify the register being
programmed, as shown in Table 9. Each byte is read into an
8-bit shift register, and is shifted out as a serial stream of
eight bits. Each register in the AFE is programmed in this
fashion until the entire AFE is programmed.
KSC−1000 Default Initialization
Upon power-up, or when the BOARD_RESET button is
pressed, the Altera PLD programs the registers of the
KSC−1000 chip on the AFE Timing Generator Board to
their default settings via the 3-wire serial interface.
The default settings are selected by the user through the PLD
inputs SW[7..0] and DIO[15..0] (See Table 10 through
Table 24 for details). The KSC−1000 must be
reprogrammed on power-up, as it does not retain register
settings when power is removed.
The KSC−1000 default settings automatically
programmed by the PLD allow the Evaluation Board Kit
user to operate the CCD image sensor with minimal
intervention and no programming. The default settings are
chosen to comply with the CCD device specification (See
References). The registers, line tables and frame tables
described in this document also serve as examples for those
who wish to create their own KSC−1000 timing.

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Figure 3. KSC−1000 Initialization Timing
R/W A0 A1 A2 A3 D0 D1 D2
SLOAD_TG
SDATA
SCLK
ÏÏ
ÏÏ
ÏÏ
Ï
Ï
Ï
ÏÏ
ÏÏ
ÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
Dn
…
[Dummy Bits]
The data for each KSC−1000 register is formatted into
bytes of data, as shown in Figure 3. The Read/Write bit is
always low, and the Address bits specify the register being
programmed, as shown in Table 3. Each byte is read into an
8-bit shift register, and is shifted out of the PLD as a serial
stream of eight bits. The last byte of data sent to a particular
register may need to be padded with extra “dummy” bits;
the SLOAD_TG signal is brought HIGH at the appropriate
time so that the correct number of bits are streamed into each
register, and the extra bits are ignored. Each register in the
KSC−1000 is programmed in this fashion until the entire
device is programmed.
Table 3. KSC−1000 REGISTERS
Register Address Register Description Data Bits
0Frame Table Pointer 3
1General Setup 202
2General Control 2
3INTG_STRT Setup 30
4INTG_STRT Line 13
5Signal Polarity 25
6 Offset 78
7 Width 65
8Frame Table Access (Variable)
9Line Table Access (Variable)
PLD State Machine
The Altera PLD contains a State Machine that parallels
the operation of the KSC−1000. The PLD controls the
KSC−1000 through the VD_TG output, and monitors
several of the KSC−1000 outputs, enabling it to track and
control the operation of the Timing Generator.
Remote Board Reset
The DIO14 input is used as a remote Board Reset control
line. The Altera PLD monitors this input, and when DIO14
goes HIGH, the ARSTZ (active low) output to the
KSC−1000 is asserted, disabling and clearing the timing
generator. When DIO14 goes LOW, the ARSTZ output is
de-asserted, and the Power-up/Board Reset initialization
sequence is executed. This allows programmable control of
the timing sequences to change the Electronic Shutter
position, for example.
Integration Clock
The Altera PLD uses the System Clock and an internal
counter to generate a1.0 ms-period clock. This clock is used
to generate an internal delay after power-up or Board Reset.
It may also be used to control precise integration times for
the image sensor.
Output Channel Control
PLD input SW0 is used to select one of the supported
operation modes: Full Field Single Output, and Full Field
Dual Output. When making a change to the switch settings,
the user must initiate a Board Reset for the change to take

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effect, either by pressing the BOARD_RESET button (S1)
on the Timing Board, or by setting and resetting the Remote
Reset (DIO14) input.
Integration & Electronic Shutter Control
In the Full Field Timing Modes, PLD inputs DIO[11..7]
may be used to select the integration time. See Table 25 for
timing details. In general, when making a change to the
DIO[11..7] settings, the user must initiate a Board Reset for
the change to take effect, either by pressing the
BOARD_RESET button (S1) on the Timing Board, or by
setting and resetting the Remote Reset (DIO14) input.
Binning Control
PLD input SW2 is used to select between 2×2 Binning
Single Output, and normal operation (no binning). When
making a change to the switch settings, the user must initiate
a Board Reset for the change to take effect, either by pressing
the BOARD_RESET button (S1) on the Timing Board, or
by setting and resetting the Remote Reset (DIO14) input.
Video Mux Switch
The PLD input SW6 controls the Video Mux Switch,
which steers either CCD output VoutL or VoutR to the
auxiliary video output connector J1.
ALTERA CODE I/O
Inputs
The Altera PLD has multiple inputs that may be used to
control certain functions. The inputs include: user selectable
switches SW[7..0] on the Timing Board; remote digital
inputs DIO[15..0] and a 3-wire serial interface through
Timing Board connector J7; Timing Board signals;
and various outputs from the KSC−1000 Timing Generator.
The KSC−1000 outputs are monitored by the PLD to control
auxiliary timing functions, and keep the KSC−1000 and
Altera PLD synchronized. The remote digital inputs
DIO[15..0] are optional, and are not required for KAI−2093
operation, but may be used to control integration time and
remote triggering.
Table 4. ALTERA INPUTS
Symbol Description
POWER_ON_DELAY The Rising Edge of this Signal Clears and Re-initializes the PLD
SYSTEM_CLK 40 MHz Clock, 2X the Desired Pixel Clock Rate
PIXCLK NI1424 20 MHz Pixel Rate Clock from the KSC1000TG (Not Used)
SW0 HIGH = Dual Output, Full Image, LOW = Single Output, Full Image
SW1 (Not Used, Must be LOW)
SW2 Binning Mode: HIGH = 2 x 2 Binning, Single Output, LOW = No Binning
SW3 (Not Used)
SW4 (Not Used)
SW5 (Not Used)
SW6 Video Mux Switch Control: HIGH = VoutR, LOW = VoutL
SW7 (Not Used)
DIO[6..0] (Not Used)
DIO[11..7] Integration Control (See Table 24)
DIO12 (Not Used)
DIO13 (Not Used)
DIO14 Remote Board Reset (HIGH Activates ARSTZ, Falling Edge Activates BOARD_RESET)
SLOAD_INPUT 3-wire Serial Interface LOAD Signal Input
SDATA_INPUT 3-wire Serial Interface DATA Signal Input
SCLOCK_INPUT 3-wire Serial Interface CLOCK Signal Input
LINE_VALID Used to Monitor KSC−1000
FRAME_VALID Used to Monitor KSC−1000
AUX_SHUT (Not Used for KAI−2093 Operation)
INTG_START Used to Monitor KSC−1000

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Outputs
The Altera PLD outputs include: the 3-wire serial
interface; control signals to the KSC−1000;
the INTEGRATE signal used for external monitoring and
synchronization; the PLD[2..0] signals which are auxiliary
Imager Board control bits; and the GIO[2..0] bits which are
used for PLD monitoring and testing.
Table 5. ALTERA OUTPUTS
Symbol Description
PLD_OUT0 KAI−2093 Video MUX Control
PLD_OUT1 (Not Used for KAI−2093 Operation)
PLD_OUT2 (Not Used for KAI−2093 Operation)
GIO[2..0] (Not Used for KAI−2093 Operation)
SLOAD_AFE_1 Serial Load Enable, Ch1 AD9845A AFE
SLOAD_AFE_2 Serial Load Enable, Ch2 AD9845A AFE
SLOAD_TG Serial Load Enable, KSC−1000
SDATA 3-wire Serial Interface DATA Signal Output
SCLOCK 3-wire Serial Interface CLOCK Signal Output
INTEGRATE High During CCD Integration Time
HD_TG (Not Used for KAI−2093 Operation)
VD_TG Control Signal to KSC−1000
ARSTZ Asynchronous Reset to KSC−1000 (from DIO14)
KAI−2093 TIMING CONDITIONS
System Timing Conditions
Table 6. SYSTEM TIMING
Description Symbol Time Notes
System Clock Period Tsys 25.0 ns 40 MHz System Clock
Unit Integration Time Uint 1.0 ms Generated by PLD
Power Stable Delay Tpwr 100 ms Typical
Default Serial Load Time Tsload 2.06 ms Typical
Integration Time Tint Operating Mode Dependent
CCD Timing Conditions
Table 7. CCD TIMING
Description Symbol Time Pixel
Counts Notes
H1, H2, RESET Period Tpix 50.0 ns 1 20 MHz Clocking of H1, H2, RESET
VCCD Delay TVD 50.0 ns 1 Delay after Hclks Stop
VCCD Transfer Time TVCCD 1.75 ms35 V2 Rising Edge to V2 Falling Edge
HCCD Delay THD 1.55 ms31 Delay before Hclks Resume
Vertical Transfer Period Vperiod 3.35 ms67 Vperiod = TVD + TVCCD +THD
Horizontal Pixels HPIX 100.80 ms2016 1992 CCD Pixels + 24 Overclock Pixels
Vertical Pixels VPIX 1220 1214 CCD Lines + 6 Overclock Lines
Line Transfer Time TL104.15 ms2083 TL = Vperiod + HPIX

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Table 7. CCD TIMING (continued)
Description Notes
Pixel
Counts
TimeSymbol
VCCS Pedestal Time T3P 25.05 ms501
Photodiode Transfer Time TV3rd 12.30 ms246 V2 3rd Level
Photodiode Delay T3D 20.00 ms400
Photodiode Frame Delay T3FD 85.50 ms1710 Delay before 1st Line Transfer
Photodiode Transfer Period T3PT142.85 ms2857 T3PT = T3P + TV3rd + T3D + T3FD
Shutter Pulse Setup TEL 1.50 ms30
Shutter Pulse Time TS10.0 ms200
Shutter Pulse Delay TSD 1.50 ms30
PCI−1424 Timing Conditions
Table 8. PCI−1424 TIMING
Description Symbol Time Pixel
Counts Notes
PIX Period TPIX 50.0 ns 1 20 MHz Clocking of DATACLK Sync Signal
FRAME Time TFRAME 127.2 ms 2,544,117 TFRAME = TPIX * ((Vperiod + HPIX) * VPIX + T3PT)
MODES OF OPERATION
The following modes of operation are available to the
user:
Electronic Shutter Modes
The Evaluation Board electronic shutter circuitry
provides a method of precisely controlling the image
exposure time without any mechanical components. Charge
may be cleared from the CCD photodiodes at some time
during the readout of the previous frame. This allows
integration times of less than one frame time, to compensate
for high light exposures that would otherwise saturate the
CCD.
In Free-Running Mode, the default integration time can be
set from 1×to 1/8×frame time via the digital inputs
DIO[11..7] (See Table 14 and Table 25). When changing the
integration time, the user must initiate a Board Reset for the
change to take effect, either by pressing the
BOARD_RESET button (S1) on the Timing Board, or by
setting and resetting the Remote Reset (DIO14) input.
Black Clamp Mode
One of the features of the AD9845A AFE chip is an
optical black clamp. The black clamp (CLPOB) is asserted
during the CCD’s dark pixels and is used to remove residual
offsets in the signal chain, and to track low frequency
variations in the CCD’s black level. The location of these
pulses is fixed in the default KSC−1000 settings, but can be
adjusted dynamically through the 3-wire serial interface.
The default settings are shown in Table 11.
POWER-ON/BOARD RESET INITIALIZATION
When the board is powered up, the Board Reset button is
pressed, or the Remote Rest (DIO14) is toggled, the Altera
PLD is internally reset. When this occurs, state machines in
the PLD will first serially load the initial default values into
the AFE registers, then will load the KSC−1000 frame
tables, line tables, and registers.
Upon completion, the KSC−1000 will be ready to proceed
according to its programmed configuration. In the
background, the Altera PLD monitors the activity of the
3-wire Serial Interface, and monitors and interacts with the
KSC−1000.
AFE Register Default Settings
On power-up or board reset, the AFE registers are
programmed to the default levels shown in Table 9. See the
AD9845A specifications (References) for details of the
AFE registers.

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Table 9. DEFAULT AD9845A AFE REGISTER PROGRAMMING
Register
Address Description Value (decimal) Notes
0 Operation 128
1VGA Gain
(KAI−2093) 340 Corresponds to a VGA Stage Gain of 9.9 dB
2 Clamp 96 The Output of the AD9845A will be Clamped to Code 96 during the CLPOB Period
3 Control 8 CDS Gain Enabled
4, 5, 6, 7 PXGA Gain 43 Corresponds to a PXGA Stage Gain of 0.0 dB
KSC−1000 Timing Generator Default Settings
On power-up or board reset, The KSC−1000 is
programmed to the default settings as detailed in Table 10
through Table 24. See the KSC−1000 Device Specification
(References) for details of the KSC−1000 registers.
Register 0: Frame Table Pointer
Register 0 contains the Frame Table Pointer, which
instructs the KSC−1000 to perform the timing sequence
defined in that table. Frame Table 0 is used for Free-Running
Single Channel and Dual Channel modes, and Frame
Table 1 is used for Single Channel 2×2 Binning mode.
The default setting depends on the position of SW2.
Table 10. REGISTER 0 DEFAULT SETTING
Register Entry Data (Normal Mode) Data (Binning 2y2)
Frame Table Address 0 1
Register 1: General Setup
The default settings written to Register 1 depend on the
position of SW0 on the Timing Board, used to select
between 1-channel and 2-channel operation.
Table 11. REGISTER 1 DEFAULT SETTING
Register Entry Data (1-channel) Data (2-channel)
Pixels Per Line[0..12] 2016 1008
Line Valid Pixel Start[0..12] 9 9
Line Valid Pixel Quadrature Start[0..1] 0 0
Line Valid Pixel End[0..12] 2004 1007
CLPOB1_Pix_Start[0..12] 1982 1000
CLPOB1_Pix_End[0..12] 1992 1004
CLPOB2_Pix_Start[0..12] 0 0
CLPOB2_Pix_End[0..12] 0 0
CLPDM1_Pix_Start[0..12] 6 22
CLPDM1_Pix_End[0..12] 16 30
CLPDM2_Pix_Start[0..12] 0 0
CLPDM2_Pix_End[0..12] 0 0
PBLK_Pix_Start[0..12] 2002 1001
PBLK_Pix_End[0..12] 1 1
RG_Enable 1 1
H6_Enable 0 0
H4_Enable 1 1
H5_ Enable 0 0
SH2_Enable 1 1
SH4_Enable 1 1

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Table 11. REGISTER 1 DEFAULT SETTING (continued)
Register Entry Data (2-channel)Data (1-channel)
DATACLK1_Enable 1 1
DATACLK2_Enable 1 1
PIXCLK_Enable 1 1
H3_Enable 1 1
H1_Enable 1 1
H2_Enable 1 1
SH1_Enable 1 1
SH3_Enable 1 1
H6 24 mA Output Enable 0 0
H4 24 mA Output Enable 0 0
H5 24 mA Output Enable 0 0
RG 24 mA Output Enable 0 0
SH2 24 mA Output Enable 0 0
SH4 24 mA Output Enable 0 0
DATACLK1 24 mA Output Enable 0 0
DATACLK2 24 mA Output Enable 0 0
H3 24 mA Output Enable 0 0
H1 24 mA Output Enable 0 0
H2 24 mA Output Enable 0 0
SH1 24 mA Output Enable 0 0
SH3 24 mA Output Enable 0 0
DLL Frequency Range Select 8 8
Register 2: General Control
Register 2 controls the Power Management and
Operation state of the KSC−1000. The Low Power Mode is
not used on the KAI−2093, so this bit is always LOW.
The Memory Table Mode bit is used to halt execution of the
KSC−1000 timing sequences and to enable programming of
the registers. The KSC−1000 Initialization sequence begins
with setting the Memory Table Mode bit in Register 2 to
Program Mode, and ends by setting the bit to Execution
Mode. See the KSC−1000 Device Specification
(References) for more details.
Table 12. REGISTER 2 SETTINGS
Register Entry Program Mode Execution Mode
Low Power Enable 0 0
Memory Table Mode 0 1
Register 3: INTG_START Setup
The default settings written to Register 3 establish the
setup, pulsewidth, and hold timing of the Electronic Shutter
pulse. The Shutter Pulse may occur on a particular line, as
controlled by Register 4, or may be asserted by setting the
“Force INTG_STRT” bit in the Frame Table (Register 8). In
either case, the Electronic Shutter Pulse occurs before the
vertical clocking interval of the Frame Table entry
(Figure 12).
Table 13. REGISTER 3 DEFAULT SETTING
Register Entry Data
Electronic Shutter Setup Clocks[0..9] 30
Electronic Shutter Pulse Width[0..9] 200
Electronic Shutter Hold Clocks[0..9] 30

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Register 4: INTG_START Line
Short integration times may be controlled through use of
the Electronic Shutter. The default setting written to
Register 4 controls the line number on which the Electronic
Shutter will occur. The DIO[11..7] inputs are used to control
the Integration time, by selecting pre-programmed line
numbers, as shown in Table 14.
In Free-Running Mode, the Electronic Shutter pulse
occurs during the previous frame readout. The line number
values are chosen to allow integration times adjustable in
increments of one-eighth the Frame or Flush time.
If the line number is greater than the number of lines
specified in a Frame Table (Register 8), the Electronic
Shutter will not occur. This is the method used to turn the
Shutter off; in this case, the integration time is controlled by
a counter in the Altera PLD (See Table 25).
Table 14. REGISTER 4 DEFAULT SETTING
DIO[11..7] Frame/Flush Integration Free-Running Mode
Integrate Start Pulse Line Number[0..12]
0 1 2040 (Default – No Pulse)
1 1/8 966
2 1/4 828
3 3/8 690
4 1/2 552
5 5/8 414
6 3/4 276
7 7/8 138
> 7 See Table 25 2040 (No Pulse)
Register 5: Signal Polarity
The default settings written to Register 5 depend on the
position of SW0 on the Timing Board, used to select
between 1-channel and 2-channel operation.
Table 15. REGISTER 5 DEFAULT SETTING
Register Entry 1-channel 2-channel Evaluation Board Signal Name
H6_IDLE_VAL 0 0 (Not Used)
H3_IDLE_VAL 1 1 H1A
H4_IDLE_VAL 0 0 H2A
H1_IDLE_VAL 1 0 H2B
H5_IDLE_VAL 0 0 (Not Used)
H2_IDLE_VAL 0 1 H1B
RG_IDLE_VAL 1 1 RESET
SH2_IDLE_VAL 1 1 SHP1
SH1_IDLE_VAL 1 1 SHP2
SH4_IDLE_VAL 1 1 SHD1
SH3_IDLE_VAL 1 1 SHD2
DATACLK1_IDLE_VAL 1 1 ADCLK (to AFEs)
DATACLK2_IDLE_VAL 0 0 DATACLK (to Framegrabber)
CLPOB_IDLE_VAL 1 1 CLPOB
CLPDM_IDLE_VAL 1 1 CLPDM
AMP_ENABLE_IDLE_VAL 0 0 AMP_ENABLE
FRAME_VALID_IDLE_VAL 0 0 FRAME_VALID
LINE_VALID_IDLE_VAL 0 0 LINE_VALID
INTEGRATE_START_IDLE_VAL 0 0 INTG_START/VES
V1_IDLE_VAL 0 0 V3RD
V2_IDLE_VAL 0 0 (Not Used)

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Table 15. REGISTER 5 DEFAULT SETTING (continued)
Register Entry Evaluation Board Signal Name2-channel1-channel
V3_IDLE_VAL 0 0 V2
V4_IDLE_VAL 1 1 V1
V5_IDLE_VAL 0 0 (Not Used)
V6_IDLE_VAL 0 0 FDG
Register 6: Pixel-Rate Signal Offset
The default settings written to Register 6 depend on the
position of SW0 on the Timing Board, used to select
between 1-channel and 2-channel operation.
Table 16. REGISTER 6 DEFAULT SETTING
Register Entry Data
(1-channel) Data (2-channel) CCD Signal Name
H6_OFFSET[0..5] 0 0 (Not Used)
H3_OFFSET[0..5] 32 32 H1A
H4_OFFSET[0..5] 29 29 H2A
H1_OFFSET[0..5] 33 31 H2B
H5_OFFSET[0..5] 0 0 (Not Used)
H2_OFFSET[0..5] 31 33 H1B
RG_OFFSET[0..5] 0 0 RESET
SH2_OFFSET[0..5] 31 31 SHP1
SH1_OFFSET[0..5] 31 31 SHP2
SH4_OFFSET[0..5] 63 63 SHD1
SH3_OFFSET[0..5] 63 63 SHD2
DATACLK1_OFFSET[0..5] 42 42 ADCLK (to AFEs)
DATACLK2_OFFSET[0..5] 0 0 DATACLK (to Framegrabber)
Register 7: Pixel-Rate Signal Width
The default settings written to Register 7 depend on the
position of SW0 on the Timing Board, used to select
between 1-Channel and 2-Channel operation.
Table 17. REGISTER 7 DEFAULT SETTING
Register Entry Data
(1-channel) Data (2-channel) CCD Signal Name
H6_WIDTH[0..4] 16 16 (Not Used)
H3_WIDTH[0..4] 13 13 H1A
H4_WIDTH[0..4] 18 18 H2A
H1_WIDTH[0..4] 13 18 H2B
H5_WIDTH[0..4] 16 16 (Not Used)
H2_WIDTH[0..4] 18 14 H1B
RG_WIDTH[0..4] 8 8 RESET
SH2_WIDTH[0..4] 14 14 SHP1
SH1_WIDTH[0..4] 14 14 SHP2
SH4_WIDTH[0..4] 14 14 SHD1
SH3_WIDTH[0..4] 14 14 SHD2
DATACLK1_WIDTH[0..4] 31 31 ADCLK (to AFEs)
DATACLK2_WIDTH[0..4] 16 16 DATACLK (to Framegrabber)

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Register 8: Frame Tables
Several Frame Tables are written by default to the
KSC−1000 Frame Table registers, but only one Frame Table
is active at one time, as determined by the Frame Table
Pointer (Register 0). Frame Table 0 is used for
Free-Running Single Channel and Dual Channel modes, and
Frame Table 1 is used for Single Channel 2×2 Binning
mode. Note that the last row in Table 18 and Table 19 are the
mnemonics associated with the Flag, Count, and Address
bits. See the KSC−1000 Device Specification (References)
for more details.
Table 18. FRAME TABLE 0 DEFAULT SETTING
Bit Location Frame Table Data
FT0 Entry
0 1 2 3
0Check and Increment Line Counter 1 0 0 0
1Clear Line Counter 0 1 1 1
2Force INTG_STRT 0 0 0 0
3:4 Horizontal Binning Factor 0 0 0 0
5HCLK_V Enable 0 0 0 0
6LINE_VALID Enable 1 0 0 0
7FRAME_VALID Enable 1 0 0 0
8Video Amplifier Enable 0 0 0 0
9AFE Clock Enable 1 1 1 1
10 CLPDM2 Enable 0 0 0 0
11 CLPDM1 Enable 1 0 0 0
12 CLPOB2 Enable 0 0 0 0
13 CLPOB1 Enable 1 0 0 0
14 PBLK Enable 1 0 0 0
15 Pblk_Idle_Val 1 1 1 1
16 Flag 0 1 0 0
17:29 Count 1104 0 1 0
30:32 Address 2:0 0 4 1 0
33 Address 3 0 0 0 0
− Mnemonic ELT0 ExLTNVD 4 ELT 1 JMPFT 0
Table 19. FRAME TABLE 1 DEFAULT SETTING
Bit Location Frame Table Data
FT1 Entry
0 1 2 3
0Check and Increment Line Counter 1 0 0 0
1Clear Line Counter 0 1 1 1
2Force INTG_STRT 0 0 0 0
3:4 Horizontal Binning Factor 1 0 0 0
5HCLK_V Enable 0 1 0 0
6LINE_VALID Enable 1 0 0 0
7FRAME_VALID Enable 1 0 0 0
8Video Amplifier Enable 0 0 0 0
9AFE Clock Enable 1 1 1 1
10 CLPDM2 Enable 0 0 0 0
11 CLPDM1 Enable 1 0 0 0
12 CLPOB2 Enable 0 0 0 0

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Table 19. FRAME TABLE 1 DEFAULT SETTING (continued)
Bit Location
FT1 Entry
Frame Table Data
Bit Location 3210 Frame Table Data
13 CLPOB1 Enable 1 0 0 0
14 PBLK Enable 1 0 0 0
15 Pblk_Idle_Val 1 1 1 1
16 Flag 0 1 0 0
17:29 Count 552 0 1 0
30:32 Address 2:0 3 2 1 1
33 Address 3 0 0 0 0
− Mnemonic ELT0 ExLTNVD 5 ELT 1 JMPFT 1
Register 9: Line Tables
There are five Line Tables written by default to the
KSC−1000 Line Table registers. Line Table 0 is the normal
Line Transfer sequence. See Figure 4.
Table 20. LINE TABLE 0 DEFAULT SETTING
CCD Signal Line Table Data Name
LT0 Entry
0123456
Count[0..12] 1 3 30 2 30 1 0
HCLK_H Enable 0000010
FDG V6 0 0 0 0 0 0 0
V5 0 0 0 0 0 0 0
V1 V4 0 0 1 0 0 0 0
V2 V3 0 1 1 1 0 0 0
V2 0 0 0 0 0 0 0
V3RD V1 0 0 0 0 0 0 0
Line Table 1 is the normal Photodiode Transfer sequence
that transfers charge from all the photodiodes to the vertical
registers. See Figure 5.
Table 21. LINE TABLE 1 DEFAULT SETTING
CCD Signal Line Table Data Name
LT1 Entry
01234567
Count[0..12] 1 500 6 240 1 400 1310 0
HCLK_H Enable 00000000
FDG V6 0 0 0 0 0 0 0 0
V5 0 0 0 0 0 0 0 0
V1 V4 0 0 0 1 0 0 0 0
V2 V3 0 1 1 1 1 1 0 0
V2 0 0 0 0 0 0 0 0
V3RD V1 0 0 1 1 1 0 0 0

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Line Table 2 is the Integration sequence. The vertical
clocks are not active, and the Horizontal register is
continually flushed of charge. See Figure 6.
Table 22. LINE TABLE 2 DEFAULT SETTING
CCD Signal Line Table Data Name
LT2 Entry
0 1
Count[0..12] 1 0
HCLK_H Enable 1 0
FDG V6 0 0
V5 0 0
V1 V4 0 0
V2 V3 0 0
V2 0 0
V3RD V1 0 0
Line Table 3 is the Binning Mode Line Transfer sequence.
Two V1 and V2 pulses occur during each Vertical clocking interval, followed by Horizontal Register readout. See Figure 7.
Table 23. LINE TABLE 3 DEFAULT SETTING
CCD Signal Line Table Data Name
LT3 Entry
0 1 2 3 4 5 6 7 8 9
Count[0..12] 1 1 30 1 30 1 30 1 30 0
HCLK_H Enable 0000000010
FDG V6 0000000000
V5 0000000000
V1 V4 0010001000
V2 V3 0111011100
V2 0000000000
V3RD V1 0 0 0 0 0 0 0 0 0 0
Line Table 4 is an Integration sequence. Neither the
Vertical clocks nor the Horizontal clocks are active. See
Figure 8.
Table 24. LINE TABLE 4 DEFAULT SETTING
CCD Signal Line Table Data Name
LT4 Entry
0 1
Count[0..12] 1 0
HCLK_H Enable 0 0
FDG V6 0 0
V5 0 0
V1 V4 0 0
V2 V3 0 0
V2 0 0
V3RD V1 0 0

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KAI−2093 TIMING
Line Table 0 (Line Transfer)
Line Table 0 is the Line Transfer timing sequence that
transfers one entire row of charge toward the horizontal
register. V1 and V2 are asserted, with overlap adjustability
to compensate for the clock driver rise and fall times. Charge
is moved down the vertical CCD registers, and the last row
of charge is dumped into the horizontal register. The VCCD
clocking interval is followed by the Horizontal clocks,
which shift one line out through the output amplifier(s).
Figure 4. Line Table 0 Default Timing
LT0 Entry
V1_CCD
V2_CCD
0 1 2 3 5
1 3 30 2 130Pix Counts
(not to scale)
HCLK_ENABLE
VLOW
VMID
VLOW
VMID
H1A_CCD
H2A_CCD
4
TVD TVCCD THD
Symbol
Line Table 1 (Diode Transfer)
Line Table 1 is the Photodiode Transfer timing, in which
the V2 clock 3rd-level shifts charge from all the photodiodes
into the vertical CCD registers. The V1 and V2 clocks have
overlap adjustability to compensate for the clock driver rise
and fall times.
Figure 5. Line Table 1 Default Timing
LT1 Entry
V1_CCD
V2_CCD
0 1 2 3 4 5 6
1 500 6 240 1 400 1310Pix Counts
(not to scale)
HCLK_ENABLE
VLOW
VLOW
VMID
VMID
VHIGH
H1A_CCD
H2A_CCD
T3P TV3rd T3D T3FD
Symbol

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Line Table 2 (Integration)
Line Table 2 is the Integration timing sequence, during
which the Vertical clocks are inactive and the Horizontal
clocks are running continuously. This sequence runs until
Integration is complete, signaled by the assertion of the
VD_TG signal from the Altera PLD.
Figure 6. Line Table 2 Default Timing
LT2 Entry
V1_CCD
V2_CCD
0
1
Pix Counts
(not to scale)
HCLK_ENABLE
(Vclks not active)
VLOW
VMID
H1A_CCD
H2A_CCD
Line Table 3 (Binning Mode Line Transfer)
Line Table 3 is the Binning Mode Line Transfer sequence,
during which the Vertical clocks are asserted twice per line.
This effectively sums two pixels’ worth of charge into each
Horizontal CCD pixel. After the binning line transfer,
the Horizontal clocks are run in Binning Mode.
Figure 7. Line Table 3 Default Timing
LT3 Entry
V1_CCD
V2_CCD
0 1 2 3 8
1 1 30 1 3030
Pix Counts
HCLK_ENABLE
VLOW
VMID
VLOW
VMID
H1A_CCD
H2A_CCD
6
THTVCCD THD
Symbol
4 5
30 1
TVCCD
7
1
TVCCD
(not to scale)
Line Table 4 (Trigger Hold)
Line Table 4 is a sequence one pixel time in length, used
when the KSC−1000 is waiting to be triggered by the Altera PLD. Neither the Vertical clocks nor the Horizontal Clocks are active during this sequence.
Figure 8. Line Table 4 Default Timing
LT4 Entry
V1_CCD
V2_CCD
0
1
Pix Counts
HCLK_ENABLE
(Vclks not active)
VLOW
VMID
H1A_CCD
H2A_CCD (Hclks not active)
HLOW
HMID
(LOW)
(not to scale)

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Frame Table 0 Sequence
Frame Table 0 contains the Free-Running (video mode)
timing sequence used to continuously read out all rows of the
CCD. The sequence begins with the Line Transfer sequence,
followed by the Timed Integration sequence. When
integration is complete, the Altera PLD asserts the VD_TG
signal to the KSC−1000. This initiates the Photodiode
transfer, and the cycle repeats with the next Line Transfer
sequence.
Execute LT1
(DIODE XFR)
Count = 1
DIO[11..7] =
{1,2,...7}?
Set INTEGRATE
Wait for INT ctr
Execute LT0
(LINE XFR)
Count = 1214
Wait for
FRAME_VALID
(falling edge)
Execute LT5
Wait for VD_TG
Issue VD_TG
Reset INTEGRATE
VD_TG
INTG_START
Shutter?
Issue
INTG_START
Set INTEGRATE
on INTG_START
(falling edge)
Wait for FRAME_VALID
(rising edge)
Altera PLD KSC−1000TG
No
Yes
State Machine Sequence Frame Table 0 Sequence
FRAME_VALID
V_TRANSFER
TIMED_
INTEGRATION
DIODE_
TRANSFER
ENTRY 0
ENTRY 1
ENTRY 2
ENTRY 3
Jump to FT0 Entry 0
Count = 1
FRAME_VALID
Figure 9. Free-Running Mode Timing Sequence

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Figure 10. Frame Table 0 Default Timing
V1_CCD
V2_CCD
H1A_CCD
H2A_CCD
PBLK
VD_TG
FRAME_VALID
LINE_VALID
FT0 Entry 2
01
0
Line Table 1
1104
Counts
1
4
x
CLPOB1
(not to scale)
INTEGRATE
DIODE_TRANSFER
V_TRANSFER
PLD STATE TIMED_INTEGRATION
Frame Table 1 Sequence
Frame Table 1 contains the 2×2 Binning Mode timing
sequence used to sum the charge collected in four photosites
into one CCD pixel. The sequence is identical to that of
Frame Table 0, except that the Vertical Clocks are asserted
twice per line, which dumps charge from two vertical CCD
pixels into each Horizontal register CCD pixel.
Figure 11. Frame Table 1 Default Timing
V1_CCD
V2_CCD
H1A_CCD
H2A_CCD
PBLK
VD_TG
FRAME_VALID
LINE_VALID
FT1 Entry 2
01
0
Line Table 1
610
Counts
1
5
x
CLPOB1
(not to scale)
INTEGRATE
DIODE_TRANSFER
V_TRANSFER
PLD STATE TIMED_INTEGRATION
Electronic Shutter Timing
The electronic shutter timing is controlled by the values in
Register 3 of the KSC−1000. There are two methods of
actuating the Electronic Shutter pulse: by setting the
Integrate Start Pulse Line Number value in Register 4 so
that the pulse occurs on a specific line, or by setting the
Force INTG_START bit in a Frame Table entry. In either
case, the Electronic Shutter pulse setup, width, and hold
times are determined by the values in Register 3. The shutter
sequence is inserted before the specified line, causing that
particular line time to be extended accordingly.
If the Integrate Start Pulse Line Number value in
Register 4 is set to 0, the Electronic Shutter will occur
immediately following the Diode Transfer sequence, before
the first line is read out. If the Integrate Start Pulse Line
Number value is greater than the number of vertical lines in
the Frame Table, there will be no Electronic Shutter. This is
the method used to disable the Electronic Shutter.

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Figure 12. Electronic Shutter Timing
Reg3 Entry
V1_CCD
V2_CCD
setup width hold (Line Table 0)
30 200 30Pix Counts
(not to scale)
VSUB
H1A_CCD
H2A_CCD
Start of Integration
Horizontal Timing
Figure 13 depicts the basic theoretical relationship
between the pixel-rate clocks to the CCD, the Video output
of the CCD, and the pixel-rate clocks to the AFE.
Figure 13. Horizontal Timing
VOUT_CCD
RESET_CCD
H2A_CCD
H1A_CCD
SHP
DATACLK
SHD
Tr
Tpix
Vpix Vsat
Tshp
Tshd
Binning Mode Horizontal Timing
In order to sum the charge from two Horizontal CCD
pixels into one, the Reset clock is suspended on alternating
Horizontal clock cycles. In this way, two pixels of charge are
dumped onto the floating diffusion of the output amplifier
before this node is reset to VRD, the Reset Drain voltage.
See the KAI−2093 Device Specification (References) for
further details.
In order to correctly convert the output amplifier voltage
to digital data, the AFE clocks must be adjusted accordingly.
The Clamp pulse (SHP) samples the output after the Reset
pulse has been issued, but before the Horizontal clocks have
moved charge onto the floating diffusion. The Sample pulse
(SHD) samples the output after two Horizontal clock cycles
have moved two charge packets onto the floating diffusion.
The DATACLK then clocks the AFE to perform the
conversion.
The KSC−1000 has the capability of implementing the
Horizontal Timing necessary to bin up to four pixels. This
feature is controlled by setting bits 3:4 of the active Frame
Table (Register 8) in the KSC−1000. Figure 14 depicts the
basic theoretical relationship between the pixel-rate clocks
to the CCD, the Video output of the CCD, and the pixel-rate
clocks to the AFE in 2×Horizontal Binning Mode.

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The Altera PLD default KSC−1000 settings contain 2×2
Binning Mode timing in Frame Table 2 (See Figure 11). In
order to activate the 2×2 Binning Mode, the Frame Table
Pointer (Register 0) must be changed to a value of 2. This is
done by setting SW2 HIGH and pressing the
BOARD_RESET button (S1 on the Timing Board).
Figure 14. Binning Mode Horizontal Timing
VOUT_CCD
RESET_CCD
H2A_CCD
H1A_CCD
SHP
DATACLK
SHD
Tr
Tpix
Tshp
Tshd
Integration & Shutter Timing
Free-Running Mode
The default Integration Time in Free-Running Mode is
approximately one Frame Time, or the time between Frame
Transfers, during which the photodiodes are collecting
charge (Figure 16). This time may be decreased by use of the
Electronic Shutter (Figure 17), and may be increased by
lengthening the Frame Time (Figure 18). The user may
control the Integration Time through the DIO connector bits
DIO[11..7]. This connector is optional, and when
disconnected, all bits are pulled LOW. The available
pre-programmed Integration Times are detailed in Table 25.
The Electronic Shutter is controlled by changing the
Integrate Start Pulse Line Number value of the KSC−1000
Register 4. The Altera PLD has 8 pre-programmed Shutter
settings, controlled through the DIO[11..7] bits, as shown in
Table 14 and Table 25. These settings result in Integration
times of one Frame Time or less, in increments of 1/8 of the
Frame Time (See Figure 17). When the Integrate Start Pulse
Line Number value is set to 2040, the Shutter is never
pulsed, as this value exceeds the number of lines in a frame
(Figure 16 and Figure 18). Either the BOARD_RESET
switch must be pressed, or the Remote Reset (DIO14) must
be toggled, after changing the DIO[11..7] bits in order for the
change to the KSC−1000 to take effect.
The Integration time is controlled by the Altera PLD. In
Free-Running mode, the KSC−1000 waits for a trigger
signal (VD_TG) before beginning the Diode Transfer
sequence (See Figure 16). The Altera PLD issues this trigger
pulse when the Integration Counter has reached
a pre-programmed value, as shown in Table 25. The
Integration counter is clocked by an internally-generated
1 ms clock. The default value of 0 means that the VD_TG
trigger is issued on the next rising edge of the 1 ms clock
after the frame readout is complete. A value greater than 0
adds that many milliseconds to the Integration Time,
allowing Integration times greater than 8 seconds
(Figure 18).

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Table 25. PROGRAMMED INTEGRATION TIMES
DIO[11..7] Int Count Free-Run Mode Reg4 Entry Free-Run Mode Tint(s)
0 (Default) 02040 (No Shutter) 0.115
1 0 966 0.014
2 0 828 0.029
3 0 690 0.043
4 0 552 0.057
5 0 414 0.072
6 0 276 0.086
7 0 138 0.101
8 1 2040 (No Shutter) 0.116
9 3 2040 (No Shutter) 0.118
10 5 2040 (No Shutter) 0.120
11 10 2040 (No Shutter) 0.125
12 25 2040 (No Shutter) 0.140
13 50 2040 (No Shutter) 0.165
14 70 2040 (No Shutter) 0.185
15 100 2040 (No Shutter) 0.215
16 200 2040 (No Shutter) 0.315
17 300 2040 (No Shutter) 0.415
18 400 2040 (No Shutter) 0.515
19 500 2040 (No Shutter) 0.615
20 600 2040 (No Shutter) 0.715
21 700 2040 (No Shutter) 0.815
22 800 2040 (No Shutter) 0.915
23 900 2040 (No Shutter) 1.015
24 1000 2040 (No Shutter) 1.115
25 2000 2040 (No Shutter) 2.115
26 3000 2040 (No Shutter) 3.115
27 4000 2040 (No Shutter) 4.115
28 5000 2040 (No Shutter) 5.115
29 6000 2040 (No Shutter) 6.115
30 7000 2040 (No Shutter) 7.115
31 8000 2040 (No Shutter) 8.115