NXP Semiconductors freescale TWR-56F8200 User manual

Freescale Semiconductor Document Number: TWR56F8200UG
User Guide Rev 1, 10/2013
© 2013 Freescale Semiconductor, Inc.
_______________________________________________________________________
TWR-56F8200 Tower Board
1Overview
The MC56F8200 Tower System 32-bit MCU
module (TWR-56F8200) is an evaluation,
demonstration and development board. The
TWR-56F8200 can operate standalone or as the
main control board in a Tower system with
peripheral modules. It can also be used as the
main control board with an
APMOTOR56F8000E motor control board.
The following list summarizes the features of
the TWR-56F8200:
32-bit Digital Signal Controller module
featuring MC56F82748 in a 64-LQFP
package
Tower system compatible
Selectable power sources:
oUSB on 56F8200 card
oBarrel connector on 56F8200
card
oMotor control board plug
direct to 56F8200 card, no
Tower System connection,
plug motor control to 9 V.
oTower System elevator board
(USB or Barrel on Primary
side)
Contents
1Overview................................................... 1
2Hardware features..................................... 3
3Jumper table............................................ 15
4Getting started......................................... 18
5Revision history...................................... 35
6Appendix A –Tower system elevator
connector pin functions................................... 35
7Appendix B—TWR-56F8200 board
schematic......................................................... 38
8Appendix C—TWR-56F8200 board BOM
38
9Appendix D—TWR-56F8200 board jack
layout (top view)............................................. 43
10 Appendix E—TWR-56F8200 board jack
layout (bottom view)....................................... 44

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Filtered power for VDDA and VSSA on the 32-bit MC56F82748DSC
Optional 8 MHz crystal circuit for the MC56F82748 DSC
Nine LEDs controlled by the MC56F82748 DSC
Two trimmer potentiometers for user to change analog input voltage
Motor Control Board connector for the APMOTOR56F8000E motor control board
Auxiliary Signal connector
Four thermistors for single-ended or differential analog inputs to the MC56F82748 DSC
CAN transceiver, header, and termination
Two push-buttons for user input or interrupts to the MC56F82748 DSC
Reset push-button for the MC56F82748 DSC
JTAG header for the MC56F82748 DSC with header to disconnect from OSBDM/OSJTAG
Headers to connect SCI signals to either USB bridge with CDC(one channel) or elevator board
(two channels) or connect one to each
Expansion via Primary Elevator connector
MC9S08JM60 MCU with a 4 MHz crystal provides:
oOpen Source Debug (OSBDM/OSJTAG) circuit
oUSB- to-SCI bridge with CDC and other techniques supported by third parties
oSimultaneous OSBDM/OSJTAG and USB -to-SCI bridge functions with no header
required to select
oHeader with enabled boot loader allows easy upgrade to latest S08 firmware pushed
down by CodeWarrior
oBDM header for the MC9S08JM60 MCU
oStatus and Target Power indicator LEDs
oControl of semiconductor switch to supply power to board from USB
oVoltage translators between 5 V MC9S08JM60 MCU chip and 3.3 V MC56F82748 DSC
chip
1.1 Block diagram
The block diagram for the TWR-56F8200 board is shown in this figure.

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From an engineering perspective, the measuring instrument is controlled by legally relevant and legally
non-relevant software applications (see Error! Reference source not found.).
MCU/DSC
Legally relevant
software
Legally non-
relevant software
Display/Printer/
Communication Keyboard
HAN
RTC
NVM
ADC
billing
ADC
billing
ADC
Aux.
Software
separation
Legally non-relevant applications perform all remaining software tasks including communicating
digitally-signed packets to the utilities and providing data to equipment attached to a Home Area
Figure 2. Kinetis M block diagram
1.2 Reference documents
The documents listed below should be referenced for more information on the Freescale Tower system
and the TWR-56F8200. See www.freescale.com/MC56F827xx, www.freescale.com/TWR-56F8200,
and www.freesale.com/Tower for the latest revision of all applicable documentation (if and when
available).
1. Freescale Tower Electromechanical Specification
2. TWR-56F8200 Quick Start Guide
3. TWR-56F8200 Sample code
4. MC56F82XXX Reference Manual
5. MC56F82XXX Data Sheet
6. MC56F82XXX Chip Errata [if exists]
7. USB Bootloader for the MC9S08JM60 (document number AN3561)
8. APMOTOR56F8000e Motor Control Demonstration System User Guide
9. BLDC Motor Control with Hall Sensors Driven by DSC using TWR-56F8257 and TWR-MC-
LV3PH (document number AN4413)
2Hardware features
This section provides more details about the features and functionality of the TWR-56F8200.
A schematic drawing of the TWR-56F8200 showing the jack locations is given in Appendix D—TWR-
56F8200 board jack layout (top view). Features are discussed in the following sections.
Motor Control&
Aux Connectors
Tower Elevator Expansion Connectors
(SPI, I2C, ADC, FEC, TPM, SCI, KB, etc.)
5.0V
External Connectors
3.3V
Freescale Device
External Connectors
Interface Circuits
Power
OSBDM (MC9S08JM60 MCU
Debug, Power, SCI Headers)
Headers
5.0V
External Connectors
USB
Mini-AB
Voltage
Translators
BDM
Header
LEDs & Buffers (9)
IRQ PB & HDRs (2)
RESET PB
Thermistors & HDRs
(4)
Analog Filters
Microphone (optional)
CAN XCVR & HDR
Barrel Power Connector
Power Selection HDRs
Voltage Regulator
5V-
9V
3.3V
MC56F82748
Digital Signal
Controller
JTAG
Header
Boot load HDR
Figure 1. TWR-56F8200 block diagram

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2.1 Tower system MCU module
The TWR-56F8200 board is an MCU module designed for standalone use (or with a Freescale Tower
system) and complies with the electrical and mechanical specification as described in Freescale Tower
Electromechanical Specification [1]. Connection to the Tower system is through two expansion card-
edge connectors that interface to the Elevator boards in a Tower system: the Primary and Secondary
Elevator connectors. The Primary Elevator connector, comprised of sides A and B, is utilized by the
TWR-56F8200, while the Secondary Elevator connector only makes connections to ground (GND). On
sheet 8 of the TWR-56F8200-SCH (See Appendix B—TWR-56F8200 board schematic), the J500A and
J500B symbols have names assigned to the card edge fingers that correspond with the normal Tower
system pin assignments.
Note: On the top and bottom of one edge of the TWR-56F8200 board, there is a WHITE BELT; the
card-edge connectors next to the WHITE BELT on the TWR-56F8200 board should be connected to the
Primary Elevator board which uses the WHITE PCI connector. The card-edge connectors without the
WHITE BELT on the TWR-56F8200 board should be connected to the secondary Elevator board (or left
unconnected) using the Black PCI connector. This instruction overrides any silkscreen information that
may be present, such as the words “Primary” or “Secondary” on the TWR-56F8200, since early
revisions had this reversed.
2.2 System power
The TWR-56F8200 board has three power rails: P5V_USB, P3_3V, and P3_3V/5V. The sources and
usage of these power rails is described as follows.
2.2.1 P5V_USB
The P5V_USB power rail is derived from the mini-B USB connector at J18 and the inductor at L2. It is
used to power the on board OSBDM/OSJTAG/Serial Bridge circuit. This consists of the
OSBDM/OSJTAG MCU at U6, several pullup resistors at R13, R14, R15, R527, and R528, the USB
power switch at U501, and the STATUS and TPWR LEDs at D12 and D13. If there is no USB cable
connected to J18, there is no power on this rail and all these circuits are powered down.
2.2.2 P3_3V
The P3_3V power rail is derived from either of the following sources.
the P3_3V_MOTOR power net from the motor control board connector at J501,
the P3_3V_ELEV power net from the Tower connector at J500, or
the onboard 3.3 V regulator at U1
The selection of any of these power sources is made with a shunt from J7-2 (jumper J7 pin 2) to another
pin of J7 or to J6. A shunt from J11-2 (Jumper J11-pin2) to another pin of J11 or to J10, is used to select
power to the regulator from the following sources:

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the P5V_TRG_USB power net out of the USB switch at U501,
the P5V_ELEV power net from the elevator connection at J500 pins A1 and B1, or
the PWR_IN power net from the 2mm barrel jack at J3 through resettable fuse F1.
Table 6 shows the operation of the different shunt positions. The barrel jack input is protected from
reverse voltage inputs by diode D11. The input to the barrel jack may be from a 5-9 V source and needs
to be center-positive.
The P3_3V power rail provides power to the majority of the circuits on the board including the
MC56F82748 (including the analog power pins through L500 and L501), inverters at U500 and U502, a
buffer at U505, the onboard LEDs at D1-D9, the thermistor divider circuits at RT1-RT4, and the pullup
resistors at R2, R3, R11, R565, R570, and R562.
2.2.3 P3_3V/5V
The P3_3V/5V power rail is derived from the diode OR (using D500 and D501) of:
the P5V_ELEV power net from the elevator connection (J500 pins A1 and B1),
the P5V output of the USB power switch at U501, or c) the P3_3V power rail from J7.
When there is a USB cable connected or when the Tower elevator boards are connected, this power rail
will be a Schottky diode drop (about 0.3V) below the 5 V power nets. When there is no 5 V source, this
power rail will be a Schottky diode drop below the P3.3V power rail. This allows the inputs of the ICs
powered by this rail to stay in a high-impedance state instead of loading down the inputs through the
input protection diodes as would happen if there were no power supplied to the buffers.
2.2.4 Default power configuration
The TWR-56F8200 board default power configuration uses the OSBDM/OSJTAG USB port for all
power. As soon as the OSBDM/OSJTAG firmware has started, it negotiates with the host PC USB port
for full USB power. Once approved, it enables the 5V USB power switch (U501) which provides 5 V to
the P3_3V/5 V power rail and to the 3.3 V regulator (U1) through headers J10 and J11. Likewise, the
onboard voltage regulator provides 3.3 V to the P3_3V power rail through headers J6 and J7. The 3.3 V
regulator is able to provide up to 700 mA current, subject to the power dissipation and temperature
limits of the device.
2.3 MC56F82748 DSC
The primary circuits on the board are related to the MC56F82748 DSC. This part is supplied in a
surface-mounted 64-pin LQFP package at U2. Although the board was laid out to allow a ZIF socket at
U3 in parallel to the chip at U2, the TWR-56F8200 is only available for purchase with the surface-
mounted chip.

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2.3.1 Clock sources for the MC56F82748 DSC
Three options are available for clocking the MC56F82748 device:
Oscillator internal to the MC56F82748 chip —approximately 8 MHz.
8 MHz crystal
External clock input from Primary Tower Connector or the AUX Connector.
The internal oscillator is used to clock the MC56F82748 MCU immediately following reset. This is the
default operation. In this mode, the 0-ohm resistors at R4 and R10 allow the GPIOC0 and GPIOC1 pins
of the MC56F82748 MCU to be used as inputs or outputs.
To use an external crystal with the MC56F82748, 0-ohm resistors R4 and R10 must be removed and
placed in the R5 and R7 positions. The desired crystal, load capacitors, and parallel resistor (if needed)
must be soldered to the board at Y1, C5, C6, and R6. (These components are not provided with the
TWR-56F8200 kit.) Following reset, reconfigure the GPIOC0 and GPIOC1 pins to the XTAL and
EXTAL functions to allow the use of an external crystal.
To use an external clock for the MC56F82748, make sure the 0-ohm resistors are installed at R4 and
R10 and removed from R5 and R7. Provide a clock signal on either the Primary Tower Connector
J500A - pin B24 (the pin designated as CLOCKIN0), or on the AUX connector J502 - pin 8. Following
reset, configure the GPIOC0 pin to the CLKIN input function. In this mode, the 0-ohm resistors at R10
allows the GPIOC1 pin of the MC56F82748 (pin 10) to be used as an input or output.
2.3.2 Serial I/O source select headers
The TWR-56F8200 board allows the UART functions of the MC56F82748 DSC to be connected to the
serial interface of the Primary Tower Connector J500A or through a USB bridge to the host PC using the
OSBDM/OSJTAG MCU (U6). The selection of the RXD connections is done as shown in Table 1.The
selection of the TXD connections is done as shown in Table 2.
Table 1. J8-RXD source select header
Pin#
Connected signal
Description
1
ELEV_RXD0 at J500A pin A41
Shunt pins 1 and 2 together to connect the DSC
RXD0 pin to the primary Tower Connector
RXD0 pin. (This is a default position.)
2
GPIOF8/RXD0/TB1 from the
56F82748 DSC –pin 6 (RXD0
function)
—

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Pin#
Connected signal
Description
3
RXD_SEL from the USB bridge
function on the OSBDM/OSJTAG
MCU.
Shunt pins 2 and 3 together to connect
the DSC RXD0 pin to the USB serial
bridge function.
Shunt pins 3 and 4 together to connect
the DSC RXD1 pin to the USB serial
bridge function.
4
GPIOF5/RXD1/XB_OUT5 from the
56F82748 DSC –pin 42 (RXD1
function)
—
5
ELEV_RXD1 at J500 pin A43
Shunt pins 4 and 5 together to connect the DSC
RXD1 pin to the primary Tower Connector
RXD1 pin. (This is a default position.)
Table 2. J9–TXD source select header
Pin #
Connected Signal
Description
1
ELEV_TXD0 at J500A pin A42
Shunt pins 1 and 2 together to connect the DSC
TXDO pin to the primary Tower Connector
TXD0 pin. (This is a default position.)
2
GPIOC2/TXD0/TB0/XB_IN2/CLKO
from the 56F82748 DSC –pin 5
(TXD0 function)
—
3
TXD_SEL to the USB bridge function
on the OSBDM/OSJTAG MCU.
Shunt pins 2 and 3 together to connect
the DSC TXD0 pin to the USB serial
bridge function.
Shunt pin 3 and 4 together to connect the
DSC TXD1 pin to the USB serial bridge
function.
4
GPIOF4/TXD1/XB_OUT4 from the
56F82748 DSC –pin 41 (TXD1
function)
—
5
ELEV_TXD1 at J500 pin A44
Shunt pins 4 and 5 together to connect the DSC
TXD1 pin to the primary Tower Connector
TXD1 pin. (This is a default position.)

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As can be seen in the tables, the 56F82748 DSC serial signals may be connected to either the Tower
serial signals or to the USB bridge chip; however, only one channel may be connected to the USB
bridge chip. If the associated 56F82748 DSC serial pins are not being used for the serial functions, the
shunts should be removed from those pins. For more information on the USB Serial Bridge function, see
USB serial bridge interface.
There are some tower boards available, such as TWR-SER that provide serial ports based on these
elevator connections. These boards can work with the TWR-56F8200, if configured and installed in the
same Tower system.
2.3.3 LEDs controlled by the MC56F82748 DSC
There are nine LEDs with buffers connected to the MC56F82748 DSC. Inverting buffers (U500A-F and
U502D-F) isolate the LEDs from the DSC pins by providing high-impedance inputs. The LEDs are
powered by the P3_3V rail and each LED draws about 5 mA current. This table shows the DSC pin
names associated with each LED.
Table 3. LEDs controlled by the MC56F82748 DSC
MC56F82748 DSC
Pin name
MC56F82748
Pin number
LED
Reference
LED
Label
LED
Color
GPIOE0/PWM0B
45
D1
E0
Green
GPIOE1/PWM0A
46
D2
E1
Yellow
GPIOE2/PWM1B
47
D3
E2
Green
GPIOE3/PWM1A
48
D4
E3
Yellow
GPIOE4/PWM2B/XB_IN2
51
D5
E4
Green
GPIOE5/PWM2A/XB_IN3
52
D6
E5
Yellow
GPIOE6/PWM3B/XB_IN4
53
D7
E6
Green
GPIOE7/PWM3A/XB_IN5
54
D8
E7
Yellow
GPIOF6/TB2/PWM3X
94
D9
F6
Amber
2.3.4 Motor control connector
The TWR-56F8200 board may be connected to a motor control board APMOTOR56F8000E. The motor
control connector (J501) is at the bottom of the board to provide a convenient connection to the motor
control board.

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Some of the MC56F82748 DSC pins are connected to the motor control connector. The pins associated
with analog inputs have 100 Ω resistors in series to provide some ESD protection for the analog inputs
of the DSC. The pins providing analog signals from the motor control board have 2200 pF capacitors
with the 100 Ω resistors to provide a low-pass filter. The connector pinout is shown in Table 4.
Table 4. Motor control connector pinout
Pin
#
MC56F82748 DSC signal
Pin
#
MC56F82748 DSC signal
1
P3_3V_MOTOR
2
GPIOB7/ANB7&ANC15&CMPB_IN2
(With 100 Ωin series)
3
GND
4
RESETB/ GPIOD4
(With 0 Ωin series –remove to isolate)
5
GPIOF4/TXD1/XB_OUT8
6
GPIOA3/ANA3&VREFLA&CMPA_IN2
(With 100 Ωin series)
7
GPIOF3/SDA1/XB_OUT7
8
GND
9
GPIOE1/PWMA_0A
10
GPIOA0/ANA0&CMPA_IN3/CMPC_O
(With 100 Ω, 2200 pF low-pass filter)
11
GPIOE0/PWMA_0B
12
GPIOA1/ANA1&CMPA_IN0
(With 100 Ω, 2200 pF low-pass filter)
13
GPIOC3/TA0/CMPA_O/RXD0/CLKIN1
14
GPIOA2/ANA2&VREFHA&CMPA_IN1
(With 100 Ω, 2200 pF low-pass filter)
15
GPIOC13/TA3/XB_IN6/EWM_OUT_B
16
GND
17
GPIOC4/TA1/CMPB_O/XB_IN8/EWM_OUT_B
18
GPIOB0/ANB0&CMPB_IN3
(With 100 Ω, 2200 pF low-pass filter)
19
GPIOC6/TA2/XB_IN3/CMP_REF
20
GPIOB1/ANB1&CMPB_IN0
(With 100 Ω, 2200 pF low-pass filter)
21
GPIOC15/SCL0/XB_OUT5
22
GPIOB2/ANB2&VREFHB&CMPC_IN3
(With 100 Ω, 2200 pF low-pass filter)
23
GPIOC14/SDA0/XB_OUT4
24
GND
25
TDI /GPIOD0
26
GPIOE7/PWMA_3A/XB_IN5/PWMB_2A
27
TDO/ GPIOD1
28
GPIOE6/PWMA_3B/XB_IN4/PWMB_2B

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Pin
#
MC56F82748 DSC signal
Pin
#
MC56F82748 DSC signal
29
TCK/GPIOD2
30
GPIOE3/PWMA_1A
31
TMS /GPIOD3
32
GPIOE2/PWMA_1B
33
GPIOB3/ANB3&VREFLB&CMPC_IN0
(With 100 Ωin series)
34
GPIOE5/PWMA_2A/XB_IN3
35
GPIOB4/ANB4&ANC12&CMPC_IN1
(With 100 Ωin series)
36
GPIOE4/PWMA_2B/XB_IN2
37
GPIOB5/ANB5&ANC13&CMPC_IN2
(With 100 Ωin series)
38
GPIOA4/ANA4&ANC8&CMPD_IN0
(With 100 Ωin series)
39
GPIOB6/ANB6&ANC14&CMPB_IN1
(With 100 Ωin series)(100K Trimpot in parallel)
40
GPIOA5/ANA5&ANC9
(With 100 Ωin series)(100K Trimpot in
parallel)
2.3.5 Auxiliary connectors
In addition to the motor control connector, the TWR-56F8200 board also provides two auxiliary
connectors J502 at the bottom of the board. These connectors provide access to the MC56F82748 DSC
signals that are not covered by the motor control connector. The pins associated with analog inputs have
100 Ωresistors in series to provide some ESD protection for the analog inputs of the DSC. The
connector pinout is shown in this table.
Table 5. Auxiliary connector J502 pinout
Pin #
MC56F82748 DSC signal
Pin #
MC56F82748 DSC signal
J502-1
GPIOF0/XB_IN6/TB2/SCK1
J502-2
GPIOA6/ANA6&ANC10
(With 100 Ωin series)
J502-3
GPIOF1/CLKO1/XB_IN7/CMPD_O
J502-4
GPIOA7/ANA7&ANC11
(With 100 Ωin series)
J502-5
GPIOF2/SCL1/XB_OUT6
J502-6
GND
J502-7
GPIOF5/RXD1/XB_OUT9
J502-8
GPIOC0/EXTAL/CLKIN0
J502-9
GPIOF6/TB2/PWMA_3X/PWMB_3X/XB
_IN2
J502-10
GPIOC1/XTAL