NXP Semiconductors SJA1105SMBEVM User manual

AH1721
SJA1105SMBEVM User Manual
Rev. 1.00 —16 July 2018
User Manual
Document information
Info
Content
Keywords
SJA1105PQRS, SJA1105S, SJA1105S Evaluation Board,
SJA1105SMBEVM, Cascading, Ethernet, Wakeup, Sleep
Abstract
The SJA1105SMBEVM Evaluation Board is described in this document.

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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: mailto:[e-mail]
Revision history
Rev
Date
Description
1.00
20180716
Release

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1. Introduction
The SJA1105SMBEVM (SJA1105S Mother Board Evaluation Module, see Fig 1) is
designed for evaluating the capabilities of the SJA1105P/Q/R/S Automotive Ethernet
switch family and the TJA1102 Automotive Ethernet PHYs, by developing and running
customer software. Therefore, the board features the MPC5748G MCU with a rich set of
peripherals for communication and automotive applications.
It is designed to allow early adaptions of applications, like a X-to-Ethernet gateway,
communication hub, etc.
Fig 1. SJA1105SMBEVM board
This user manual describes the board hardware and the software development
environment to allow the user to quickly bring up a working system and to pave the way
towards an own customized software, and in the end towards an all custom system.
After the HW description the manual walks the user through the process to create the
factory firmware starting at the supplied example project and describes the
recommended SW development environment S32 Design Studio for Power as far as it is
needed for the example project.
2. Prerequisites
Besides this document and the hardware package you will need the following support
material - consult https://www.docstore.nxp.com and https://www.nxp.com
SJA1105PQRS User Manual (UM11040)
SJA1105PQRS Data sheet
SJA1105PQRS Application Hint (AH1704)
TJA1102 Datasheet

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User Manual
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TJA1102 Application Hint (AH1508)
SJA1105S Evaluation Board Software Package
TJA1145FD CAN-Transceiver Product data sheet and Application Hint (AH1309)
MPC5748G reference manual
If you want to download and run SW on the SJA1105SMBEVM you also need a JTAG-
Debug adapter. The easiest solution is the PEMicro “USB Multilink Universal”USB-to-
JTAG debug probe
(http://www.pemicro.com/products/product_viewDetails.cfm?product_id=15320168), as
this is already integrated in the S32 Design Studio IDE.
3. System Overview

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Fig 2. Block diagram indicating the primary functional blocks and interconnections
The primary functional components of the SJA1105SMBEVM Evaluation Module are:
•1 Microcontroller MPC5748G
•2 switches SJA1105S: ETH-SW(A) and ETH-SW(B)
•3 100BASE-T1 PHYs: ETH-PHY TJA1102 (2*) + TJA1102S
•2 1000BASE-T PHYs: 1G PHY KSZ9031
•1 100BASE-TX PHY; FE PHY DP83848C
•1 CAN Transceiver TJA1145FD
•1 UART-USB-Converter FT230XQ
The main Ethernet data paths are:

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•Switch-A and Switch-B can exchange ethernet data via a SGMII connection at
1GBps.
•Port0 of the MPC5748G is wired to Switch-A Port0 using MII-Lite at 100MBps.
•The FE-PHY is directly connected to MPC5748G’s Port1, also with MII-Lite.
•The 1G-PHYs are connected to Switch-A’s ports 2 and 3. These links support
speed autonegotiation, but not direction autonegotiation. The actual link speed
depends on the result of the autonegotiation process.
4. Hardware Description
4.1 Power
The SJA1105SMBEVM is powered by a single 12 Volt input. It is advised to use an
adapter that can deliver at least 1 Amp for covering startup current peaks and full-load
situations. The nominal current is ~350mA@12V and depends on the number of active
PHYs, and if the port is connected to a peer.
The power supply topology is shown in Fig 3. The switching regulators for 5V0, 3V3 and
2V5 are controlled by the signal VREG_EN, which can be either fixed to “enable” or
controlled by a combination of an output signal from the PHYs and some sign-off signal
from the CPU. The selection is done with a jumper (J6). With this schema, most of the
board can be switched off when entering sleep mode. For more details see chapter 6.4.
4.2 MPC5748G Microcontroller
The microcontroller runs the user’s software, which controls all components on the
board, e.g. switches, PHYs, LEDs, etc. It also has an ethernet connection to the
switches, so it can receive and send ethernet packets. Therefore, the microcontroller can
work as a host controller for protocols like gPTP, where the software works in conjunction
with hardware features implemented in the switches.
which are only partly implemented in the switches, and need SW assistance.
The MPC5748G features:
•2 e200Z4 32bit cores with 160MHz and 8k I-cache + 4k D-cache
Fig 3. Power supply topology

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•1 e200Z2 32bit core with 80MHz
•6MB on-chip flash and 768kB internal RAM
•2 independent 100Mbps ethernet ports with AVB and 1588 support
•6 SPI, 18 LIN/UART, 8 CAN (with FD support), 4 I2C and USB peripheral blocks
•Standard microcontroller infrastructure, like interrupt controller, DMA, timer,
watchdog, JTAG debug interface, etc.
For making the task to create user’s software easier, there is an example project, which
initializes all peripherals on the SJA1105SMBEVM and implements basic functions, like
communicating via the USB-UART adapter, configuring the PHYs and switches, sending
and receiving ethernet packets, sending and receiving CAN frames, dealing with PHY
plug events, etc. This example project serves as a foundation for user extensions for
specific applications.
The SW development environment and the example project is described in chapter 6.
4.3 SJA1105S switches
The SJA1105S is an IEEE 802.3-compliant 5-port automotive Ethernet switch supporting
Audio Video Bridging (AVB) and Time-Sensitive Networking (TSN) standards. It is a
member of the SJA1105P/Q/R/S family of switches:
Table 1. SJA1105P/Q/R/S variants
Device
SGMII interface
TT-Ethernet and TSN-Ethernet
SJA1105P
No
No
SJA1105Q
No
Yes
SJA1105R
Yes
No
SJA1105S
Yes
Yes
The SJA1105S’s fifth port is a SGMII-only port and is capable to operate at up to 1Gbps.
The other four ports can be individually configured to operate at 10Mbps, 100Mbps or
1Gbps, depending on the capability and configuration of the PHY connected. Interfacing
a PHY to one of these four ports can be done using one of the 3 supported MII interface
standards: MII, RMII or RGMII.
This port arrangement provides the flexibility to connect a mix of PHY devices such as
the TJA110x 100BASE-T1 PHYs from NXP Semiconductors and other commercially
available Fast Ethernet and Gigabit Ethernet PHYs, or fiber optic PHYs. The high-speed
interface makes it easy to cascade multiple switches of the SJA1105 family for
scalability. It can be used in various automotive scenarios such as gateway applications,
body domain controllers or for interconnecting multiple ECUs in a daisy chain. Full Audio
Video Bridging (AVB) support means that the SJA1105 family can be used in
infotainment and driver assistance systems. Time-triggered Ethernet and Time-Sensitive
Networking support with IEEE 802.1Qbv time-aware traffic shaping and IEEE 802.1Qci
per-stream policing makes the SJA1105 family usable in applications with hard realtime
communication requirements.
In the SJA1105SMBEVM design, the switches are used in a cascaded topology: the
SGMII ports are connected to create a high-speed link for forwarding payload ethernet
frames and management data frames. Cascading also includes HW provisions to
synchronize the PTP clock counter by using a master/slave clock configuration.
The usage of the switches’ ports is shown in Table 2.

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4.4 TJA1102 PHYs for 100BASE-T1
The TJA1102 is an OPEN Alliance 100BASE-T1 compliant Dual Ethernet PHY optimized
for automotive use cases. The device provides 100Mbit/s transmit and receive capability
over a single Unshielded Twisted Pair (UTP) cable, supporting a cable length of up to at
least 15 m. Optimized for automotive use cases such as IP camera links, driver
assistance systems and back-bone networks, the TJA1102 has been designed to
minimize power consumption and system costs, while still providing the robustness
required for automotive use cases.
The default configuration of the TJA1102 PHYs on the SJA1105S Evaluation Module are
detailed in Table 2, together with the interconnection to the switch ports. The PHYs’
default configuration can be overruled by issuing SMI commands to the PHY.
Table 2. Ethernet port usage and default PHY configurations
MAC:
PHY/Peer
MII mode:
Connector
SMI
address:
Master / Slave:
Switch A0
Proc Port0
MII-Lite
-
-
-
Switch A1
U19, TJA1102S
RMII
J11
4
Master
Switch A2
U18, KSZ9031
RGMII
P2
2
-
Switch A3
U17, KSZ9031
RGMII
P1
3
-
Switch A4
Switch B4
SGMII
-
-
-
Switch B0
U21A, TJA1102
RMII
J14
6
Master
Switch B1
U21B, TJA1102
RMII
J15
7
Master
Switch B2
U20A, TJA1102
RMII
J12
8
Master
Switch B3
U20B, TJA1102
RMII
J13
9
Master
Switch B4
Switch A4
SGMII
-
-
-
Proc Port0
Switch A0
MII-Lite
-
-
-
Proc Port1
J4
MII-Lite
J4
1
-
4.5 PHYs for copper ethernet
For the two GBit (1000BASE-T) ports A2 and A3 the KSZ9031 PHY is used. The two
PHYs are connected to Switch-A via RGMII.
The single FE (100BASE-TX) port, which makes the MPC5748G’s 2nd ethernet port
available, uses a DP83848 PHY.
The copper ethernet PHYs are configured to allow autonegotiation. This requires SW
assistance to configure the MACs in the switch or the in the µC to the interface speed.
4.6 CAN interface
The SJA1105SMBEVM features a CAN interface, which is implemented with one of the
MPC5748G’s FlexCAN-controllers and the TJA1145TK/FD CAN transceiver. In the
example project, the CAN-interface is configured with 100kbps and a payload size of
8Byte. FD extensions are not used.
The TJA1145TK/FD requires a configuration setting via SPI before it can forward data.
This is also done in the example project.

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4.7 LEDs
Fig 4. LEDs and Connectors
Table 3. SJA1105SMBEVM LEDs overview
LED label
Color
Description:
D1
red
Indicates if the reset line for the on-board μC is active.
D2, D4,
D5, D15,
D16
green
link-up indication LEDs for the 100BASE-T1 ethernet ports. Each LED
is controlled by the on-board uC. and is set/cleared by the
LinkUp/LinkFail interrupt of the associated port’s PHY.
D2: Port A1
D4: Port B0
D5: Port B1
D15: Port B2
D16: Port B3
J4-L, J4-R
L=green
R=yellow
LEDs integrated in the FE connector J4
L = Link; controlled by the FE-PHY U10 LEDLINK output. By default
(Mode 1) the LED is on when there is a good link on the port.
R = Activity; controlled by the FE-PHY U10 LEDACTCOL output. By
default (Mode 1) the LED is on during activity on either TX or RX.

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LED label
Color
Description:
P2-L,
P2-R,
P3-L,
P3-R
L=green
R=yellow
LEDs integrated in the GBit connectors P2 and P3
L is controlled by the GBit PHY’s LED2 output, and R by the LED1
output. In Tri-Color dual-LED mode the following settings are used:
state
L = green
R = yellow
Link off
off
off
1000 Link, no activity
on
off
1000 Link/Activity (RX, TX)
blink
off
100 Link, no activity
off
on
100 Link/Activity (RX, TX)
off
blink
10 Link, no activity
on
on
10 Link/Activity (RX, TX)
blink
blink
D6, D7,
D8
green
Power-Good LEDs for the voltages generated by switching regulators.
D6 = 5V0
D7 = 3V3
D8 = 2V5
D11, D12
green
Power-Good LEDs for the voltages generated by LDOs.
D11 = 1V8
D12 = 1V2
D3
green
Labeled “ALIVE”. General purpose LED connected to the uC. Used by
the μC software as a heartbeat. This LED should continuously blink if
the example SW is running.
D17
green
General purpose LED connected to the uC. No special meaning.
D13
green
PTP LED. The LED is connected to SwitchA’s PTP_CLK output by a
transistor inverter. If PTP_CLK is low, the LED is off.
Positions of the LEDs are shown in Fig 4.
4.8 Jumper blocks and connectors
The position of the jumper blocks and connectors is shown in Fig 4.
Table 4. Jumper blocks and connectors
Name
Meaning/Usage
J1
Power Jack 12V input
J2
USB Type B receptacle for the serial link to PC
J3,J5
CAN bus termination setting; J3 = CAN_L, J5 = CAN_H
1-2: 120R termination active (used for an end node on the CAN bus)
2-3: 2k6 termination active (used for a middle node on the CAN bus)
No jumper: No termination
J4
Fast Ethernet RJ45 receptacle with LEDs
J6
Jumper block for selecting the source of the enable signal VREG_EN to the
switching power regulators (5V0, 3V3, 2V5)
2-3: 12V0 –regulators permanently enabled
1-2: VREG_EN is under control of the PHYs and the processor –see ch 6.3 for
sleep/wakeup