OLIMEX MSP430-CCRF User manual

MSP430-CCRF development board
Users Manual
All boards produced by Olimex are ROHS compliant
Revision A, June 20
Copyright(c) 20 , OLIMEX Ltd, All rights reserved
Page 1

INTRODUCTION:
MSP430-CCRF is de elopment board with CC430F5137IRGZ microcontrol-
ler from Texas Instruments. This ultra-low-power microcontroller has integrated RF
transcei er. The board has also UEXT, which can be modified as de ice or host.
MSP430-CCRF can communicate with other boards with integrated CC430F5137IR-
GZ ia radio connection.
BOARD FEATURES:
•Microcontroller: CC430F5 37IRGZ
•JTAG
•UEXT
•PWR jack for 2 x 1.5V AA batteries
•on-board oltage regulator
•On-bard pcb antenna
•Supported radio frequencies bands 868/915 MHz – software selectable.
By default – 868 MHz.
•Maximal permissible distance between two MSP430-CCRF boards
depends on RF chip's output power and the selected radio frequency
band. When RF chip's output power is set to maximum (>10 dBm),
then :
- If RF band is 868 MHz, distance is more than 200 m.
- If RF band is 915 MHz, distance is maximum 7-8 m.
•user button
•status led
•RTC crystal
•extension pin holes for most of the microcontroller pins
•FR-4, 1.00 mm, soldermask, component print
•Dimensions: 78.49 x 39.12mm (3.09 x 1.54")
ELECTROSTATIC WARNING:
The MSP430-CCRF board is shipped in protecti e anti-static packaging. The board
must not be subject to high electrostatic potentials. General practice for working
with static sensiti e de ices should be applied when working with this board.
Page 2

BOARD USE REQUIREMENTS:
Cables: The cable you will need depends on the programmer/debugger
you use. If you use MSP-JTAG-TINY, MSP-JTAG-TINY-V2, or MSP-JTAG-ISO, you
will need USB A-B cable. If you use MSP-JTAG, you will need LPT cable.
Hardware: Programmer/Debugger MSP-JTAG-TINY, MSP-JTAG-TINY-
V2, MSP-JTAG-ISO, MSP-JTAG, MSP-JTAG-RF, or other compatible
programming/debugging tool.
You can also use other Olimex's board MSP-CCRF, or MSP-CCRF-LCD for radio
communication.
PROCESSOR FEATURES:
MSP430-CCRF board use microcontroller CC430F5 37IRGZFBD 00 with these
features:
−True System-on-Chip (SoC) for Low-Power Wireless Communication
Applications
−Wide Supply Voltage Range: 1.8 V to 3.6 V
−Ultra-Low Power Consumption:
−CPU Acti e Mode (AM): 160 μA/MHz
−Standby Mode (LPM3 RTC Mode):2.0 μA
−Off Mode (LPM4 RAM Retention): 1.0 μA
−Radio in RX: 15 mA, 250 kbps, 915 MHz
−MSP430™ System and Peripherals
−16-Bit RISC Architecture, Extended Memory, up to 20-MHz System Clock
−Wake-Up From Standby Mode in Less Than 6 μs
−Flexible Power Management System with SVS and Brownout
−Unified Clock System with FLL
−16-Bit Timer TA0, Timer_A with Fi e Capture/Compare Registers
−16-Bit Timer TA1, Timer_A with Three Capture/Compare Registers
−Hardware Real-Time Clock
−Two Uni ersal Serial Communication Interfaces
−USCI_A0 supporting UART, IrDA, SPI
−USCI_B0 supporting I2C, SPI
−12-Bit A/D Con erter With Internal Reference, Sample-and-Hold, and
Autoscan Features
−Comparator
−128-bit AES Security Encryption/Decryption Coprocessor
−32-Bit Hardware Multiplier
−Three-Channel Internal DMA
Page 3

−Serial Onboard Programming, No External Programming Voltage Needed
−Embedded Emulation Module (EEM)
−High-Performance Sub-1-GHz RF Transcei er Core
−Wide Supply Voltage Range: 2.0 V to 3.6 V
−Frequency Bands: 300 MHz to 348 MHz, 389 MHz to 464 MHz, and 779
MHz to 928 MHz.
−Programmable Data Rate From 0.6 kBaud to 500 kBaud
−High Sensiti ity (-117 dBm at 0.6 kBaud, -111 dBm at 1.2 kBaud, 315 MHz,
1% Packet Error Rate)
−Excellent Recei er Selecti ity and Blocking Performance
−Programmable Output Power Up to +12 dBm for All Supported
Frequencies
−2-FSK, 2-GFSK, and MSK Supported as well as OOK and Flexible ASK
Shaping
−Flexible Support for Packet-Oriented Systems: On-Chip Support for Sync
Word Detection, Address Check, Flexible Packet Length, and Automatic
CRC Handling
−Support for Automatic Clear Channel Assessment (CCA) Before
Transmitting (for Listen-Before-Talk Systems)
−Digital RSSI Output
−Suited for Systems Targeting Compliance With EN 300 220 (Europe) and
FCC CFR Part 15 (US)
−Suited for Systems Targeting Compliance With Wireless M-Bus Standard
EN 13757-4:2005
−Support for Asynchronous and Synchronous Serial Recei e/Transmit
Mode for Backward Compatibility With Existing Radio Communication
Protocols
(1) 5, 3 - represents two instantiations of Timer_A, the first instantiation ha ing 5 and the second
instantiation ha ing 3 capture compare registers and PWM output generators, respecti ely.
Page 4

BLOCK DIAGRAM:
Page 5

MEMORY ORGANIZATION:
(1) All memory regions not specified here are acant memory, and any access to them causes a Vacant
Memory Interrupt.
Page 6

SCHEMATIC:
Page 7
3-1 2VDC
Monopole_PCB_Antenna
IT1185AU2
2.2nF
100nF
10uF/16V
100nF
100nF
10uF/6.3V
NA NA
100nF
10uF/6.3V
100nF
10uF/6.3V
100nF
10uF/6.3V
100nF
2pF
100nF
2pF
100nF
100nF
100nF
15pF 15pF 70nF
1pF/+-0.25pF/COG
1.5pF/+-0.25pF/COG 1.5pF/+-0.25pF/COG
100pF/5%/COG
3.3pF/+-0.25pF/COG
100pF/5%/COG
NANA
10uF/6.3V
100nF
BAT5 C
BAT5 C
1-2:Open; 2-3:Close 1-2:Open; 2-3:Close
BH1 S
FB0805/600R/200mA(201209-601) FB0805/600R/200mA(201209-601)
12nH/5%(ELJRE12NJFA/1198377)
12nH/5%(ELJRE12NJFA/1198377)
18nH/5%(ELJRE18NJFA/1198379) 18nH/5%(ELJRE18NJFA/1198379) 12nH/5%(ELJRE12NJFA/1198377)
12nH/5%(ELJRE12NJFA/1198377)
GYX-SD-T C0805SURK(RED)
WF2R
QCT32768/6pF
TSX-3225/26MHz/10PPM/9pF/3.2x2.5mm SMD
33k
330R
33k
33k .7k .7k
0R(NA) 0R(NA)
NA NA
56k/1%
0R(NA)
0R(NA)
330R
330R 33k
CC 30F5137IRG Z
BH10RBH10RBH10RBH10RBH10RBH10RBH10RBH10RBH10RBH10R
3.3V 3.3V 3.3V
3.3V
3.3V
3.3V 3.3V 3.3V 3.3V
MCP 1702T-3302E/MB
#RST/SWBTDIO BSLRX/UCA0RXD
BSL RX/UCA0RXD
BSLTX/UCA0TXD
BSL TX/UCA0TXD
BUT
BUT
LED
LED
SCL
SDA
SW_SCL
SW_SCL
SW_SDA
SW_SDA
TCK TDI TDO TEST/SWBTCK TMS UCB0_CLK
UCB0_CLK
UCB0_MISO /SCL
UCB0 _MISO/SCL
UCB0_MOSI/SDA
UCB0 _MOSI/SDA
UCB0 _STE
UCB0_STE
VIN
3.3V
ANT
BUT
C1
C2 C3
C
C5 C6
C7 C8
C9
C10
C11
C12
C13
C1
C15
C16
C17
C18
C19
C20
C21
C22 C23 C2
C25
C26
C27
C28
C29
C30
C31C32
C33
C3
D1
D2
GND
GND.
1
2
3
J1
1
2
3
J2
12 3 56 78 910 1112 131
JTAG
L1 L2
L3 L
L5 L6 L7
L8
LED
P1.0 P1.1 P1.2 P1.3 P1. P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2. P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3. P3.5 P3.6 P3.7
PJ.0 PJ.1 PJ.2 PJ.3
1 2
PWR
Q1
GND
GND_
Q3
R1 R2
R3
R
R5 R6
R8 R9
R10 R11
R12
R13
R1
R15
R16 R17
RST
TEST
#RST/NMI/SBWTDIO
0 AVCC 5
AVCC_RF 27 AVCC_RF 28 AVCC_RF 31 AVCC_RF 32
AVSS 2 DVCC 8 DVCC 22 DVCC 1
GUARD 3
P1.0/PM_RFGDO0
13
P1.1/PM_RFGDO2
12
P1.2/PM_UCB0SOMI/PM_UCB0SCL
11
P1.3/PM_UCB0SIMO/PM_UCB0SDA
10
P1. /PM_UCB0CLK/PM_UCA0STE
9
P1.5/PM_UCA0RXD/PM_UCA0SOMI
6
P1.6/PM_UCA0TXD/PM_UCA0SIMO
5
P1.7/PM_UCA0CLK/PM_UCB0STE/(ROSC) P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0
3
P2.1/PM_TA1CCR0A/CB1/A1
2
P2.2/PM_TA1CCR1A/CB2/A2
1
P2.3/PM_TA1CCR2A/CB3/A3
8
P2. /PM_RTCCLK/CB /A /VREF-/VEREF-
7
P2.5/PM_SVMOUT/CB5/A5/VREF+/VEREF+
6
P2.6/PM_ACLK/(RF_ATEST)
2
P2.7/PM_MODCLK/PM_DMAE0
23
P3.0/PM_CBOUT0/PM_TA0CLK
21
P3.1/PM_TA0CCR0A
20
P3.2/PM_TA0CCR1A
19
P3.3/PM_TA0CCR2A
18
P3. /PM_TA0CCR3A
17
P3.5/PM_TA0CCR A
16
P3.6/PM_RFGDO1
15
P3.7/PM_SMCLK
1
P5.0/XIN
P5.1/XOUT 3
PJ.0/TDO
35 PJ.1/TDI/TCLK 36 PJ.2/TMS 37 PJ.3/TCK 38
RF_N 30 RF_P 29
RF_XIN 25
RF_XOUT 26
R_BIAS 33
TEST/SBWTCK
39
VCORE 7
VSS VSS
U1
UEXT-1 UEXT-2 UEXT-3 UEXT- UEXT-5 UEXT-6 UEXT-7 UEXT-8 UEXT-9
UEXT-10
GND
1
VIN
2
VOUT 3
VR
MSP 30-CCRF Rev. A CO PYRIGHT(C) 2011, OLIMEX Ltd. http://www.olimex.com/dev
+
+
+
+
+
+
GND
0R 0R
0R
0R
UEXT POWER SUPPLY

BOARD LAYOUT:
POWER SUPPLY CIRCUIT:
MSP430-CCRF can take power from:
–External power supply ia PWR connector 3 - 12 VDC
–JTAG
The programmed board power consumption is about 25 mA with all peripherals
enabled.
RESET CIRCUIT:
MSP430-CCRF reset circuit includes R2 (330Ω), R1 (33k), C1 (2.2nF), JTAG
pin 11 and CC430F5137IRGZ pin 40 (#RST/SWBTDIO).
CLOCK CIRCUIT:
Quartz crystal Q 32.768 kHz is connected to CC430F5137IRGZ pin 44
(P5.0/XIN) and pin 43 (P5.1/XOUT).
Quartz crystal Q3 26 MHz is connected to CC430F5137IRGZ pin 25
(RF_XIN) and pin 26 (RF_XOUT).
Page 8

JUMPER DESCRIPTION:
J
This jumper, when is in position 1-2 – UEXT pin 3 (signal TX) is connected to
CC430F5137IRGZ pin 5 (signal BSLTX/UCA0TXD); when the jumper is in position 2-
3 - UEXT pin 3 (signal TX) is connected to CC430F5137IRGZ pin 6 (signal
BSLRX/UCA0RXD)
Default state is shorted in position 2-3.
J2
This jumper, when is in position 1-2 – UEXT pin 4 (signal RX) is connected to
CC430F5137IRGZ pin 6 (signal BSLRX/UCA0RXD); when the jumper is in position 2-
3 - UEXT pin 4 (signal RX) is connected to CC430F5137IRGZ pin 5 (signal
BSLTX/UCA0TXD)
Default state is shorted in position 2-3.
When jumpers J1 and J2 are shorted in position 1-2 – the board is configured as host and can
be used as host for some of our module boards. When these jumpers are shorted in
position 2-3 – the board is configured as de ice and can be used as module board.
INPUT/OUTPUT:
Status Led with name LED (red) connected to CC430F5137IRGZ pin 13
(P1.0/PM_RFGDO0).
User button with name BUT connected to CC430F5 37IRGZ pin 12
(P1.1/PM_RFGDO2).
Page 9

EXTERNAL CONNECTORS DESCRIPTION:
JTAG:
Pin # Signal Name Pin # Signal Name
1 TDO 2 JTAG power supply
3 TDI 4 VCC
5 TMS 6 Not Connected
7 TCK 8 TEST/SWBTCK
9 GND 10 Not Connected
11 #RST/SWBTDIO 12 BSLTX/UCA0TXD
13 Not Connected 14 BSLRX/UCA0RXD
PWR:
Pin # Signal Name
1 VIN
2 GND
Page 10