OLIMEX STM32-P107 User manual

STM32-P107 development board
User's manual
All boards produced by Ol mex are ROHS compl ant
Rev. G, December 2013
Copyr ght(c) 2013, OLIMEX Ltd, All r ghts reserved

DISCLAIMER
© 2013 Ol mex Ltd. Ol mex®, logo and comb nat ons thereof, are reg stered trademarks of Ol mex Ltd. Other product
names may be trademarks of others and the r ghts belong to the r respect ve owners.
The information in this document is provided in connection with Olimex products No license, express or implied
or otherwise, to any intellectual property right is granted by this document or in connection with the sale of
Olimex products
Th s hardware des gn of STM32-P107 s ne ther publ c not open-source. Any copy ng of the product would result n
copyr ght nfr ngement.
The software s released under open source terms regard ng the code wr tten by Ol mex. Every other else (l brar es,
ready-to-use-f les, etc) follow the r owner's copyr ght.
It s poss ble that the p ctures n th s manual d ffer from the latest rev s on of the board.
The product descr bed n th s document s subject to cont nuous development and mprovements. All part culars of the
product and ts use conta ned n th s document are g ven by OLIMEX n good fa th. However all warrant es mpl ed or
expressed nclud ng but not l m ted to mpl ed warrant es of merchantab l ty or f tness for purpose are excluded. Th s
document s ntended only to ass st the reader n the use of the product. OLIMEX Ltd. shall not be l able for any loss or
damage ar s ng from the use of any nformat on n th s document or any error or om ss on n such nformat on or any
ncorrect use of the product.
Th s evaluat on board/k t s ntended for use for eng neer ng development, demonstrat on, or evaluat on purposes only
and s not cons dered by OLIMEX to be a f n shed end-product f t for general consumer use. Persons handl ng the
product must have electron cs tra n ng and observe good eng neer ng pract ce standards. As such, the goods be ng
prov ded are not ntended to be complete n terms of requ red des gn-, market ng-, and/or manufactur ng-related
protect ve cons derat ons, nclud ng product safety and env ronmental measures typ cally found n end products that
ncorporate such sem conductor components or c rcu t boards.
Ol mex currently deals w th a var ety of customers for products, and therefore our arrangement w th the user s not
exclus ve. Ol mex assumes no l ab l ty for appl cat ons ass stance, customer product des gn, software performance, or
nfr ngement of patents or serv ces descr bed here n.
THERE IS NO WARRANTY FOR THE DESIGN MATERIALS AND THE COMPONENTS
USED TO CREATE STM32-P107 THEY ARE CONSIDERED SUITABLE ONLY FOR
STM32-P107
Page 2 of 19

INTRODUCTION
STM32-P107 prototype board prov des easy way for develop ng and prototyp ng w th the new
STM32F107VCT6 connect v ty l ne m crocontroller, produced by STM croelectron cs. STM32-
P107 has JTAG port for programm ng and debugg ng, USB_OTG, user button, two status LEDs,
and most of the GPIOs are on extens on headers where you can connect your add t onal c rcu ts.
BOARD FEATURES
- CPU: STM32F107VCT6 32 b t ARM-based m crocontroller w th 256 KB Flash, 64 KB RAM,
USB OTG, Ethernet, 10 t mers, 2 CANs, 2 ADCs, 14 commun cat on nterfaces
- JTAG connector w th ARM 2x10 p n layout for programm ng/debugg ng
- USB_OTG connector
- USB_HOST connector
- 100Mb t Ethernet
- RS232
- M n SD/MMC card connector
- UEXT connector
- Power jack
- Two user buttons
- RESET button and c rcu t
- Two status LEDs
- Power-on LED
- 3V battery connector
- Extens on port connectors for many of m crocontrollers p ns
- PCB: FR-4, 1.5 mm (0,062"), soldermask, s lkscreen component pr nt
- D mens ons: 132.08x96.52mm (5.2x3.8")
ELECTROSTATIC WARNING
The STM32-P107 board s sh pped n protect ve ant -stat c packag ng. The board must not be
subject to h gh electrostat c potent als. General pract ce for work ng w th stat c sens t ve dev ces
should be appl ed when work ng w th th s board.
Page 3 of 19

BOARD USE REQUIREMENTS
Cables: The cable you w ll need depends on the programmer/debugger you use. If you use ARM-
JTAG, you w ll need LPT cable, f you use ARM-USB-OCD, ARM-USB-OCD-H, ARM-USB-
TINY, or ARM-USB-TINY-H you w ll need 1.8 meter USB A-B cable, for ARM-USB-OCD and
ARM-USB-OCD-H you w ll need RS232 cable, too.
Hardware: Programmer/Debugger – one of the Ol mex ARM Programmers: ARM-JTAG, ARM-
JTAG-EW, ARM-USB-OCD, ARM-USB-OCD-H, ARM-USB-OCD-TINY, ARM-USB-OCD-H.
Note that Ol mex OpenOCD debuggers lack SWD nterface by default. There s the adapter ARM-
JTAG-SWD that adds SWD to any of the programmers/debuggers ment oned above.
Add t onally you can use our ARM-JTAG-COOCOX debugger wh ch has both JTAG and SWD
nterfaces and works w th CooCox IDE nat vely and w th IAR EW and Ke l uV s on v a plugg ns.
Software: ARM C comp ler
PROCESSOR FEATURES
STM32-P107 board uses the ARM-based 32-b t m crocontroller STM32F107VCT6 w th the
follow ng features:
–Core: ARM 32-b t Cortex™-M3 CPU
–72 MHz max mum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wa t
state memory access
–S ngle-cycle mult pl cat on and hardware d v s on
–Memor es
–256 Kbytes of Flash memory
–64 Kbytes of SRAM
–Clock, reset and supply management
–2.0 to 3.6 V appl cat on supply and I/Os
–POR, PDR, and programmable voltage detector (PVD)
–25 MHz crystal osc llator
–Internal 8 MHz factory-tr mmed RC
–Internal 40 kHz RC w th cal brat on
–32 kHz osc llator for RTC w th cal brat on
–Low power
–Sleep, Stop and Standby modes
–VBAT supply for RTC and backup reg sters
–2 × 12-b t, 1 µs A/D converters (16 channels)
–Convers on range: 0 to 3.6 V
–Sample and hold capab l ty
–Temperature sensor
–up to 2 MSps n nterleaved mode
–2 × 12-b t D/A converters
–DMA: 12-channel DMA controller
–Supported per pherals: t mers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
Page 4 of 19

–Debug mode
–Ser al w re debug (SWD) & JTAG nterfaces
–Cortex-M3 Embedded Trace Macrocell™
–80 fast I/O ports
–80 I/Os, all mappable on 16 external nterrupt vectors and almost all 5 V-tolerant
–10 t mers
–four 16-b t t mers, each w th up to 4 IC/OC/PWM or pulse counter and quadrature
( ncremental) encoder nput
–1 × 16-b t motor control PWM t mer w th dead-t me generat on and emergency stop
–2 × watchdog t mers (Independent and W ndow)
–SysT ck t mer: a 24-b t downcounter
–2 × 16-b t bas c t mers to dr ve the DAC
–14 commun cat on nterfaces
–2 × I2C nterfaces (SMBus/PMBus)
–5 USARTs (ISO 7816 nterface, LIN, IrDA capab l ty, modem control)
–3 SPIs (18 Mb t/s), 2 w th a mult plexed I2S nterface that offers aud o class accuracy v a
advanced PLL schemes
–2 × CAN nterfaces (2.0B Act ve) w th 512 bytes of ded cated SRAM
–USB 2.0 full-speed dev ce/host/OTG controller w th on-ch p PHY that supports
HNP/SRP/ID w th 1.25 Kbytes of ded cated SRAM
–10/100 Ethernet MAC w th ded cated DMA and SRAM (4 Kbytes): IEEE1588 hardware
support, MII/RMII ava lable on all packages
–CRC calculat on un t, 96-b t un que ID
Page 5 of 19

Page 6 of 19

Page 7 of 19

SCHEMATIC
0
STATUS LEDS RESET CIRCUIT
BUTTONS
USB CIRCUIT
RS232
UEXT
USB_HOST
USB_OTG
JTAG SD/MMC
POWER SUPPLY C RCUIT
6VAC
(6 9)VDC
1
01
O H
O
O
H
H
Ethernet
STM32-P107, board revision C
OLIMEX LTD, PLOVDIV, BULGARIA 2013
https: /www.olimex com
STM32-P107, board revision C
OLIMEX LTD, PLOVDIV, BULGARIA 2013
https: /www.o imex com
V 3 3V 3 3VA
1 2
3 3VA_E
C OSE
12
33VA_MCU_E
COSE
12
3 3V_E
C OSE
1
2
3 3V_MCU_E
C OSE
1
2
3V_BA
W 2S
AGND
1 2 3
B0_0 B0_1
N1x3
1 2 3
B1_0 B1_1
HN1x3
1 2
BOO 0_E
HN1x2 Open)
C1
100n
C2
100n
C3
47u63V
C4
100n
C
100n
100n
C7
10u
C
100n
C9
10u 6 3
C10
100n
C11
NA(47 )
C12
NA(47p )
C13
100n
C14 100n
C1
2 2u 6 3V
C16
100n
C17 NA
C18
27p
C19
27p
C2022u 6 3V
C21 10p
C2222u 6 3V
C23 10p
24100n
C2
22u63V
C26
22u
27
100n
28
100n
C2
22u63V
C30
100
C31
22u63V
C32
100n C33
100n
C34
100n
C3
100n
C36
100n
C37
100n
C38
100n
C39
100n
C40
470u 16VDC
C41
22u63V
C42
100n
C43
100n
C44
100n
C4
22u
C4
22u
4
100n
C4
22u
C4
22u
C
22u
C
22u
C 2
0V
C 3
0V
C 4
100n
C 10u 6 3V
VDD
VSS OU
E D 1
3
4
2
CD1
NA 6NC2- 0MHz)
D1
BA 4C
D
1N41
D3
1N4148
D4 1N 819S
D 1N 819S
D6 1N 819S
G1
0
GND
1 2
GNDA_E
C OSE
GND_
1 2
3 4
6
7 8
9 10
11 12
13 14
1 16
17 18
19 20
J AG
BH20S
1
0 0 00 00 0 9 0
2
0 0 00 0 0 9 0
3
0 0 00 00 0 9 0
4
0 0 0 0
B0 0 00 00 0 9 0
V
RJ4 SDE
1
4
2
3
7
8
6
Y W
AG
AG
A
A
COM
3
GND1 GND2
KG
KG
K
K
NC
6
RD
7
RD-
8
D
1
D-
2
AN
RJ BC 060 C1
V
V
A3
A
B1
B2
B3
B
B6
B7
B9
B11
C1
C2
C3
C4
C
C6
C7
C8
C9
C10
C11
D1
D2
D3
D4
D
D6
D7
D10
D11
D12
D13
D14
D1
E1
E2
E3
E4
E
E6
E7
E8
E9
E10
E11
E12
E13
E14
WR_JACK
D -1136
WR_ ED
ED RED 0603
Q1
0 0 9 0
Q2
32768Hz
1 2
R-
O EN
0R Boa d_Mounted)
R1
0
R2 22R
R322R
R422k
R33k
R6 33k
R722R
R8 22R
0R9
0R
R10 10k
R11
NA
R121M
R1310k
R14
NA
R133k
R16 1 R1733k
R1833k
R1
NA
R20 2 2k
R21 330R
R22
499R1%
R23
499R1%
R24
499R1%
R2
499R1%
R
49R1%
0R27
0B
R28 10k
R29 NA
R30
10k
R31 1
R3222k
R33
49R 1%
R34
330R R3
100R 1%
R36
100R 1%
R3733k
R38
330R
R39
330R
R40
330R
R41
33k
R42 NA R43
4 7k R44
4 7k
R4
33k
R46
2 2k
R47
10k
R48
10k
R49
100R 1%
R 0
0R 1
2 2k
R 2
2 2k
R 3
330R
R 4
100R 1%
R
300R 1%
R 6
90
RESE
0
RM1G1
RA1206_( x0603)_4B8_ 0k
RM1G2
RA1206_( x0603)_4B8_ 0k
RM1G3
RA1206_( x0603)_4B8_ 0k
RM1G4
RA1206_( x0603)_4B8_ 0k
RM2G1
RA1206_ 4x0603 _4B8_10k
RM2G2
RA1206_ 4x0603 _4B8_10k
RM2G3
RA1206_ 4x0603 _4B8_10k
RM2G4
RA1206_ 4x0603 _4B8_10k
RM3G1
0 0 0 B
RM3G2
0 0 0 B
RM3G3
0 0 0 B
RM3G4
0 0 0 B
M G1
0 0 0 B
0 0 0
M G30 0 0 B
M G40 0 0 B
1
2
3
4
6
7
8
9
RS1
RS
1 2
RS _E
HN1x2(Open)
CD DA
2
C K SC K
CMD D
3
DA 0 DO
7
DA 1 RES
8
DA 2 R
1
VDD
4
VSS
6
SD MMC
MICRO
SA1
0 0
SA2
Y W 0 0
1
D A 14 KA
2
DC114KA
AM ER
0
U1
S M32 107VC 6
BOO 0
94
NC
73
NRS
14
OSC_IN
12
OSC_OU
13
A0 KU USA _ S ADC 2_IN0 IM2_CH1_E R IM _CH1E H_M I_C S_WKU
23
A1 SAR 2_R A 1 M H M _CH2 E H_MI _RX_C K E H_ MI RE C
24
A2 SAR 2_ X I C 1 _ N2 M2_CH3 E H_MI _MD OE H_ MI MD O
2
A3 SAR 2_RX IM _CH4 ADC12_ N3 M2 CH4 E H_MI _CO
26
A4 1_NSS D USAR 2_CK ADC12_ 4
29
A S 1_SCKDAC_OU 2 ADC1 _IN
30
A6 S 1_M SO ADC12_IN6 M3_CH1 IM1_BK N
31
A7 S 1_MOSI ADC12_IN7 M3_CH2 E H_MI RX_DV E H_RM I_CRS DV M _CH N
32
A8 USAR 1_CK O G_ S_SO M1_CH1 MCO
67
A9 USAR 1_ X IM1_CH2 O G_ S_VBUS
68
A10 USAR 1_RX IM1_CH3 O G_ S_ D
69
A11 USAR 1_C S CAN1_RX IM1_CH4 O G_ S_DM
70
A1 USAR 1_R S 1_ X M1_E R O G_ S_D
71
A1 J MS SWDI
72
A1 J CK SWC
76
A1 J DI S 3_NSS M2 CH1_E R S I1_NSS
77
B0 DC12_ N8 M3 CH3 E H_MI _RXD2 IM1_CH2N
3
B1 DC12_ N9 M3 CH4 E H_MI _RXD3 IM1_CH3N
36
B2 OO 1
37
B3 J DO S 3_SCK RACESWO M2_CH2 S I1 SCK
89
B4 JN RS S I3_MISO IM3_CH1 S 1_MISO
90
B 2C1_SMBA S I3_MOSI E H_M I_ S_OU E H_RM I_ S_OU IM3_CH2S 1_MOSI CAN2_RX
91
B6 2C1_SC M _CH1USAR 1_ X CAN2_ X
92
B7 2C1_SDA M4_CH2 USAR _RX
93
B8 M4_CH3 E H_MI _ XD3 2C1_SC CAN1_RX
9
B9 M4_CH4 2 _ AN1_ X
96
B1 2C2_SC USAR 3_ X E H_M I_RX_ER IM2_CH3
47
B1 2C2_SDA S 3 E M _ X_EN E H_RMI_ X_EN IM2_CH4
48
B1 S 2_NSS S W 2 M A USAR 3_CK M _BK NCAN2_RX E H_M I X M D0
1
B1 S 2_SCK S R _ S M1 CH1NCAN2_ X E H_MI _ XD1 E H_ MI D
2
B1 S 2_MISO M1_CH N USAR 3_R S
3
B1 S 2_MOS _ M _CH3N
4
C DC12_IN10
1
C1 ADC12_IN11 E H_MI _MDC E H_RM I_MDC
16
C2 ADC12_IN12 E H_MI _ XD2
17
C3 ADC12_IN13 E H_MI _ X_C K
18
C4 ADC12_IN14 E H_MI _RXD0E H_RMI _RXD0
33
C ADC12_IN1 E H_MI _RXD1 E H_RMI _RXD1
34
C6 2S2_MCK M _C 1
63
C7 2S3_MCK M _C 2
64
C M _CH3
6
C M _CH4
66
C UAR 4_ X S S I _SCK
78
C UAR 4_RX X S I3_MISO
79
C UAR _ X S S I3_MOSI
80
C AM ER-R
7
C OSC32_ N
8
C OSC32_OU
9
D0 OSC_INCAN1_RX
81
D1 OSC_OU CAN1_ X
82
D2 M _E R UAR _RX
83
D3 USAR 2_C S
84
D4 USAR 2_R S
8
D SAR 2_ X
86
D SAR 2_RX
87
D SAR 2_CK
88
D SAR 3_ X M R _DV
D SAR 3_RX _M X D0
6
D USAR 3_CK E H_M I_RX_D1
7
D USAR 3_C S E H_M I_RX_D2
8
D 2 M4_CH1USAR 3_R S E H_M I_RX_D3
9
D 3 M4_CH2
60
D 4 M4_CH3
61
D M4_CH4
62
E0 IM4_E R
97
E1
98
E2 RACECK
1
E3 RACED0
2
E4 RACED1
3
E RACED2
4
E6 RACED3
E7 IM1_E R
38
E8 IM1_CH1N
39
E9 IM1_CH1
40
E10 IM1_CH2N
41
E11 IM1_CH2
42
E12 IM1_CH3N
43
E13 IM1_CH3
44
E14 IM1_CH4
4
E1 IM1_BKI N
46
VBA
6
VDD
0
VDD
7
VDD
100
VDD
28
VDD
11
VDDA
22
VRE
21
VRE -
20
VSS
49
VSS
74
VSS
99
VSS
27
VSS
10
VSSA
19
1
2
34
6
U2
B
U3
M C2026-1 M
ENA
1
ENB
4
AG_A
2
AG_B
3GND 6
IN 7
OU _A
8
OU B
U4
AN8710A-EZC
CO CRS_DV MODE2
1
CRS
14
GND
ED1 R
3
ED2 N
2
MDC
17
MDIO
16
N N XER XD4
18
NRS
19
RB AS
32
RXC K H AD1
7
RXD0 MODE0
11
RXD1 MODE1
10
RXD2 RMISE
9
RXD3 H AD2
8
RXDV
26
RXERRXD4 H AD0
13
RXN
30
RX 31
XC K
20
XD0
22
XD1
23
XD2
24
XD3
2
XEN
21
XN28
X29
VDD1A
27
VDD2A
1
VDDCR
6
VDDIO
12
X A 1 C KIN
XA2
4
C1
1
C1-
3
C2
4
C2-
R1I N 3
R1OU
12
R2I N 8
R2OU
9
1 N
11 1OU 4
2 N
10 2OU 7
V2
V- 6
U
S 3232BDR(SO16)
V16
U WR
GND
VCC RESE
3
12
U6
NA S M1001RWX6 )
1 2
3 4
6
7 8
9 10
UEX
BH10S
12
UEX _ WR_E
C OSE
1 2 3
USB_D
HN1 3 O C ose H Open)
1 2 3
USB_D-
HN1x3(O Close H Open)
USB
1
2
3
4
USB_HOS
USB_A
USB
D
D-
GND
GN GN
GND3 GND4
ID
VBUS
USB_O G
M CRO_AB
3 3V
3 3V
3 3V
3 3V
33V
3 3V
3 3V
3 3V
3 3V
3 3V
3 3V
3 3V
3 3V
3 3V
3 3V
3 3V
3 3VA
3 3V
3 3VA
3 3V 3 3V
3 3V
3 3V
3 3V
3 3V
3 3V
VBA
1 2 3
VBUS
HN1x3(O Cose H Open)
VR1( 0V)
AME108
GNDADJ
1
VI
3VO 2
ADJ GND
N OU
VR2(3 3V)
M1117IM X-ADJ
VRE
VRE -
WKU
0
S 3_SCK S 3_MOSI S I3_MI SO CS_UEX I2C1_SC 2C1_SDA USAR 3_ X USAR 3_RX S I1_NSS S I1_SCK S I1_MISO S I1_MOSI USAR 2_ X USAR 2_RX USAR 2_R S USAR 2_C S
V_EX
V_HOS _ WR
V_HOS _ WR
V_HOS _ WR
V_J AG
V_J AG
V_O G_ WR
V_O G_ WR
V_O G_ WR
V_O G_ WR
BOO 0
BOO 0
CS_MMC CS_MMC
CS_MMCCS_MMC
CS_UEX
CS_UEX CS_UEX
E H_RMII_CRS_DV E H RM I_CRS_DV
E H_RMII_CRS_DV E H_RMI _CRS_DV
E H_RMII_MDC E H_RMII_MDC
E H_RMII_MDC E H_RMI _MDC
E H_RMII_MD N
E H_RMII_MD N E H_RMI _MD N
E H_RMII_MD O E H_RMII_MD O
E H_RMII_MD O E H_RMI _MD O
E H_RMII_RE _C K E H_RMII_RE _C K
E H_RMII_RE _C K E H_RMI_RE _C K
E H_RM I_RE _C K
E H_RMII_RXD0 E H_RM II_RXD0
E H_RMII_RXD0 E H_RMI _RXD0
E H_RMII_RXD1 E H_RM II_RXD1
E H_RMII_RXD1 E H_RMI _RXD1
E H_RMII_ XD0 E H_RMII_ XD0
E H_RMII_ XD0 E H_RMI _ XD0
E H_RMII_ XD1 E H_RMII_ XD1
E H_RMII_ XD1 E H_RMI _ XD1
E H_RMII_ X_EN E H_RMII_ X_EN
E H_RMII_ X_EN E H_RMI _ X_EN
I2C1_SC
2C1_SC 2C1_SC
I2C1_SDA
2C1_SDA 2C1_SDA
O G_DM
O G_DM
O G_D
O G_D
O G_ID
O G_ID
O G_ID
O G_VBUS
O G_VBUS
B2 BOO 1
B2 BOO 1
C_C S
C_DCD
C_R S
C_RXD
C_ XD
H AD0
H AD0
H AD1
H AD1
H AD2
H AD2
H _SO _RS H _SO _RS
H _SO _RS
RMI SE
RM ISE
RS
RS
RS
RS
S I3_M SO S I3_M SO
S 3_MISO
S 3_MISS 3_MI SO
S I3_MOSI S I3_MOSI
S 3_MOSI
S 3_MOSIS 3_MOSI
S I3_SCK S I3_SCK
S 3_SCK
S 3_SCK
SA1
SA1
SA2
SA2
AM ER
AM ER
CK
CK CK
DI
DI
DO
DO DO
MS
MS MS
RS
RS
RS RS
USAR 2_C SUSAR 2_C S
USAR 2_C S
USAR 2_R SUSAR 2_R S
USAR 2_R S
USAR 2_RX USAR 2_RX
USAR 2_RX
USAR 2_ X USAR 2_ X
USAR 2_ X
USAR 3_RX USAR 3_RX
USAR 3_RX
USAR 3_ X USAR 3_ X
USAR 3_ X
USB_ AU
USB_ AU
USB_HOS _D
USB_HOS _D
USB_HOS _D
USB_HOS _D-
USB_HOS _D-
USB_HOS _D-
USB_O G_D
USB_O G_D
USB_O G_D
USB_O G_D-USB_O G_D- USB_O G_D-
USB_VBUSON
USB_VBUSON
WKU
WKU

BOARD LAYOUT
POWER SUPPLY CIRCUIT
STM32-P107 can take power from three sources:
–PWR connector where (6.5-9)V DC or 6V AC s appl ed by external power source.
–+5V_ OTG-PWR from USB OTG
–+5V_JTAG from JTAG
The programmed board power consumpt on s about 70 mA.
RESET CIRCUIT
STM32-P107 reset c rcu t ncludes JTAG connector p n 15, U2 (STE101P) p n 28 (RESET), R73(10k),
R74(330Ohm), R75(100Ohm/1%), C55(100nF), STM32F107 p n 14 (NRST) and RESET button.
CLOCK CIRCUIT
Quartz crystal 25 MHz s connected to STM32F107 p n 12 (OSC_IN) and p n 13 (OSC_OUT).
Quartz crystal 32.768kHz s connected to STM32F107 p n 8 (PC14/OSC32_IN) and p n 9
(PC15/OSC32_OUT).

JUMPER DESCRIPTION
PWR_SEL
When pos t on 1-2 s shorted – the board s power suppl ed from JTAG.
When pos t on 3-4 s shorted – the board s power suppl ed from USB_OTG.
When pos t on 5-6 s shorted – the board s power suppl ed from External power
source.
Default state s – pos t on 5-6 – shorted.
B0_0/B0_1
When th s jumper s n pos t on B0_1 – BOOT0 s connected to 3.3V, and when the
jumper s n pos t on B0_0 – BOOT0 s connected to GND.
Default state s B0_0.
B1_0/B1_1
When th s jumper s n pos t on B1_1 – BOOT1 s connected to 3.3V, and when the
jumper s n pos t on B1_0 – BOOT1 s connected to GND.
Default state s B1_0.
VBUS
When s n pos t on “H” - connects +5V_HOST_PWR to OTG_VBUS.
When s n pos t on “O” - connects +5V_OTG_PWR to OTG_VBUS.
Default state s “O”.
USB_D+
When s n pos t on “H” - connects USB_HOST_D+ to OTG_DP.
When s n pos t on “O” - connects USB_OTG_D+ to OTG_DP.
Default state s “O”.
USB_D-
When s n pos t on “H” - connects USD_HOST_D- to OTG_DM.
When s n pos t on “O” - connects USB_OTG_D- to OTG_DM.
Default state s “O”.
PWDW_D
When s closed – d sables Ethernet transce ver (STE101P) Power Down Mode. STE101P
s act ve.
Default state s closed.

3 3V_MCU_E
Enable m crocontroller 3.3V power supply
Default state s closed.
3 3V_E
Enable regulator VR2 (3.3V) - LM1117
Default state s closed.
3 3VA_E
Enables board 3.3V analog power supply.
Default state s closed.
3 3VA_MCU_E
Enables m crocontroller 3.3V analog power supply.
Default state s closed.
GNDA_E
Enables board analog GND.
Default state s closed.
R-T
Connects RST to TRST
Default state s open.
RST_E, BOOT_E jumpers
Note that t s recommended to move those jumpers together – e ther both should be
open or both should be closed.
When both are closed RS232 boot s enabled.
Default states are RST E – open; BOOT E – open.
INPUT/OUTPUT
Status LED1 (green) w th name STAT1 connected to STM32F107 p n 63
(PC6/I2S2_MCK/TIM3_CH1).
Status LED2 (yellow) w th name STAT2 connected to STM32F107 p n 64
(PC7/I2S3_MCK/TIM3_CH2).
Power-on LED (red) w th name PWR – th s led shows that +3.3V s appl ed to the board.
User button w th name WKUP connected to STM32F107 p n 23 (PA0/WKUP).
User button w th name TAMPER connected to STM32F107 p n 7 (PC13/TAMPER-RTC).
Reset button w th name RESET connected to STM32F107 p n 14 (NRST).

CONNECTOR DESCRIPTIONS
JTAG
The JTAG connector allows the software debugger to talk v a a JTAG (Jo nt Test Act on Group) port
d rectly to the core. Instruct ons may be nserted and executed by the core thus allow ng STM32F107
memory to be programmed w th code and executed step by step by the host software.
For more deta ls please refer to IEEE Standard 1149.1 - 1990 Standard Test Access Port and Boundary
Scan Arch tecture and STM32F107 datasheets and users manual.
Pin # Signal name Pin # Signal name
1 3.3V 2 3.3V
3 TRST 4 GND
5 TDI 6 GND
7 TMS 8 GND
9 TCK 1 GND
11 PULL-DOWN 12 GND
13 TDO 14 GND
15 RST 16 GND
17 PULL-DOWN 18 GND
19 +5V_JTAG 2 GND

PWR_JACK
Pin # Signal name
1 Power input
2 GND
USB_HOST
Pin # Signal name
1 +5V_HOST_PWR
2 USB_HOST_D-
3 USB_HOST_D+
4 GND
USB_OTG
Pin # Signal name
1 +5V_OTG_PWR
2 USB_OTG_D-
3 USB_OTG_D+
4 OTG_ID
5 GND
3V_BAT
Pin # Signal name
1 VBAT
2 GND

RS232
The RS232 port can be used for commun cat on when n bootloader mode. To enter bootloader mode you
need to close RST_E and BOOT0_E jumpers. Note that the default pos t on of those jumpers s closed,
e.g. bootloader mode d sabled.
Pin # Signal name
1 NC
2 T1OUT
3 R1IN
4 NC
5 GND
6 NC
7 CTS
8 RTS
9 NC
UEXT
Pin # Signal name
1 3.3V
2 GND
3 USART2_TX
4 USART2_RX
5 I2C1_SCL
6 I2C1_SDA
7 SPI3_MISO
8 SPI3_MOSI
9 SPI3_SCK
1 CS_UEXT

LAN
Pin # Signal name chip side Pin # Signal name chip side
1 TX+ 5 Not connected (NC)
2 TX- 6 VDD
3 VDD 7 RX+
4 Not connected (NC) 8 RX-
LED Color Usage
Right Green Link status
Left Yellow Activity status
SD/MMC
Pin # Signal name
1 MCIDAT2
2 CS_MMC
3 SPI3_MOSI
4 3.3V
5 SPI3_SCK
6 GND
7 SPI3_MISO
8 MCIDAT1
9 Not connected
1 Not connected
11 Not connected
12 Not connected

MECHANICAL DIMENSIONS
All measures are n m ls.
AVAILABLE DEMO SOFTWARE
All demo examples are ava lable at the board's web-page
(https://www.ol mex.com/Products/ARM/ST/STM32-P107/) and w k art cle
(https://www.ol mex.com/w k /STM32-P107). Make sure that the demo you download s compat ble w th
the board rev s on you have! The board rev s on s pr nted on STM32-P107 tself.

REVISION AND ORDERING INFORMATION
STM32-P107 – fully assembled and tested
Ma ual revisio history:
REV. I - created December 2009
REV. A - ed ted by TU December 2010
REV. B - demo software added and mechan cal d mens ons deta le
REV. C - rev. A schemat c and added more programmers n BOARD USE
REQUIREMENTS.
REV. D - ed ted June 2011 – changed schemat c
REV. E - changed schemat cs to rev. B, added board rev s on h story
REV. F - added BOOT0_E, RST_E descr pt on, changed d mens ons, updated
rev s on B p ctures, updated d scla mer
REV.G - updated the nformat on to f t board rev s on C, updated schemat cs,
mproved document layout, added product support nformat on, updated
l nks
Board revisio history:
rev. A
========
1. ST2052BD s exchanged w th LM3526-L.
2. SD/MMC s gnals are changed as follows:
SPI1_MOSI -> SPI3_MOSI
SPI1_SCK -> SPI3_SCK
SPI1_MISO -> SPI3_MISO
and SPI1_NSS renamed to CS_MMC
3. Changed the polar ty to + of C36
rev. B
========
1. All element l brar es are now updated
2. Ethernet PHY s changed from STE101P to MICREL's one - KS8721BLMM
3. All 10uF/6.3V/TANT are changed to 0805 and a lot of element names are changed.
4. PWR_SEL jumpers are replaced by d odes.
5. USART3 s connected to UEXT wh le USART2 s connected to RS232 and bootloader funct onal ty s
enabled! Two add t onal jumpers are added!!!
6. Added UEXT_PWR_E jumper!
7. A lot jumpers are added nto jumpers descr pt on table

rev. C
========
1. L2 s now placed further from USB_HOST connector to avo d contact
2. Ethernet PHY M crel KS8721 s changed to LAN8710A-EZC n RMII
3. Changed C18 from 100n to 4.7uF/6.3V accord ng to the datasheet. C18 s now renamed C3.
4. STAT1, STAT2 and PWR_LED were changed to 0603 and ts res stors to 2.2k.
5. SD/MMC capac tor was replaced by 2x22uF/6.3V capac tors.
6. LM3526 was exchanged w th MIC2026-1YM and connect on between p n 1 and p n4 was swapped
because the default EN level s oppos te.
7. All tantalum capac tors are changed to ceram c.
8. Opt m zat ons n the values of few other elements as well.
9. R28(0R) was changed to 10k, C55=10uF/6.3V was added and RST connect on was removed from the
PHY!