ON Semiconductor NCN49597 User manual

©Semiconductor Components Industries, LLC, 2011
December, 2011 −Rev. P0
1Publication Order Number:
NCN49597/D
NCN49597
Product Preview
Power Line Carrier Modem
ON Semiconductor’s NCN49597 is an IEC 61334−5−1 compliant
power line carrier modem using spread−FSK (S−FSK) modulation for
robust low data rate communication over power lines. NCN49597 is
built around an ARM processor core, and includes the MAC layer.
With this robust modulation technique, signals on the power lines can
pass long distances. The half−duplex operation is automatically
synchronized to the mains, and can be up to 4800 bits/sec.
The product configuration is done via its serial interface, which
allows the user to concentrate on the development of the application.
The NCN49597 is implemented in ON Semiconductor mixed signal
technology, combining both analog circuitry and digital functionality
on the same IC.
Features
•Power Line Carrier Modem for 50 and 60 Hz Mains
•Fully compliant to IEC 61334−5−1 and CENELEC EN 50065−1
•Complete Handling of Protocol Layers Physical to MAC
•Programmable Carrier Frequencies in CENELEC A-Band from 9 to
95 kHz; B−Band from 95 to 125 kHz, in 10 Hz Steps
•Half Duplex
•Data Rate Selectable:
300 – 600 – 1200 −2400 – 4800 baud (@ 50 Hz)
360 – 720 – 1440 −2880 – 5760 baud (@ 60 Hz)
•Synchronization on Mains
•Repetition Algorithm Boost the Robustness of Communication
•SCI Port to Application Microcontroller
•SCI Baudrate Selectable: 9.6 – 19.2 – 38.4 −115.2 kb
•Power Supply 3.3 V
•Ambient Temperature Range: −40°C to +80°C
•These Devices are Pb−Free and are RoHS Compliant*
Typical Applications
•ARM: Automated Remote Meter Reading
•Remote Security Control
•Streetlight Control
•Transmission of Alerts (Fire, Gas Leak, Water Leak)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
ON
e3
ARM
See detailed ordering and shipping information in the package
dimensions section on page 27 of this data sheet.
ORDERING INFORMATION
XXXX = Date Code
Y = Plant Identifier
ZZ = Traceability Code
http://onsemi.com
MARKING DIAGRAMS
152
QFN52 8x8, 0.5P
CASE 485M
XXXXYZZ
NCN 49597
C597−901
1
52

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APPLICATION
Application Example
PC201 11120 .1
TX_OUT
NCN49597
TX_ENB
ZC_IN
REF_OUT
RX_IN
RX_OUT
XTAL _I N
XTAL_OUT
Appli
&
Metering
mC
TXD
RXD
BR0
BR1
RESB
VSSA
VSS
T_REQ
VDD
VDDA
3V3_A 3V3_D
1:2 C1
R1
C2
R2
CDREF
C16 C17
3V3_A
D5
D1
D2
D3
D4
R12
C11
C12
R14
C15
C14
Y1
NCS5650
Enable
C3
C4
C6
C7
R6
R5R4
R7
R9
R10
2
Vcom
+B
−B
+A
−A
OutA
OutB 8
9
13
12 5
4
3
1
67
VCC
10 11
VEE
Vuc
19
151420
GNDuC
Rlim
Vwarn
3V3_D12V
R11
C5
C10
C9
12V
R3
MAINS
Tr
C8
C13
U1
U2
3V 3_D
VDD1V8
R8
SEN
EXT_CLK_E
Figure 1. Typical Application for the NCN49597S−FSK Modem
Figure 1 shows an S−FSK PLC modem build around
NCN49597. For synchronization the line frequency is
coupled in via a 1 MWresistor. The Schottky diode pair D5
clamps the voltage within the input range of the zero cross
detector. In the receive path a 2nd order high pass filter
blocks the mains frequency. The corner point defined by C1,
C2, R1and R2is designed at 10 kHz. In the transmit path a
3th order low pass filter build around the NCS5650 power
operational amplifier suppresses the 2nd and 3rd harmonics
to be in line with the CENELEC EN 50065−1 specification.
The filter components are tuned for a space and mark
frequency of 63.3 and 74 kHz respectively. The output of the
amplifier is coupled via a DC blocking capacitor C10 to a 2:1
pulse transformer Tr. The secondary of this transformer is
coupled to the mains via a high voltage capacitor C11. High
energetic transients from the mains are clamped by the
protection diode combination D3, D4together with D1, D2.
Because the mains is not galvanic isolated care needs to be
taken when interfacing to a microcontroller or a PC!
Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION
Component Function −Remark Typ Value Tolerance Unit
C1, C2High pass receive filter 1.5 ±10% nF
C5, CDREF VREF_OUT ; VREF_OUT decoupling cap −ceramic 1−20 +80% mF
C7, C9, C16, C17 Decoupling block capacitor 100 −20 +80% nF
C3TX_OUT coupling capacitor 470 ±20% nF
C4Low pass transmit filter 470 ±10% pF
C6Low pass transmit filter 68 ±10% pF
C8Low pass transmit filter 3±10% pF
C10 TX coupling cap; 1 A rms ripple @ 70 kHz 10 ±20% mF

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Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION
Component UnitToleranceTyp ValueFunction −Remark
C11 High Voltage coupling capacitor; 630 V 220 ±20% nF
C12 Zero Cross noise suppression 100 ±20% pF
C13, C14 X−tal load capacitor 22 ±20% pF
C15 Decoupling block capacitor 1.8 V internal supply 1−20 +80% mF
R1High pass receive filter 22 ±1% kW
R2High pass receive filter 11 ±1% kW
R3, R9, R12, R13 High pass receive filter; Alarm current ; Pull up 10 ±1% kW
R4Low pass transmit filter 3,3 ±1% kW
R5Low pass transmit filter 10 ±1% kW
R6Low pass transmit filter 8,2 ±1% kW
R7Low pass transmit filter 500 ±1% W
R8Low pass transmit filter 3±1% kW
R10 TX Coupling resistor ; 0.5 W 0,47 ±1% W
R11 Zero Cross coupling HiV 1±5% MW
D1, D2High current Schottky Clamp diodes MBRA430
D3, D4TVS diodes P6SMB6.8AT3G
D5Double low current Schottky clamp diode BAS70−04
Y1 X−tal 48 MHz
Tr 2:1 Pulse transformer
U1 PLC modem NCN49597
U2 Power Operational Amplifier NCS5650
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating Symbol Min Max Unit
ABSOLUTE MAXIMUM RATINGS SUPPLY
Power Supply Pins VDD, VDDA, VSS, VSSA
Absolute max. digital power supply VDD_ABSM VSS −0.3 3.9 V
Absolute max. analog power supply VDDA_ABSM VSSA −
0.3
3.9 V
Absolute max. difference between digital and analog power supply VDD −VDDA_ABSM −0.3 0.3 V
Absolute max. difference between digital and analog ground VSS −VSSA_ABSM −0.3 0.3 V
ABSOLUTE MAXIMUM RATINGS NON 5V SAFE PINS
Non 5V Safe Pins: TX_OUT, ALC_IN, RX_IN, RX_OUT, REF_OUT, ZC_IN, XIN, XOUT, TDO, TDI, TCK, TMS, TRSTB, TEST
Absolute maximum input for normal digital inputs and analog inputs VIN_ABSM VSS −0.3 VDD + 0.3 V
Absolute maximum voltage at any output pin VOUT_ABSM VSS −0.3 VDD + 0.3 V
ABSOLUTE MAXIMUM RATINGS 5V SAFE PINS
5V Safe Pins: TX_ENB, TXD, RXD, BR0, BR1, IO3 .. IO11, RESB
Absolute maximum input for digital 5V safe inputs V5VS_ABSM VSS −0.3 6.0 V
Absolute maximum voltage at 5V safe output pin VOUT5V_ABSM VSS −0.3 3.9 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

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Normal Operating Conditions
Operating ranges define the limits for functional operation and parametric characteristics of the device as described in the
Normal Operating Conditions section and for the reliability specifications as listed in Detailed Hardware Description section.
Functionality outside these limits is not implied.
Total cumulative dwell time outside the normal power supply voltage range or the ambient temperature under bias, must be
less than 0.1% of the useful life as defined in Detailed Hardware Description section.
Table 3. OPERATING RANGES
Rating Symbol Min Max Unit
Power supply voltage range VDD 3.0 3.6 V
Ambient Temperature TA−25 80 °C
Extended Ambient Temperature on special request TA−40 80 °C
PIN DESCRIPTION
QFN Packaging
AMIS49597
1
2
3
4
5
6
7
8
9
10
11
12
13
26 25 24 23 22 21 20 19 18 17 16 15 14
39
38
37
36
35
34
33
32
31
30
29
28
27
40 41 42 43 44 45 46 47 48 49 50 51 52
NC
REF_OUT
NC
RX_IN
RX_OUT
VSSA
VDDA
NC NC
ALC_IN
TX_OUT
NC NC
IO8 IO9 TXD/PRES XIN XOUT
VDD1V8
VSS VDD TXD IO10 RXD
SCK SDI
IO7
IO6
TMS
TCK
TDI
TDO
IO0/RX_DATA
IO5
IO4
IO3
NC
M50Hz_IN
SDO
CSB
T_REQ
SEN
BR1
BR0
CRC
IO11
TEST
NC
NC
TRST
RES
TX_EN
Figure 2. QFN Pin−out of NCN49597 (Top view)
Table 4. NCN49597QFN PIN FUNCTION DESCRIPTION
Pin No. Pin Name I/O Type Description
1 ZC_IN In A 50/60 Hz input for mains zero cross detection
3..5, 12..15,
23, 34
IO3 .. IO11 In/Out D, 5V Safe General Purpose I/O
6 RX_DATA Out D, 5V Safe Data reception indication (open drain output)
7 TDO Out D, 5V Safe Test data output
8 TDI In D, 5V Safe Test data input (internal pull down)
9 TCK In D, 5V Safe Test clock (internal pull down)
10 TMS In D, 5V Safe Test mode select (internal pull down)
11 TRSTB In D, 5V Safe Test reset bar (internal pull down, active low)

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Table 4. NCN49597QFN PIN FUNCTION DESCRIPTION
Pin No. DescriptionTypeI/OPin Name
16 TXD/PRES Out D, 5V Safe Output of transmitted data (TXD) or PRE_SLOT signal
(PRES)
17 XIN In A Xtal input (can be driven by an internal clock)
18 XOUT Out A Xtal output (output floating when XIN driven by external
clock)
19 VDD1V8 P 1V8 regulator output. Foresee a decoupling capacitor
20 VSS P Digital ground
21 VDD P 3.3V digital supply
22 TXD Out D, 5V Safe SCI transmit output (open drain)
24 RXD In D, 5V Safe SCI receive input (Schmitt trigger output)
25 SCK Out D SPI interface external Flash
26 SDI In D SPI interface external Flash
27 SDO Out D SPI interface external Flash
28 CSB In D SPI interface external Flash
29 T_REQ In D, 5V Safe Transmit Request input
30 SEN In D Boot option
31 BR1 In D, 5V Safe SCI baud rate selection
32 BR0 In D, 5V Safe SCI baud rate selection
33 CRC Out D, 5V Safe Correct frame CRC indication (open drain output)
35 RESB In D, 5V Safe Master reset bar (Schmitt trigger input, active low)
36 TEST In D Hardware Test enable (internal pull down)
37 TX_ENB Out D, 5V Safe TX enable bar (open drain)
42 TX_OUT Out A Transmitter output
43 ALC_IN In A Automatic level control input
46 VDDA P 3.3V analog supply
47 VSSA P Analog ground
48 RX_OUT Out A Output of receiver low noise operational amplifier
49 RX_IN In A Positive input of receiver low noise operational amplifier
51 REF_OUT Out A Reference output for stabilization
2, 38..41, 44,
45,50, 52
NC Pins 2, 38..41, 44, 45, 50, 52 are not connected. These
pins need to be left open or connected to the GND plane.
P: Power pin 5V Safe: IO that support the presence of 5V on bus line
A: Analog pin Out: Output signal
D: Digital pin In: Input signal
Detailed Pin Description
VDDA
VDDA is the positive analog supply pin. Nominal voltage
is 3.3 V. A ceramic decoupling capacitor CDA = 100 nF must
be placed between this pin and the VSSA. Connection path
of this capacitance to the VSSA on the PCB should be kept
as short as possible in order to minimize the serial resistance.
REF_OUT
REF_OUT is the analog output pin which provides the
voltage reference used by the A/D converter. This pin must
be decoupled to the analog ground by a 1 mF ceramic
capacitance CDREF. The connection path of this capacitor to

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the VSSA on the PCB should be kept as short as possible in
order to minimize the serial resistance.
VSSA
VSSA is the analog ground supply pin.
VDD
VDD is the 3.3 V digital supply pin. A ceramic decoupling
capacitor CDD = 100 nF must be placed between this pin and
the VSS. Connection path of this capacitance to the VSS on
the PCB should be kept as short as possible in order to
minimize the serial resistance.
VSS
VSS is the digital ground supply pin.
Figure 3: Recommended Layout of the Placement of
Decoupling Capacitors
VDD1V8
This is an additional power supply pin to decouple an
internal LDO regulator. The decoupling capacitor should be
placed as close as possible to this output pin as illustrated in
Figure 4.
RX_OUT
RX_OUT is the output analog pin of the receiver low
noise input op−amp. This op−amp is in a negative feedback
configuration.
RX_IN
RX_IN is the positive analog input pin of the receiver low
noise input op−amp. Together with RX_OUT and
REF_OUT, an active high pass filter is realized. This filter
removes the main frequency (50 or 60 Hz) from the received
signal. The filter characteristics are determined by external
capacitors and resistors. A typical application schematic can
be found in paragraph 50/60 Hz Suppression Filter.
ZC_IN
ZC_IN is the mains frequency analog input pin. The signal
is used to detect the zero cross of the 50 or 60 Hz sine wave.
This information is used, after filtering with the internal
PLL, to synchronize frames with the mains frequency. In
case of direct connection to the mains it is advised to use a
series resistor of 1 MWin combination with two external
clamp diodes in order to limit the current flowing through
the internal protection diodes.
RX_DATA
RX_DATA is a 5 V compliant open drain output. An
external pull−up resistor defines the logic high level as
illustrated in Figure 4. A typical value for the pull−up
resistance “R” is 10 kW. The signal on this output depends
on the status of the data reception. If NCN49597waits for
configuration RX_DATA outputs a pulse train with a 10 Hz
frequency. After Synchronization Confirm Time out
RX_DATA = 0. If NCN49597is searching for
synchronization RX_DATA = 1.
PC20090722.2
VSSD
+5V
Output
R
Figure 4. Representation of 5V Safe Output
TDO, TDI, TCK, TMS, and TRSTB
All these pins are part of the JTAG bus interface. The
JTAG interface is used during production test of the IC and
will not be described here. Input pins (TDI, TCK, TMS, and
TRSTB) contain internal pull−down resistance. TDO is an
output. When not used, the JTAG interface pins may be left
floating.
TXD/PRES
TXD/PRES is the output for either the transmitting data
(TX_DATA) or a synchronization signal with the time−slots
(PRE_SLOT). TXD/PRES. More information can be found
in paragraph Local Port.
XIN
XIN is the analog input pin of the oscillator. It is connected
to the interval oscillator inverter gain stage. The clock signal
can be created either internally with the external crystal and
two capacitors or by connecting an external clock signal to
XIN. For the internal generation case, the two external
capacitors and crystal are placed as shown in Figure 5. For
the external clock connection, the signal is connected to XIN
and XOUT is left unused.

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XTAL_IN PC20111118.1
XTAL_OUT
CX
VSSA
CX
48 MHz
Figure 5. Placement of the Capacitors and Crystal
with Clock Signal Generated Internally
The crystal is a classical parallel resonance crystal of
48 MHz. The values of the capacitors CXare given by the
manufacturer of the crystal. A typical value is 36 pF. The
crystal has to fulfill impedance characteristics specified in
the NCN49597data sheet. As an oscillator is sensitive and
precise, it is advised to put the crystal as close as possible on
the board and to ground the case.
XOUT
XOUT is the analog output pin of the oscillator. When the
clock signal is provided from an external generator, this
output must be floating. When working with a crystal, this
pin cannot be used directly as clock output because no
additional loading is allowed on the pin (limited voltage
swing).
TXD
TXD is the digital output of the asynchronous serial
communication (SCI) unit. Only half−duplex transmission
is supported. It is used to realize the communication between
the NCN49597and the application microcontroller. The
TXD is an open drain IO (5 V safe). External pull−up
resistances (typically 10 kW) are necessary to generate the
5 V level. See Figure 4 for the circuit schematic.
RXD
This is the digital input of the asynchronous SCI unit.
Only half−duplex transmission is supported. This pin
supports a 5 V level. It is used to realize the communication
between the NCN49597and the application microcontroller.
RXD is a 5 V safe input.
T_REQ
T_REQ is the transmission request input of the Serial
Communication Interface. When pulled low its initiate a
local communication from the application micro controller
to NCN49597. T_REQ is a 5 V safe input. See also
paragraph Error! Reference source not found..
BR1, BR0
BR0 and BR1 are digital input pins. They are used to select
the baud rate (bits/second) of the Serial Communication
Interface unit. The rate is defined according to Error!
Reference source not found.. The values are taken into
account after a reset, hardware or software. Modification of
the baud rate during function is not possible. BR0 and BR1
are 5 V safe.
CRC
CRC is a 5 V compliant open drain output. An external
pull−up resistor defines the logic high level as illustrated in
Figure 4. A typical value for this pull−up resistance “R” is
10 kW. The signal on this output depends on the cyclic
redundancy code result of the received frame. If the cyclic
redundancy code is correct CRC = H during the pause
between two time slots.
RESB
RESB is a digital input pin. It is used to perform a
hardware reset of the NCN49597. This pin supports a 5 V
voltage level. The reset is active when the signal is low
(0 V).
TEST
TEST is a digital input pin with internal pull down resistor
used to enable the Hardware Test Mode of the chip. When
TEST is left open or forced to ground Normal Mode is
enabled. When TEST is forced to VDD the Hardware Test
Mode is enabled. This mode is used during production test
of the IC and will not be described here. TEST pin is not 5 V
safe.
TX_ENB
TX_ENB is a digital output pin. It is low when the
transmitter is activated. The signal is available to turn on the
line driver. TX_ENB is a 5 V safe with open drain output,
hence a pull−up resistance is necessary achieve the
requested voltage level associated with a logical one. See
also Figure 4 for reference.
TX_OUT
TX_OUT is the analog output pin of the transmitter. The
provided signal is the S−FSK modulated frames. A filtering
operation must be performed to reduce the second and third
order harmonic distortion. For this purpose an active filter
is suggested. See also paragraph Transmitter Output
TX_OUT.
ALC_IN
ALC_IN is the automatic level control analog input pin.
The signal is used to adjust the level of the transmitted
signal. The signal level adaptation is based on the AC
component. The DC level on the ALC_IN pin is fixed
internally to 1.65 V. Comparing the peak voltage of the AC
signal with two internal thresholds does the adaptation of the
gain. Low threshold is fixed to 0.4 V. A value under this
threshold will result in an increase of the gain. The high
threshold is fixed to 0.6 V. A value over this threshold will
result in a decrease of the gain. A serial capacitance is used
to block the DC components. The level adaptation is
performed during the transmission of the first two bits of a
new frame. Eight successive adaptations are performed. See

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also paragraph Amplifier with Automatic Level Control
(ALC).
SCK, SDI, SDO, CSB
These signals from the SPI interface to an optional
external Flash. See Reference 1.
ELECTRICAL CHARACTERISTICS
DC and AC Characteristics
Oscillator: Pin XIN, XOUT
In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on
the static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.
Table 5. OSCILLATOR
Parameter Test Conditions Symbol Min Typ Max Unit
Crystal frequency (Note 1) fCLK −100 ppm 48 +100 ppm MHz
Duty cycle with quartz connected (Note 1) 40 60 %
Start−up time (Note 1) Tstartup 50 ms
Load capacitance external crystal (Note 1) CL18 pF
Series resistance external crystal (Note 1) RS20 40 80 W
Maximum Capacitive load on
XOUT
XIN used as clock input CLXOUT 50 pF
Low input threshold voltage XIN used as clock input VILXOUT 0.3 VDD V
High input threshold voltage XIN used as clock input VIHXOUT 0.7 VDD V
Low output voltage XIN used as clock input,
XOUT = 2 mA
VOLXOUT 0.3 V
High input voltage XIN used as clock input VOHXOUT VDD −0.3 V
1. Guaranteed by design. Maximum allowed series loss resistance is 80 W

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Zero Cross Detector and 50/60 Hz PLL: Pin ZC_IN
Table 6. ZERO CROSS DETECTOR AND 50/60 HZ PLL
Parameter Test Conditions Symbol Min Typ Max Unit
Maximum peak input current ImpZC_IN −20 20 mA
Maximum average input current During 1 ms ImavgZC_IN −2 2 mA
Mains voltage (ms) range With protection resistor at
ZC_IN
VMAINS 90 550 V
Rising threshold level (Note 2) VIRZC_IN 1.9 V
Falling threshold level (Note 2) VIFZC_IN 0.9 V
Hysteresis (Note 2) VHYZC_IN 0.4 V
Lock range for 50 Hz (Note 3) MAINS_FREQ = 0 (50 Hz) Flock50Hz 45 55 Hz
Lock range for 60 Hz (Note 3) MAINS_FREQ = 0 (60 Hz) Flock60Hz 54 66 Hz
Lock time (Note 3) MAINS_FREQ = 0 (50 Hz) Tlock50Hz 15 s
Lock time (Note 3) MAINS_FREQ = 0 (60 Hz) Tlock60Hz 20 s
Frequency variation without going
out of lock (Note 3)
MAINS_FREQ = 0 (50 Hz) DF60Hz 0.1 Hz/s
Frequency variation without going
out of lock (Note 3)
MAINS_FREQ = 0 (60 Hz) DF50Hz 0.1 Hz/s
Jitter of CHIP_CLK (Note 3) JitterCHIP_CLK −25 25 ms
2. Measured relative to VSS
3. These parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be guaranteed
by the digital test patterns.

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Transmitter External Parameters: Pin TX_OUT, ALC_IN, TX_ENB
To guarantee the transmitter external specifications the TX_CLK frequency must be 12 MHz ±100 ppm.
Table 7. TRANSMITTER EXTERNAL PARAMETERS
Parameter Test Conditions Symbol Min Typ Max Unit
Maximum peak output level fTX_OUT = 23 – 75 kHz
fTX_OUT = 95 kHz
Level control at max. output
VTX_OUT 0.85
0.76
1.15
1.22
Vp
Second order harmonic distortion fTX_OUT = 95 kHz
Level control at max. output
HD2 −54 dB
Third order harmonic distortion fTX_OUT = 95 kHz
Level control at max. output
HD3 −53 dB
Frequency accuracy of the gener-
ated sine wave
(Notes 4 and 6) DfTX_OUT 30 Hz
Capacitive output load at pin
TX_OUT
(Note 4) CLTX_OUT 20 pF
Resistive output load at pin
TX_OUT
RLTX_OUT 5kW
Turn off delay of TX_ENB output (Note 5) TdTX_ENB 0.25 0.5 ms
Automatic level control attenuation
step
ALCstep 2.9 3.1 dB
Maximum attenuation ALCrange 20.3 21.7 dB
Low threshold level on ALC_IN VTLALC_IN −0.46 −0.36 V
High threshold level on ALC_IN VTHALC_IN −0.68 −0.54 V
Input impedance of ALC_IN pin RALC_IN 111 189 kW
Power supply rejection ration of the
transmitter section
PSRRTX_OUT 10
(Note 7)
35
(Note 8)
dB
4. This parameter will not be tested in production.
5. This delay corresponds to the internal transmit path delay and will be defined during design.
6. Taking into account the resolution of the DDS and an accuracy of 100ppm of the crystal.
7. A sinusoidal signal of 10 kHz and 100 mVpp is injected between VDDA and VSSA. The digital AD converter generates an idle pattern. The
signal level at TX_OUT is measured to determine the parameter.
8. A sinusoidal signal of 50 Hz and 100 mVpp is injected between VDDA and VSSA. The digital AD converter generates an idle pattern. The
signal level at TX_OUT is measured to determine the parameter.
The LPF filter + amplifier must have a frequency characteristic between the limits listed below. The absolute output level
depends on the operating condition. In production the measurement will be done for relative output levels where the 0 dB
reference value is measured at 50 kHz with a signal amplitude of 100 mV.
Table 8. TRANSMITTER FREQUENCY CHARACTERISTICS
Frequency (kHz)
Attenuation
Unit
Min Max
10 −0.5 0.5 dB
95 −1.3 0.5 dB
130 −4.5 −2.0 dB
165 −3.0 dB
330 −18.0 dB
660 −36.0 dB
1000 −50 dB
2000 −50 dB

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Receiver External Parameters: Pin RX_IN, RX_OUT, REF_OUT
Table 9. RECEIVER EXTERNAL PARAMETERS
Parameter Test Conditions Symbol Min Typ Max Unit
Input offset voltage 42 dB AGC gain = 42 dB VOFFS_RX_IN 5 mV
Input offset voltage 0 dB AGC gain = 0 dB VOFFS_RX_IN 50 mV
Max. peak input voltage (corres-
ponding to 62.5% of the SD full
scale)
AGC gain = 0 dB (Note 9) VMAX_RX_IN 0.85 1.15 Vp
Input referred noise of the analog
receiver path
AGC gain = 42 dB
(Notes 9 and 10)
NFRX_IN 150 nV/ǠHz
Input leakage current of receiver
input
ILE_RX_IN −1 1 mA
Max. current delivered by
REF_OUT
IMax_REF_OUT −300 300 mA
Power supply rejection ratio of the
receiver input section
AGC gain = 42 dB (Note 11) PSRRLPF_OUT 10 dB
AGC gain = 42 dB (Note 12) 35
AGC gain step AGCstep 5.7 6.3 dB
AGC range AGCrange 39.9 44.1 dB
Analog ground reference output
voltage
VREF_OUT 1.52 1.78 V
Signal to noise ratio at 62.5 % of
the SD full scale
(Notes 9 and 13) SNAD_OUT 54 dB
Clipping level at the output of the
gain stage (RX_OUT)
VCLIP_AGC_IN 1.15 1.65 Vp
9. Input at RX_IN, no other external components.
10.Characterization data only. Not tested in production.
11. A sinusoidal signal of 10 kHz and 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT and
REF_OUT output is measured to determine the parameter.
12.A sinusoidal signal of 50 Hz and 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT output is
measured to determine the parameter.
13.These parameters will be tested in production with an input signal of 95 kHz and 1 Vp by reading out the digital samples at the point AD_OUT
with the default settings of T_RX_MOD[7], SDMOD_TYP, DEC_TYP, and COR_F_ENA. The AGC gain is switched to 0 dB.
The receive LPF filter + AGC + low noise amplifier must have a frequency characteristic between the limits listed below.
The absolute output level depends on the operating condition.
Table 10. RECEIVER FREQUENCY CHARACTERISTICS
Frequency (kHz)
Attenuation
Unit
Min Max
10 −0.5 0.5 dB
95 −1.3 0.5 dB
130 −4.5 −2.0 dB
165 −3.0 dB
330 −18.0 dB
660 −36.0 dB
1000 −50 dB
2000 −55 dB

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Power−on−Reset (POR)
Table 11. POWER−ON−RESET
Parameter Test Conditions Symbol Min Typ Max Unit
POR threshold VPOR 1.7 2.7 V
Power supply rise time 0 to 3V TRPOR 1 ms
Digital Outputs: TDO, CLK_OUT
Table 12. DIGITAL OUTPUTS: TDO, CLK_OUT
Parameter Test Conditions Symbol Min Typ Max Unit
Low output voltage IXOUT = 4 mA VOL 0.4 V
High output voltage IXOUT = −4 mA VOH 0.85 VDD V
Digital Outputs with Open Drain: TX_ENB, TXD
Table 13. DIGITAL OUTPUTS WITH OPEN DRAIN: TX_ENB, TXD, RX_DATA, CRC, T_REQ
Parameter Test Conditions Symbol Min Typ Max Unit
Low output voltage IXOUT = 4 mA VOL 0.4 V
Digital Inputs: BR0, BR1
Table 14. DIGITAL INPUTS: BR0, BR1
Parameter Test Conditions Symbol Min Typ Max Unit
Low input level VIL 0.2 VDD V
High input level 0 to 3 V VIH 0.8 VDD V
Input leakage current ILEAK −10 10 mA
Digital Inputs with Pull Down: TDI, TMS, TCK, TRSTB, TEST
Table 15. DIGITAL INPUTS WITH PULL DOWN: TDI, TMS, TCK, TRSTB, TEST
Parameter Test Conditions Symbol Min Typ Max Unit
Low input level VIL 0.2 VDD V
High input level VIH 0.8 VDD V
Pull down resistor (Note 14) RPU 7 50 kW
14.Measured around a bias point of VDD/2.
Digital Schmitt Trigger Inputs: RXD, RESB
Table 16. DIGITAL SCHMITT TRIGGER INPUTS: RXD, RESB
Parameter Test Conditions Symbol Min Typ Max Unit
Rising threshold level VT+ 0.80 VDD V
Falling threshold level VT−0.2 VDD V
Input leakage current ILEAK −10 10 mA

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Current Consumption
Table 17. CURRENT CONSUMPTION
Parameter Test Conditions Symbol Min Typ Max Unit
Current consumption in receive
mode
Current through VDD and VDDA
(Note 15)
IRX 60 80 mA
Current consumption in transmit
mode
Current through VDD and VDDA
(Note 15)
ITX 60 80 mA
Current consumption when RESB
= 0
Current through VDD and VDDA
(Note 15)
IRESET 4 mA
15.fCLK = 48 MHz.
INTRODUCTION
General Description
The NCN49597 is a single chip half duplex S−FSK
modem dedicated to power line carrier (PLC) data
transmission on low−or medium−voltage power lines. The
device offers complete handling of the protocol layers from
the physical up to the MAC. NCN49597 complies with the
CENELEC EMC standard EN 50065−1 and the
IEC 61334−5−1 standards. It operates from a single 3.3 V
power supply and is interfaced to the power line by an
external power driver and transformer. An internal PLL is
locked to the mains frequency and is used to synchronize the
data transmission at data rates of 300, 600, 1200, 2400 and
4800 baud for a 50 Hz mains frequency, or 360, 720, 1440,
2880 and 5760 baud for a 60 Hz mains frequency. In both
cases this corresponds to 3, 6, 12 or 24 data bits per half cycle
of the mains period.
S−FSK is a modulation and demodulation technique that
combines some of the advantages of a classical spread
spectrum system (e.g. immunity against narrow band
interferers) with the advantages of the classical FSK system
(low complexity). The transmitter assigns the space
frequency fS to “data 0” and the mark frequency fM to
“data 1”. The difference between S−FSK and the classical
FSK lies in the fact that fS and fM are now placed far from
each other, making their transmission quality independent
from each other (the strengths of the small interferences and
the signal attenuation are both independent at the two
frequencies). The frequency pairs supported by the
NCN49597 are in the range of 9 −150 kHz with a typical
separation of 10 kHz.
The conditioning and conversion of the signal is
performed at the analog front−end of the circuit. The further
processing of the signal and the handling of the protocol is
digital. At the back−end side, the interface to the application
is done through a serial interface. The digital processing of
the signal is partitioned between hardwired blocks and a
microprocessor block. The microprocessor is controlled by
firmware. Where timing is most critical, the functions are
implemented with dedicated hardware. For the functions
where the timing is less critical, typically the higher level
functions, the circuit makes use of the ARM microprocessor
core.
The processor runs DSP algorithms and, at the same time,
handles the communication protocol. The communication
protocol, in this application, contains the MAC = Medium
Access Control Layer. The program running on the
microprocessor is stored into ROM. The working data
necessary for the processing is stored in an internal RAM. At
the back−end side the link to the application hardware is
provided by a Serial Communication Interface (SCI). The
SCI is an easy to use serial interface, which allows
communication between an external processor used for the
application software and the NCN49597 modem. The SCI
works on two wires: TXD and RXD. Baud rate is
programmed by setting 2 bits (BR0, BR1).
Because the low protocol layers are handled in the circuit,
the NCN49597 provides an innovative architectural split.
Thanks to this, the user has the benefit of a higher level
interface of the link to the PLC medium. Compared to an
interface at the physical level, the NCN49597 allows faster
development of applications. The user just needs to send the
raw data to the NCN49597 and no longer has to take care of
the protocol detail of the transmission over the specific
medium. This last part represents usually 50% of the
software development costs.

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Minor User TypeMajor User Type
PC201111 12.2
SPY
Application
NCN49597in
MONITOR mode
TEST
Application
NCN49597in
TEST mode
CLIENT
Application
NCN49597in
MASTER mode
SERVER
Application
NCN49597 in
SLAVE mode
SERVER
Application
NCN49597in
SLAVE mode
Figure 6. Application Examples
NCN49597 is intended to connect equipment using
Distribution Line Carrier (DLC) communication. It serves
two major and two minor types of applications:
•Major types:
♦Master or Client:
A Master is a client to the data served by one or
many slaves on the power line. It collects data from
and controls the slave devices. A typical application
is a concentrator system
♦Slave or Server:
A Slave is a server of the data to the Master. A
typical application is an electricity meter equipped
with a PLC modem.
•Minor type:
♦Spy or Monitor:
Spy or Monitor mode is used to only listen to the
data that comes across the power line. Only the
physical layer frame correctness is checked. When
the frame is correct, it is passed to the external
processor.
♦Test Mode:
The Software Test Mode is used to test the
compliance of a PLC modem conforms to
CENELEC. EN 50065−1 by a continuous broadcast
of fSor fM.

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Functional Description
The block diagram below represents the main functional units of the NCN49597:
Communication Controller
ARM
Risc
Core
Serial
Comm.
Interface
Local Port
Test
Control
POR
Watchdog
Timer 1 & 2
SPI
Interrupt
Control
Data
RAM
Program
ROM
AAF AGC A/D
REF
S−FSK
Demodulator
Receiver (S−FSK Demodulator)
Clock and Control
Zero
crossing PLL OSC
Clock Generator
& Timer
Transmit Data
& Sine Synthesizer
D/A
LP
Filter
Transmitter (S−FSK Modulator)
RX_DATA
RESB
JTAG I /F
TEST
TX_ENB
TX_OUT
ALC_IN
RX_OUT
RX_IN
REF_OUT
M50Hz_IN
XIN XOUTVDDA VSSA VDDD VSSD
NCN49597
PC20111019.2
TO Power Amplifier
FROM Line Coupler
TO Application
Micro Controller
TxD
RxD
T_REQ
BR0
BR1
CRC
TX_DATA / PRE_SLOT
5
VDD1V8
IO[9:3]
5
SPI I/F
5
Figure 7. S−FSK Modem NCN49597 Block Diagram
Transmitter
The NCN49597 Transmitter function block prepares the
communication signal which will be sent on the
transmission channel during the transmitting phase. This
block is connected to a power amplifier which injects the
output signal on the mains through a line−coupler.
Receiver
The analog signal coming from the line−coupler is low
pass filtered in order to avoid aliasing during the conversion.
Then the level of the signal is automatically adapted by an
automatic gain control (AGC) block. This operation
maximizes the dynamic range of the incoming signal. The
signal is then converted to its digital representation using
sigma delta modulation. From then on, the processing of the
data is done in a digital way. By using dedicated hardware,
a direct quadrature demodulation is performed. The signal
demodulated in the base band is then low pass filtered to
reduce the noise and reject the image spectrum.
Clock and Control
According to the IEC 61334−5−1 standard, the frame data
is transmitted at the zero cross of the mains voltage. In order
to recover the information at the zero cross, a zero cross
detection of the mains is performed. A phase−locked loop
(PLL) structure is used in order to allow a more reliable
reconstruction of the synchronization. This PLL permits as
well a safer implementation of the ”repetition with credit”
function (also known as chorus transmission). The clock
generator makes use of a precise quartz oscillator master.
The clock signals are then obtained by the use of a
programmed division scheme. The support circuits are also
contained in this block. The support circuits include the
necessary blocks to supply the references voltages for the
AD and DA converters, the biasing currents and power
supply sense cells to generate the right power off and startup
conditions.

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48 bit @ 2400 baud
20 ms
t
PC20100609.1
Figure 8. Data Stream is in Sync with Zero Cross of the Mains (example for 50 Hz)
Communication Controller
The Communication Controller block includes the
micro−processor, its peripherals: RAM, ROM, UART,
TIMER, and the Power on reset. The processor uses the
ARM Reduced Instruction Set Computer (RISC)
architecture optimized for IO handling. For most of the
instructions, the machine is able to perform one instruction
per clock cycle. The microcontroller contains the necessary
hardware to implement interrupt mechanisms, timers and is
able to perform byte multiplication over one instruction
cycle. The microcontroller is programmed to handle the
physical layer (chip synchronization), and the MAC layer
conform to IEC 61334−5−1. The program is stored in a
masked ROM. The RAM contains the necessary space to
store the working data. The back−end interface is done
through the Serial Communication Interface block. This
back−end is used for data transmission with the application
micro controller (containing the application layer for
concentrator, power meter, or other functions) and for the
definition of the modem configuration.
Local Port
The controller uses 3 output ports to inform about the
actual status of the PLC communication. RX_DATA
indicates if Receiving is in progress, or if NCN49597 is
waiting for synchronization, or of it configures. CRC
indicates if the received frames are valid (CRC = OK).
TXD/PRES is the output for either the transmitting data
(TX_DATA) or a synchronization signal with the time−slots
(PRE_SLOT).
Serial Communication Interface
The local communication is a half duplex asynchronous
serial link using a receiving input (RxD) and a transmitting
output (TxD). The input port T_REQ is used to manage the
local communication with the application micro controller
and the baud rate can be selected depending on the status of
two inputs BR0, BR1. These two inputs are taken in account
after an NCN49597 reset. Thus when the application micro
controller wants to change the baud rate, it has to set the two
inputs and then provoke a reset.
DETAILED HARDWARE DESCRIPTION
Clock and Control
According to the IEC 61334−5−1 standard, the frame data
is transmitted at the zero cross of the mains voltage. In order
to recover the information at the zero cross, a zero cross
detection of the mains is performed. A phase−locked loop
(PLL) structure is used in order to allow a more reliable
reconstruction of the synchronization. The output of this
block is the clock signal CHIP_CLK, 8 times over sampled
with the bit rate. The oscillator makes use of precise 48 MHz
quartz. This clock signal together with CHIP_CLK is fed
into the Clock Generator and time block. Here several
internal clock signals and timings are obtained by the use of
a programmed division scheme.

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Clock and Control
Zero
crossing PLL OSC
Clock Generator
& Timer
ZC_IN
XIN XOUT
PC20090619.4
BIT_CLK BYTE_CLK FRAME_CLK PRE_BYTE_CLK PRE_FRAME_CLK PRE_SLOT
CHIP_CLK
Figure 9. Clock and Control Block
Zero Cross Detector
ZC_IN is the mains frequency analog input pin. The signal
is used to detect the zero cross of the 50 or 60 Hz sine wave.
This information is used, after filtering with the internal
PLL, to synchronize frames with the mains frequency. In
case of direct connection to the mains it is advised to use a
series resistor of 1 MWin combination with two external
Schottky clamp diodes in order to limit the current flowing
through the internal protection diodes.
FROM
MAINS
Clock & Control
ZC_IN
ZeroCross
PLL CHIP_CLK
Debounce
Filter
3V3_A
1MW
PC20100608.1
100 pF
BAS70−04
Figure 10. Zero Cross Detector with Falling Edge De−bounce Filter
The zero cross detector output is logic zero when the input
is lower than the falling threshold level and a logic one when
the input is higher than the rising threshold level. The falling
edges of the output of the zero cross detector are de−bounced
by a period between 0.5 ms and 1 ms. The Rising edges are
not de−bounced.

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t
10 ms
VMAINS
ZeroCross
tZCD
VIRZC_IN
PC20090620 .1
VIFZC _IN
tDEBOUNCE = 0,5 .. 1 ms
Figure 11. Zero Cross Detector Signals and Timing (example for 50 Hz)
50/60 Hz PLL
The output of the zero cross detector is used as an input for
a PLL. The PLL generates the clock CHIP_CLK which is 8
times the bit rate and which is in phase with the rising edge
crossings. The PLL locks on the zero cross from negative to
positive phase. The bit rate is always an even multiple of the
mains frequency, so following combinations are possible:
Table 18. CHIP_CLK IN FUNCTION OF SELECTED BAUD RATE AND MAINS FREQUENCY
BAUD[1:0] MAINS_FREQ Baudrate CHIP_CLK
00
50 Hz
300 2400 Hz
01 600 4800 Hz
10 1200 9600 Hz
11 2400 19200 Hz
00
60 Hz
360 2880 Hz
01 720 5760 Hz
10 1440 11520 Hz
11 2880 23040 Hz
In case no zero crossings are detected the PLL freezes its internal timers in order to maintain the CHIP_CLK timing.

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6 bit @ 300 baud
t
10 ms
VMAINS
ZeroCross
tZCD
VIRZC _IN
CHIP _CLK
PC 20090 619 .3
PLL in lock
Start of Physical PreFrame (*)
*The start of the Physical Subframe is shifted back with R_ZC_ADJUST[7:0] x 26 mS = tZCD to compensate for the zero cross delay.
Figure 12. Zero Cross Adjustment to Compensate for Zero Cross Delay (example for 50 Hz)
The phase difference between the zero cross of the mains
and CHIP_CLK can be tuned. This opens the possibility to
compensate for external delay tZCD (e.g. opto coupler) and
for the 1.9 V positive threshold VIRZC_IN of the zero cross
detector. This is done by pre−loading the PLL counter with
a number value stored in register R_ZC_ADJUST[7:0]. The
adjustment period or granularity is 26 ms. The maximum
adjustment is 255 x 26 ms = 6.6 ms which corresponds with
1/3rd of the 50 Hz mains sine period.
Table 19. ZERO CROSS DELAY COMPENSATION
R_ZC_ADJUST[7:0] Compensation
0000 0000 0 ms
0000 0001 26 ms
0000 0010 52 ms
0000 0011 78 ms
… …
1111 1101 6589 ms
1111 1110 6615 ms
1111 1111 6641 ms
Oscillator
The oscillator works with a standard parallel resonance
crystal of 48 MHz. XIN is the input to the oscillator inverter
gain stage and XOUT is the output.

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XTAL_IN PC20111118.1
XTAL_OUT
CX
VSSA
CX
48 MHz
Figure 13. Placement of the Capacitors and Crystal
with Clock Signal Generated Internally
For correct functionality the external circuit illustrated in
Figure 13 must be connected to the oscillator pins. For a
crystal requiring a parallel capacitance of 18 pF CXmust be
around 36 pF. (Values of capacitors are indicative only and
are given by the crystal manufacturer). To guarantee startup
the series loss resistance of the crystal must be smaller than
60 W.
The oscillator output fCLK = 48 MHz is the base frequency
for the complete IC. The clock frequency for the ARM fARM
= fCLK. The clock for the transmitter, fTX_CLK is equal to
fCLK / 4 or 12 MHz. All the transmitter internal clock signals
will be derived from fTX_CLK. The clock for the receiver,
fRX_CLK is equal to fCLK / 8 or 6 MHz. All the receiver
internal clock signals will be derived from fRX_CLK.
Clock Generator and Timer
The CHIP_CLK and fCLK are used to generate a number
of timing signals used for the synchronization and interrupt
generation. The timing generation has a fixed repetition rate
which corresponds to the length of a physical subframe. (see
paragraph Error! Reference source not found.)
The timing generator is the same for transmit and receive
mode. When NCN49597 switches from receive to transmit
and back from transmit to receive, the R_CHIP_CNT
counter value is maintained. As a result all timing signals for
receive and transmit have the same relative timing. The
following timing signals are defined as:
BIT_CLK
63 64 652871 2872 102879 2 3 4 5 6 7 8 9
CHIP_CLK
BYTE_CLK
FRAME_CLK
PRE_FRAME_CLK
PRE_BYTE_CLK
R_CHIP_CNT
PRE_SLOT
PC20090619.1
Start of the physical subframe
Figure 14. Timing Signals
CHIP_CLK: is the output of the PLL and 8 times the bit rate
on the physical interface. See also paragraph 50/60 Hz PLL.
BIT_CLK: is active at counter values 0, 8, 16, .. 2872 and
inactive at all other counter values. This signal is used to
indicate the transmission of a new bit.
BYTE_CLK: is active at counter values 0, 64, 128, .. 2816
and inactive at all other counter values. This signal is used
to indicate the transmission of a new byte.