A5191HRTNGEVB
www.onsemi.com
8
Microcontroller Interface IDC1
RESET
R2
1
22
23
25
26
RxD
CD
TxD
RTS
2
3
5
7
9
IDC1
VCC
VCC
R23
PC20110513.4
Figure 8. Microcontroller Interface
Table 5. MICROCONTROLLER INTERFACE
Pin Number Signal Type Description
1 RST Open drain Reset signal from the voltage supervisor, open drain with pull−up
3 CD Output Carrier Detect
5 RxD Input Receive from microcontroller
7 TxD Output Transmit towards microcontroller
9 RTSB Input Request to send
2, 10 VDD Power 3 V nominal
4, 6, 8 GND Power
The interface towards a microcontroller is provided in
IDC1. This interface can also be used to supply power to the
module. The nominal supply voltage for the module is 3 V.
For more information see the section on power supply and
references.
The RESETB line to the modem is an open drain signal.
A pull−up resistor of 200 kWis provided on the board, and
should not be duplicated on the microcontroller side. The
reset signal is generated on the board, and could be used as
reset signal for other IC such as the microcontroller.
The CD signal rises when a HART signal of ca. 100 mVpp
is detected on the current loop. See the section on reference
voltages for more information on these threshold level
settings. When no signal, or a signal of limited amplitude is
present, the CD line is pulled down to 0 V.
The RxD, TxD, and RTSB signals implement a standard
UART interface at 1200 baud with start bit 8 data bits, parity
bit and stop bit (11−bit frame). The RTSB signal disconnects
the transmitter circuit when pulled high, and should be held
low before any data is transmitted. Data frames are not
buffered by the modem. Instead, data is transmitted bit by
bit. Care should be taken to avoid clock skew in the receiving
UART. If the same time base is used for both the modem and
the UART, a 1% accurate time base may not be sufficient.
The problem is a combination of receive data jitter and clock
skew between transmitting and receiving HART devices. If
the transmit time base is at 99% of nominal and the receive
time base in another device is at 101% of nominal, the
receive data (at the receiving UART) will be skewed by
roughly 21% of one bit time at the end of each 11−bit byte.
This is shown in Figure 9. The skew time is measured from
the initial falling edge of the start bit to the center of the 11th
bit cell. This 21% skew by itself is a relatively good result.
However, there is another error source for bit boundary jitter.
The Phase Lock Loop demodulator in the A5191HRT
produces jitter in the receive data that can be as large as 12%
of a bit time. Therefore, a bit boundary can be shifted by as
much as 24% of a bit time relative to its ideal location based
on the start−bit transition. (The start−bit transition and a later
transition can be shifted in opposite directions for a total of
24%.)
The clock skew and jitter added together is 45%, which is
the amount that a bit boundary could be shifted from its
expected position. UARTs that sample at mid−bit will not be
affected. However, there are UARTs that take multiple
samples during each bit to try to improve on error
performance. These UARTs may not be satisfactory,
depending on how close the samples are to each other, and
how samples are interpreted. A UART that takes a majority
vote of three samples is acceptable.
