ON Semiconductor Fairchild PFC SPM Guide

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PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
1
Application Note AN-9041
PFC SPM® Design Guide with Analog PFC IC
Written by:
Application Engineering Part
Motion Control System Team
HV PCIA
FAIRCHILD SEMICONDUCTOR

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
2
Contents
1. System Configurations...........................................................................3
2. Protection Circuits..................................................................................3
Over Current Protection (OCP).............................................................................................................. 3
Over Voltage Protection......................................................................................................................... 4
Under Voltage Protection....................................................................................................................... 4
3. Design Example (PFC SPM® DEMO BOARD) ......................................5
Operating conditions of PFC SPM® demo board: .................................................................................. 5
Output capacitance and Inductance design............................................................................................ 5
Output Voltage Ripple & Output Capacitance...................................................................................... 5
Inductance & Input Current Ripple ....................................................................................................... 6
Open Loop Response ............................................................................................................................... 6
Current Loop Amplifier .......................................................................................................................... 7
Voltage Loop Amplifier .......................................................................................................................... 7
Control Loop Implementation................................................................................................................ 8
Current Loop .......................................................................................................................................... 8
Voltage Loop......................................................................................................................................... 10
Other Parameters ................................................................................................................................. 10
Over Current Protection....................................................................................................................... 12
Over Voltage Protection....................................................................................................................... 13
DC-link Voltage Control .......................................................................................................................... 14
4. Experimental Results ...........................................................................15
NOTE:
In this and other Fairchild documentation and collateral, the following terms are interchangeable:
DIP = SPM2, Mini-DIP = SPM3, Tiny-DIP = SPM5, µMini-DIP = SPM45H, PFCM = PFC SPM®.

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
3
1. System Configurations
Control IC
Vac
N/F
Relay
LVIC
VTH
RTH
S
R
PR
N
NSENSE
VAC-
Shunt
Resistor
NTC
Thermistor
SPM
IN(S)
IN(R)
Fig.1 Typical block diagram of PFC SPM® system
An inrush-current prevention circuit is required due to the large DC link capacitance as shown in Fig. 1.
The relay of the circuit should be closed after DC link capacitor is charged far enough. PFC SPM®, mini-
SPM and control IC can share single GND stage. Usually, this GND and the NSENSE terminal of PFC SPM
should have the same potential. Large surge voltage is easily produced between P and N terminals by large
current switching. To reduce surge voltage it is important to shorten the DC link bus wiring between PFC
SPM and DC link capacitor. In addition, good high frequency characteristic capacitor, such as polypropylene
film capacitor should be mounted near to P and N terminals as a snubber.
2. Protection Circuits
Following Fig. 2 shows the timing chart of protection function. There are two kind of protection level
for both OCP and OVP. Generally, PFC control ICs have its own OCP and OVP function. Also, user can
make the PFC SPM® stop and output the FO signal under preset OC, OV condition using its Csc input.
Over Current Protection (OCP)
[OCP Level1 –PFC SPM®] PFC SPM can protect from over current situation. When OC(over current)
situation happens, the PFC SPM stops operating and generates fault out signal during fault-out duration
time(set by CFOD). And then after the duration, it works again according to the input command. Its total
propagation delay time may depend on outer op-amp speed. We recommend using a low cost slow op-amp
solution with fast protection. It is the OCP level2 protection described in next paragraph.
[OCP Level2 (SCP) –PFC control IC] By the peak current limit function of PFC control IC, the system
is protected from SC(Short Circuit) situation. The recommended current limit of OCP level 2 is higher than
that of OCP level 1. It doesn’t generate the fault out signal but its response is very fast. It will protect the
system from short circuit situation during the propagation delay time of OCP level1.

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
4
Over Voltage Protection
OV (Over Voltage) protection can be also implemented by dual protection. The DC-link voltage
changes slowly because of its large capacitance. So OVP does not need fast response. Therefore it is
optional to activate the OVP of PFC controller.
[OVP Level 1 - PFC controller] OVP level 1 suppresses voltage overshoot in transient situation. It
doesn’t generate fault out signal.
[OVP Level 2 – PFC SPM®] The voltage level of OVP level 2 is higher than that of OVP level 1.
When OV situation happens, the PFC SPM stops operating and generates fault out signal during fault-out
duration time(set by CFOD). And then it works again.
Under Voltage Protection
IGBT gate will be interrupted when control voltage drops below UV trip level, and the protection will be realeased
automatically if the control voltage recovers to the UV reset level.
Fig.2 Timing chart of protection function

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
5
3. Design Example (PFC SPM® DEMO BOARD)
A general PFC example is implemented for 5[kW] air-conditioning applications whose input voltage is
187~276[V].
Operating conditions of PFC SPM® demo board:
Table 1. The operating conditions.
Item Symbol Value Unit
1 Switching Frequency Fsw 40 KHz
2 Minimum Input Voltage Vimin 176 Vac
3 Nominal Input Voltage Vinom 220 Vac
4 Maximum Input Voltage Vimax 264 Vac
5 Output Max. Power Po 5000 W
6 Minimum Output Voltage Vomin 350 Vdc
7 Nominal Output Voltage Vonom 380 Vdc
8 OVP level 1 V
OV1
420 V
9 OVP level 2 V
OV2
440 V
10 Peak Ripple Current Iripple 5A
11 OCP Level1 Iocp1 40 A
12 OCP Level2 (SCP) Iocp2 50 A
13 Shunt Resistor Rsh 2 MOhm
14 DC Capacitor Cout 940 uF
Output capacitance and Inductance design
Output Voltage Ripple & Output Capacitance
Voltage ripple of V
DC
can be reduced by employing large C
OUT
. In demo board, C
OUT
is set to 940[µF]
(470[µF] x 2)
5

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
6
Inductance & Input Current Ripple
where: I
Lp-p
: Peak to peak current of PFC inductor
V
IN
: Input AC voltage
V
OUTDC
: DC link Voltage
f : Switching frequency
L : Inductance of PFC inductor
OUTDC
INOUTDCIN
L
fLV VVV
I
PP
)( 


fL
V
IOUTDC
MAXL
PP
4
)( 
(
OUTDCIN
VV 2
1
)
AI
MAXL
PP 5)(  

][475
4000020 380 20 H f
V
LOUTDC  


(fs=40kHz)
Current ripple is decided by switching frequency and inductance. To reduce current ripple, high
switching frequency and large inductance value is required. It means that employing higher switching
frequency can reduce inductor size. But the power losses will increase and it requires more efficient heat
sink structure.
Open Loop Response
Fig.3 Block diagram of PFC control IC
6

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
7
The following is the block diagram of PFC controller ucc3818. The average current mode control is
composed of two types of loops- voltage loop and current loop. The voltage loop controls the output DC-Link
voltage. It regulates the output voltage. There is a 120[Hz] ripple voltage in the output DC-Link, which is
caused by the 60[Hz] ac input current. Hence, the voltage loop must be designed to be slow enough to reject
the 120[Hz] ripple voltage.
In general CCM (Continuous Current Mode) PFC IC, there is a multiplier. It multiplies VEA(the output of
voltage loop) by IAC(reference of input ac current shape) and then divides it by VRMS(reference of rms input
voltage). The output( 2
RMS
ACEA
MO V
IV
KI   ) of a multiplier is the reference of the PFC’s input current(IAC).
The difference between the voltage of IMO pin(output of the multiplier) and the voltage of the current
sensing resister is amplified by the current loop. The VEA(output of the current loop) is the reference voltage
to the comparameter that generates the gating signal. Current loop should be fast enough to catch up with
the 120[Hz] input ac current. But too fast speed can distort the current shape due to the switching noise.
Therefore, the current loop must be designed to be fast enough to catch up with the 120[Hz] rectified input
current, but not too fast for switching noise immunity.
Current Loop Amplifier
Eq. 1 shows the open loop response of power stage. (Refer to UCC3818 datasheet)
sL
RV
sV sV
GSHDC
IAOUT
S
PST 4)(
)(  (UCC3818) (Eq.1)
where: VS: Voltage of shunt resistor
V
IAOUT : Voltage of RMO
V
DC : DC link Voltage
R
SH : Shunt resistance for current sensing (2mohm)
L : PFC inductance
s : j(= j2f)
Voltage Loop Amplifier
Eq. 2 shows the open loop response of power stage. (Refer to UCC3818 datasheet)
EAOUTOUTDCOUT
IN
LOV VVsC P
G 
... (UCC3818) (Eq.2)
where: PIN : Input power
C
OUT : DC link capacitance
VOUTDC : DC link voltage
VEAOUT : Error amplifier output difference (5V)

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
8
s : j(= j2f)
Control Loop Implementation
Current Loop
[Step 1] Crossover frequency
Theoretical crossover frequency is given by following equation.
kHz
f
fS
C7.6
6 (Eq.3)
[Step 2] Fz and Fp decision
kHz
f
fC
Z3.3
2 , kHzff ZP 206 
[Step 3] Rz, Cp, Cz decision
Riis same to RMO. (Refer to “other parameters” in page 10)
Ri= 470[Ω],
In Eq.1, dB
Lf
RV
sL
RV
G
C
SHDCSHDC
kHzfPST C8.390103.0
)2(44
6.6  

Therefore it requires 40dB boosting at fc(=6.6kHz).
Rzis given by Eq.7.
dB
R
R
G
i
z
dB 40log20  Rz= 47[kΩ],
From Eq.4 ,Eq.5, Cp and Cz is given.
Cp= 180[pF], Cz= 1[nF]
zz
zCR
f
 21
(Eq.4)
pzz
pz
pCCR
CC
f
 2

(Eq.5)

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
9
Ri
Cp
Cz
Rz
IA +
CAOUT
IA -
RMO
Fig.4 Current loop circuit
Fig.5 Desired current error amplifier response
[1]
zi
dB CfR
G
 21
log20
(Eq.6)
[2]
i
z
dB R
R
Glog20(Eq.7)
[3]
pi
dB CfR
G
 21
log20
(Eq.8)
FZ=3.3kHz
FC=6.7kHz
FP=20kHz

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
10
Voltage Loop
ffVVsC P
G
EAOUTOUTDCOUT
IN
LOV 419
5380001.02 5000
... 





A resistor(RVD) is added between E/A input and sensing resistor. By virtue of large RVD, CVF can be
replaced by small SMD type capacitor.
 kRVD 120 (>RVS)
 MRR VDVF 18 (>RVD)
120
21
VFVD
CV CR
f

CVF=1uF


HzfCV 3.1

CVF
RVF
Vre f EAOUT
EA-
Vdc
RVS
RVL RVD
Fig.6 Voltage loop circuit
Other Parameters
RT, CT: Switching frequency decision
TT CR
f6.0 
RT= 15[kΩ]
CT= 1[nF]
Fs= 40[kHz]
RMO: (Refer to fig.4)

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
11
][470471
10300 002.0250 6
_





GMMAX
sensepeakAC
MO I
RI
R
(Assuming the input current is 50ARMS @ VAC = 100VRMS)
RMO = 470[Ω]
Rsense = 0.002[Ω]( small resistance can cause distortions at low level current)
RAC & Optocoupler circuit:
Optocuopler: TLP180
RAC
RFF UCC3818
ISINE
VFF
CL
VCC
Optocoupler
1
2
5
4
RAX
CFF
RL
-
+
Rc1
Rc2
Fig.7 Input AC voltage sensing circuit
RAX and RLdepend on optocoupler :
][64
106 2270
2
3
max_
max_ 




k
I
V
R
LINEAR
RMS
AX
)245.0]([18181818 Wk




][18
105.0 93
max_
_

 k
I
V
R
AC
PEAKRL
AC
][390 
L
R
RC1 , RC2 , CL, and an op-ampISINE off-set compensation
CL= 1[uF], RC1 = 0[Ω], RC2 = 150[Ω],

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
12
VFF:
][4.1 VVFF (when, input voltage VAC = 90[VAC])
RFF = 33[kΩ], CFF = 100[uF]
Over Current Protection
OCP
OUT
R19
-
+
PFCM
VAC-
UCC3818
PKLIMIT
VREF(7.5V)
R40
R18
R37
R38
Fig.8 Over current protection circuit
The actual protection level can be slightly different from the calculated value. It depends on PCB
layout pattern. About demo board, the designed values are:
R18 = R40 = 1.2[kΩ], R19 = R37 = 82[kΩ], R38 = 1.5[kΩ]
And the expected OC levels are:
1) OCP level 1











401918
37
38
4018
19401918
194018
37
38 )( RRR
R
R
RR
RR
V
I
RRR RIRVRR
V
R
R
SH
REF
PK
PKSHREF
REF
][40 AIPK 

2) OCP level 2

4019
18
18
4019 RRR VR
I
IRV RRR
SH
REF
PK
PKSH
REF



][50 AIPK 


PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
13
Over Voltage Protection
Vdc
OVP1
OVP2
RX
RY
RZ
Fig.9 Over voltage protection circuit
About demo board, the designed values are:
RX= 15 [kΩ], RY= 1.8 [kΩ], RZ= 870 (270+270+330) [kΩ]
And the expected OC levels are:
1) OVP level 1
][4228
8.16 8.886
__
_
_VV
RR RRR
V
V
V
RRR RR OVREF
YX
ZYX
PKDC
PKDC
OVREF
ZYX
YX 





2) OVP level 2
][4435.7
158.886
_
_
VV
RRRR
V
VV RRR RREF
X
ZYX
PKDC
PKDC
REF
ZYX
X




PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
14
DC-link Voltage Control
CVF
RVF
Vref EAOUT
EA-
Vdc
RVS1
RVL
RVD
RD1
RD2 VSIG
Outer
OP-AMP
RVS2
Fig.10 DC link voltage control circuit
The relation between VDC and parameters is:
SIG
DD
D
VS
VL
EA
VS
VDVL
VLVD
VFVF
VD
VSVFVSVF
VD
VLDC V
RR R R
R
V
R
RR
RR
RR
R
RRRR
R
RV 

































21
1
1111
1
1
11
5.7
The variable VDC voltage is available by just changing VSIG voltage. VEA, the output of voltage error
amplifier changes from 0 to 5.5V as its load current. In no load condition, VEA value is almost zero. And the
voltage of VDC will be the highest value. The next graph shows VSIG and VDC voltage. The voltage of VDC in
low load condition is higher than that of max. load condition.
Fig.11. DC link voltage vs. control voltage
Min. load
Max. load
VSIG [V]
VDC [V]

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
15
4. Experimental Results
Fig. 12 shows the overall schematics of implemented PFC converter. Table 2 shows the components
that are used for the implemented hardware. Fig. 13 shows the input ac current and DC-link voltage
waveforms. These figures’ details are shown in table 3.
Fig.12. Schematic diagram of the implemented PFC converter.
15

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
16
Table 2. BOM of PFC SPM® demo board.
16

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
17
Fig. 13. Full load test results (I
IN
= 16A
RMS
)
Table 3. Power factor and input power measurement.
V
AC
[V] I
AC
[A] Power [kW] Power Factor [%]
Fig.13 220 16
3.5 99
* V
AC
and I
AC
are RMS values
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HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF
THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE
UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
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CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
I
IN
(10A/div)
V
DC
(50V/div)
17

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ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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