ON Semiconductor Fairchild PFC SPM Guide

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PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
1
Application Note AN-9041
PFC SPM® Design Guide with Analog PFC IC
Written by:
Application Engineering Part
Motion Control System Team
HV PCIA
FAIRCHILD SEMICONDUCTOR

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
2
Contents
1. System Configurations...........................................................................3
2. Protection Circuits..................................................................................3
Over Current Protection (OCP).............................................................................................................. 3
Over Voltage Protection......................................................................................................................... 4
Under Voltage Protection....................................................................................................................... 4
3. Design Example (PFC SPM® DEMO BOARD) ......................................5
Operating conditions of PFC SPM® demo board: .................................................................................. 5
Output capacitance and Inductance design............................................................................................ 5
Output Voltage Ripple & Output Capacitance...................................................................................... 5
Inductance & Input Current Ripple ....................................................................................................... 6
Open Loop Response ............................................................................................................................... 6
Current Loop Amplifier .......................................................................................................................... 7
Voltage Loop Amplifier .......................................................................................................................... 7
Control Loop Implementation................................................................................................................ 8
Current Loop .......................................................................................................................................... 8
Voltage Loop......................................................................................................................................... 10
Other Parameters ................................................................................................................................. 10
Over Current Protection....................................................................................................................... 12
Over Voltage Protection....................................................................................................................... 13
DC-link Voltage Control .......................................................................................................................... 14
4. Experimental Results ...........................................................................15
NOTE:
In this and other Fairchild documentation and collateral, the following terms are interchangeable:
DIP = SPM2, Mini-DIP = SPM3, Tiny-DIP = SPM5, µMini-DIP = SPM45H, PFCM = PFC SPM®.

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
3
1. System Configurations
Control IC
Vac
N/F
Relay
LVIC
VTH
RTH
S
R
PR
N
NSENSE
VAC-
Shunt
Resistor
NTC
Thermistor
SPM
IN(S)
IN(R)
Fig.1 Typical block diagram of PFC SPM® system
An inrush-current prevention circuit is required due to the large DC link capacitance as shown in Fig. 1.
The relay of the circuit should be closed after DC link capacitor is charged far enough. PFC SPM®, mini-
SPM and control IC can share single GND stage. Usually, this GND and the NSENSE terminal of PFC SPM
should have the same potential. Large surge voltage is easily produced between P and N terminals by large
current switching. To reduce surge voltage it is important to shorten the DC link bus wiring between PFC
SPM and DC link capacitor. In addition, good high frequency characteristic capacitor, such as polypropylene
film capacitor should be mounted near to P and N terminals as a snubber.
2. Protection Circuits
Following Fig. 2 shows the timing chart of protection function. There are two kind of protection level
for both OCP and OVP. Generally, PFC control ICs have its own OCP and OVP function. Also, user can
make the PFC SPM® stop and output the FO signal under preset OC, OV condition using its Csc input.
Over Current Protection (OCP)
[OCP Level1 –PFC SPM®] PFC SPM can protect from over current situation. When OC(over current)
situation happens, the PFC SPM stops operating and generates fault out signal during fault-out duration
time(set by CFOD). And then after the duration, it works again according to the input command. Its total
propagation delay time may depend on outer op-amp speed. We recommend using a low cost slow op-amp
solution with fast protection. It is the OCP level2 protection described in next paragraph.
[OCP Level2 (SCP) –PFC control IC] By the peak current limit function of PFC control IC, the system
is protected from SC(Short Circuit) situation. The recommended current limit of OCP level 2 is higher than
that of OCP level 1. It doesn’t generate the fault out signal but its response is very fast. It will protect the
system from short circuit situation during the propagation delay time of OCP level1.

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
4
Over Voltage Protection
OV (Over Voltage) protection can be also implemented by dual protection. The DC-link voltage
changes slowly because of its large capacitance. So OVP does not need fast response. Therefore it is
optional to activate the OVP of PFC controller.
[OVP Level 1 - PFC controller] OVP level 1 suppresses voltage overshoot in transient situation. It
doesn’t generate fault out signal.
[OVP Level 2 – PFC SPM®] The voltage level of OVP level 2 is higher than that of OVP level 1.
When OV situation happens, the PFC SPM stops operating and generates fault out signal during fault-out
duration time(set by CFOD). And then it works again.
Under Voltage Protection
IGBT gate will be interrupted when control voltage drops below UV trip level, and the protection will be realeased
automatically if the control voltage recovers to the UV reset level.
Fig.2 Timing chart of protection function

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
5
3. Design Example (PFC SPM® DEMO BOARD)
A general PFC example is implemented for 5[kW] air-conditioning applications whose input voltage is
187~276[V].
Operating conditions of PFC SPM® demo board:
Table 1. The operating conditions.
Item Symbol Value Unit
1 Switching Frequency Fsw 40 KHz
2 Minimum Input Voltage Vimin 176 Vac
3 Nominal Input Voltage Vinom 220 Vac
4 Maximum Input Voltage Vimax 264 Vac
5 Output Max. Power Po 5000 W
6 Minimum Output Voltage Vomin 350 Vdc
7 Nominal Output Voltage Vonom 380 Vdc
8 OVP level 1 V
OV1
420 V
9 OVP level 2 V
OV2
440 V
10 Peak Ripple Current Iripple 5A
11 OCP Level1 Iocp1 40 A
12 OCP Level2 (SCP) Iocp2 50 A
13 Shunt Resistor Rsh 2 MOhm
14 DC Capacitor Cout 940 uF
Output capacitance and Inductance design
Output Voltage Ripple & Output Capacitance
Voltage ripple of V
DC
can be reduced by employing large C
OUT
. In demo board, C
OUT
is set to 940[µF]
(470[µF] x 2)
5

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
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Inductance & Input Current Ripple
where: I
Lp-p
: Peak to peak current of PFC inductor
V
IN
: Input AC voltage
V
OUTDC
: DC link Voltage
f : Switching frequency
L : Inductance of PFC inductor
OUTDC
INOUTDCIN
L
fLV VVV
I
PP
)( 


fL
V
IOUTDC
MAXL
PP
4
)( 
(
OUTDCIN
VV 2
1
)
AI
MAXL
PP 5)(  

][475
4000020 380 20 H f
V
LOUTDC  


(fs=40kHz)
Current ripple is decided by switching frequency and inductance. To reduce current ripple, high
switching frequency and large inductance value is required. It means that employing higher switching
frequency can reduce inductor size. But the power losses will increase and it requires more efficient heat
sink structure.
Open Loop Response
Fig.3 Block diagram of PFC control IC
6

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
7
The following is the block diagram of PFC controller ucc3818. The average current mode control is
composed of two types of loops- voltage loop and current loop. The voltage loop controls the output DC-Link
voltage. It regulates the output voltage. There is a 120[Hz] ripple voltage in the output DC-Link, which is
caused by the 60[Hz] ac input current. Hence, the voltage loop must be designed to be slow enough to reject
the 120[Hz] ripple voltage.
In general CCM (Continuous Current Mode) PFC IC, there is a multiplier. It multiplies VEA(the output of
voltage loop) by IAC(reference of input ac current shape) and then divides it by VRMS(reference of rms input
voltage). The output( 2
RMS
ACEA
MO V
IV
KI   ) of a multiplier is the reference of the PFC’s input current(IAC).
The difference between the voltage of IMO pin(output of the multiplier) and the voltage of the current
sensing resister is amplified by the current loop. The VEA(output of the current loop) is the reference voltage
to the comparameter that generates the gating signal. Current loop should be fast enough to catch up with
the 120[Hz] input ac current. But too fast speed can distort the current shape due to the switching noise.
Therefore, the current loop must be designed to be fast enough to catch up with the 120[Hz] rectified input
current, but not too fast for switching noise immunity.
Current Loop Amplifier
Eq. 1 shows the open loop response of power stage. (Refer to UCC3818 datasheet)
sL
RV
sV sV
GSHDC
IAOUT
S
PST 4)(
)(  (UCC3818) (Eq.1)
where: VS: Voltage of shunt resistor
V
IAOUT : Voltage of RMO
V
DC : DC link Voltage
R
SH : Shunt resistance for current sensing (2mohm)
L : PFC inductance
s : j(= j2f)
Voltage Loop Amplifier
Eq. 2 shows the open loop response of power stage. (Refer to UCC3818 datasheet)
EAOUTOUTDCOUT
IN
LOV VVsC P
G 
... (UCC3818) (Eq.2)
where: PIN : Input power
C
OUT : DC link capacitance
VOUTDC : DC link voltage
VEAOUT : Error amplifier output difference (5V)

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
8
s : j(= j2f)
Control Loop Implementation
Current Loop
[Step 1] Crossover frequency
Theoretical crossover frequency is given by following equation.
kHz
f
fS
C7.6
6 (Eq.3)
[Step 2] Fz and Fp decision
kHz
f
fC
Z3.3
2 , kHzff ZP 206 
[Step 3] Rz, Cp, Cz decision
Riis same to RMO. (Refer to “other parameters” in page 10)
Ri= 470[Ω],
In Eq.1, dB
Lf
RV
sL
RV
G
C
SHDCSHDC
kHzfPST C8.390103.0
)2(44
6.6  

Therefore it requires 40dB boosting at fc(=6.6kHz).
Rzis given by Eq.7.
dB
R
R
G
i
z
dB 40log20  Rz= 47[kΩ],
From Eq.4 ,Eq.5, Cp and Cz is given.
Cp= 180[pF], Cz= 1[nF]
zz
zCR
f
 21
(Eq.4)
pzz
pz
pCCR
CC
f
 2

(Eq.5)

PFC SPM®Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
9
Ri
Cp
Cz
Rz
IA +
CAOUT
IA -
RMO
Fig.4 Current loop circuit
Fig.5 Desired current error amplifier response
[1]
zi
dB CfR
G
 21
log20
(Eq.6)
[2]
i
z
dB R
R
Glog20(Eq.7)
[3]
pi
dB CfR
G
 21
log20
(Eq.8)
FZ=3.3kHz
FC=6.7kHz
FP=20kHz