ON Semiconductor NCP2824FCT2GEVB User manual

©Semiconductor Components Industries, LLC, 2012
May, 2012 −Rev. 2
1Publication Order Number:
EVBUM2110/D
NCP2824FCT2GEVB
NCP2824FCT2 Evaluation
Board User's Manual
Overview
The NCP2824 is a Filterless Class D amplifier capable of
delivering up to 2.4 W to a 4 Wload with a 5 V supply
voltage. With the same battery voltage, it can deliver 1.2 W
to an 8 Wload with less than 1% THD+N. The Non-clipping
function adjusts automatically the output voltage in order to
control the distortion when an excessive input is applied to
the amplifier. This adjustment is done thanks to an
Automatic Gain Control circuitry (AGC) built-in the chip.
A simple Single wire interface allows to enable/disable the
non Clipping function and also to configure the maximum
distortion level in the output. A programmable power limit
function is also embedded in order to protect speakers from
damage caused by an excessive sound level.
The intent of the evaluation boards is to illustrate typical
operation of the NCP2824 device for laboratory
characterization. The NCP2824FCT2GEVB schematic is
depicted in Figure 2.
Figure 1. NCP2824FCT2GEVB Board Picture
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EVAL BOARD USER’S MANUAL

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BOARD SCHEMATIC
Figure 2. NCP2824FCT2GEVB Evaluation Board Schematic
Title
Size Document Number Rev
Date: Sheet of
NCP2824 EVB TLS−P−001−A−0310−DR
NCP2824 EVB
Custom
11
U1
NCP2824
INP
A1
VDD A2
OUTP A3
AGND
B1
NC
B2
PGND
B3
INM
C1
CNTL
C2 OUTM C3
C1
100n
C2
100n
C3
4.7μF
0
OUTN
OUTP
0 0
J1
Jumper3
11
22
33
0
Vdd
J2
Jumper2
11
22
J3
Jumper2
11
22
0
0
Î
ÎÎ
J4
CUT H
1
122
Î
Î
ÎÎ
ÎÎ
J5
CUT H
1
122
INPF
ÎÎ
ÎÎ
J6
TP 1.0D
1
1
ÎÎ
ÎÎ
J7
TP 1.0D
1
1
ÎÎ
ÎÎ
J8
TP 1.0D
1
1
CNTL
ÎÎ
ÎÎ
J9
TP 1.0D
1
1
Vdd
ÎÎ
ÎÎ
J10
TP 1.0D
1
1
ÎÎ
ÎÎ
J11
TP 1.0D
11
ÎÎ
ÎÎ
ÎÎ
ÎÎ
J13
GND
1
122
00
INMF
J14
CON2
1
1
2
2
0
J15
CON2
1
1
2
2
C4
NC
0
C5
100μF−NC
C6
4.7μF
0
J16
FIX 3.2 H
1
1
J17
FIX 3.2 H
1
1
J18
FIX 3.2 H
1
1
J19
FIX 3.2 H
1
1
0
ÎÎ
ÎÎ
J12
TP 1.0D
1
1
ENABLE−SINGLE WIRE
BOARD FIXATION HOLES
POWER SUPPLY
SPEAKER CONNECTION

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OPERATION
The operating power supply of the NCP2824 is from 2.5
to 5.5 V. The absolute maximum input voltage is 7.0 V. A
power supply set to 3.6 V and current limit set to at least
1.5 A must be connected to J14 connector to powering the
NCP2824EVB/D. Also to compensate for parasitic
inductance of wires between the power supply and the
evaluation board it is highly recommended to connect a
470 mF electrolytic capacitor to bypass J14 terminal. Like
this the device can be evaluated under powering condition
very similar that battery power supplies.
Performances of EVB Solution
To be as close as possible with final handset application,
the design of this power conversion solution used small size
footprints where possible. Changing components may
positively or negatively impact the evaluation board
performance illustrated in Figure 3 to 8. For more
information please refer to the NCP2824 datasheet.
Single Wire Interface Operation
The single wire interface allows changing the default
configuration of the NCP2824.
After Wake up, the NCP2824 is configured with:
•AGC enable
•Non Clip + Power limit
•Gain = 18 dB
•THD max = 1%
The following table described all the NCP2824
configurations.
Table 1. NCP2824 CONFIGURATION
Pulse
Counting Register Description
01 AGC AGC disable
02 AGC Enable
03 Reset Reset configuration
04 Gain
Control
Gain = 12 dB
05 Gain = 18 dB
06 THD
Control
1%
07 2%
08 4%
09 6%
10 8%
11 10%
12 15%
13 20%
14 NC+L Non Clip + Power limit
15 NC Non Clip only
16 Power
Limit
Control
0.45 VPeak
17 0.9 VPeak
18 1.35 VPeak
19 1.8 VPeak
20 2.25 VPeak
21 2.7 VPeak
22 3.15 VPeak
23 3.6 VPeak
Single Wire commands can easily be emulated using a
pulse generator configured in accordance with the Single
wire specification, for more information about timings
please refers to NCP2824 datasheet.

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Table 2. BOARD CONNECTIONS
INPUT POWER
Symbol Descriptions
J14−1This is the positive connection for power supply. The leads (positive + ground) to the input supply should
be twisted and kept as short as possible.
J14−2This is the return connection for the power supply (Ground signal)
J13 Ground clip
AUDIO
Symbol Descriptions
J3 Positive Audio input
J2 Negative Audio input
J15−2Positive Audio output
J15−1Negative Audio output
SWITCHES SETUP
Symbol Switch Descriptions
J1 Enable
J4 Short input capacitor on positive input
J5 Short input capacitor on negative input
J2 Connect the positive audio input to Gnd
J3 Connect the negative audio input to Gnd
TEST POINT
Symbol Switch Descriptions
J12 This test point is directly connected to the GND
J9 This test point is directly connected to the Vdd pin
J6 This test point is connected to the positive audio input
J7 This test point is connected to the negative audio input
J10 This test point is connected to the positive audio output
J11 This test point is connected to the negative audio output

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TYPICAL OPERATING CHARACTERISTICS
Figure 3. THD vs. POUT , RI = 8 W, f = 1 kHz Figure 4. THD vs. POUT , RI = 4 W, f = 1 kHz
THD+N vs Pout @ 25°C
0.01
0.1
1
10
100
10 100 1000 10000
Pout (mW)
THD (%)
Vdd=2.5V Vdd=2.7V Vdd=3V Vdd=3.6V Vdd=4.2V Vdd=5V Vdd=5.5V
THD+N vs Pout @ 255C
0.01
0.1
1
10
100
10 100 1000 10000
Pout (mW)
THD (%)
Vdd=2.5V Vdd=2.7V Vdd=3V Vdd=3.6V Vdd=4.2V Vdd=5V Vdd=5.5V
Figure 5. Efficiency vs. POUT , RI = 8 W, f = 1 kHz Figure 6. THD vs. Frequency, RI = 8 W,
POUT = 250 mW
Eff vs Pout @ Vdd=3.6V
0
10
20
30
40
50
60
70
80
90
100
0 200 400 600 800 1000
Pout (mW)
(%)
RL = 8 W
THD ve rsus Fre que ncy @ Vdd=3.6V
0.001
0.01
0.1
1
10
10 100 1000 10000 100000
Freq (Hz)
THD+N (%)
Pout=250mW Pout=500mW
Figure 7. Peak Output Voltage in Power Limit vs. Input
Voltage (rms) and Power Limit Settings, Av = 12 dB Figure 8. PSRR vs. Frequency
Peakvoltage vs. Vinfor VDD=5V
Temp=25 5C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin(V)
(V)
Vpeak Target=0.45V Vpeak Target=0.9V Vpeak Target=1.35V Vpeak Target=1.8V
Vpeak Target=2.25V Vpeak Target=2.7V Vpeak Target=3.15V Vpeak Target=3.6V
PSRR vs Frequency (Inputs grounded, Gain = 12 dB, Cin = 1 mF)
−80
−70
−60
−50
−40
−30
−20
−10
0
10 100 1000 10000 100000
Fr e q (Hz)
PSRR (dB)
Vdd=3V Vdd=3.6V Vdd=5V

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PCB LAYOUT
As with all Class D amplifiers, care must be observed to
place the components on the PCB and layout the critical
nodes. The evaluation board is made of 4 PCB layers where
first internal layer is a GND. Figure 9, Figure 10 and
Figure 11 show the layout of the NCP2824FCT2GEVB
board.
For more specific layout guidelines please refer to the
NCP2824 datasheet.
Figure 9. Assembly Layer TOP
Figure 10. Top Layer Routing

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Figure 11. Bottom Layer Routing
Table 3. BILL OF MATERIALS
Qty Ref Des. Description Size Manufacturer Part Number
1 U1 NCP2824 CSP−9
1.45 x 1.45
mm
ON Semiconductor NCP2824
2C1, C2 Capacitor, Ceramic 100 nF 0603 KEMET C0603C104K5RAC
2C3, C6 Capacitor, Ceramic 4.7 mF 6.3 V 0603 KEMET C0603C475K9PAC
2J14, J15 Mal. SL5.08/2/90B plus Fem. BLZ
5.08/2
Weidmuller SL5.08/2/90 +
BLZ 5.08/2
3 J1 Header 3 pin, 100 mil spacing 0.100 x 2 Std Std
2J2, J3 Header 2 pin, 100 mil spacing 0.100 x 2 Std Std
1 J6 GND Connection Std Std
9J6, J7, J9, J10,
J11, J12, J13
Test Point Std Std
2J4, J5 Soldering point must be connected
1 PCB PCB 2.0 in x 2.0 in x 1.0 mm, 4 Layers Any TLS−P−001−A−0310−RD
NOTE: C3 is not mounted
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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