ON Semiconductor NCP1608BOOSTGEVB User manual

©Semiconductor Components Industries, LLC, 2012
November, 2012 −Rev. 1
1Publication Order Number:
EVBUM2162/D
NCP1608BOOSTGEVB
NCP1608 100 W Boost
Evaluation Board User's
Manual
Introduction
The NCP1608 is a voltage mode power factor correction
(PFC) controller designed to implement converters to
comply with line current harmonic regulations. The device
operates in critical conduction mode (CrM) for optimal
performance in applications up to 350 W. Its voltage mode
scheme enables it to obtain near unity power factor (PF)
without the need for a line-sensing network. The output
voltage is accurately controlled with an integrated high
precision transconductance error amplifier. The controller
also implements a comprehensive set of safety features that
simplify system design.
This application note describes the design and
implementation of a 400 V, 100 W, CrM boost PFC
converter using the NCP1608. The converter exhibits high
PF, low standby power dissipation, high active mode
efficiency, and a variety of protection features.
The Need for PFC
Most electronic ballasts and switch−mode power supplies
(SMPS) use a diode bridge rectifier and a bulk storage
capacitor to produce a dc voltage from the utility ac line.
This causes a non-sinusoidal current consumption and
increases the stress on the power delivery infrastructure.
Government regulations and utility requirements mandate
control over line current harmonic content. Active PFC
circuits are the most popular method to comply with these
harmonic content requirements. System solutions consist of
connecting a PFC pre−converter between the rectifier bridge
and the bulk capacitor (Figure 1). The boost converter is the
most popular topology for active PF correction. It produces
a constant output voltage and consumes a sinusoidal input
current from the line.
Figure 1. Active PFC Stage with the NCP1608
Rectifiers
+
AC Line High
Frequency
Bypass
Capacitor
NCP1608
PFC Pre−Converter Converter
Load
+Bulk
Storage
Capacitor
Basic Operation of a CrM Boost Converter
For medium power (< 350 W) applications, CrM is the
preferred control method. CrM operates at the boundary
between discontinuous conduction mode (DCM) and
continuous conduction mode (CCM). In CrM, the drive on
time begins when the inductor current reaches zero.
CrM combines the reduced peak current of CCM
operation with the zero current switching of DCM
operation. This control method causes the frequency to vary
with the instantaneous line input voltage (Vin) and the output
load. The operation and waveforms of a CrM PFC boost
converter are illustrated in Figure 2. For detailed
information on the operation of a CrM boost converter for
PFC applications, please refer to AND8123 at
www.onsemi.com.
http://onsemi.com
EVAL BOARD USER’S MANUAL

NCP1608BOOSTGEVB
http://onsemi.com
2
Figure 2. Schematic and Waveforms of an Ideal CrM Boost Converter
Diode Bridge
AC Line
+
−
L
Diode Bridge
AC Line
+
−
L+
The power switch is ON The power switch is OFF
Critical Conduction Mode:
Next current cycle starts
when the core is reset.
Inductor
Current
+
With the power switch voltage being about zero, the
input voltage is applied across the inductor. The induct-
or current linearly increases with a (Vin/L) slope.
The inductor current flows through the diode. The inductor
voltage is (Vout −Vin) and the inductor current linearly decays
with a (Vout −Vin)/L slope.
Vout
(Vout −Vin)/L
IL(peak)
IL
Vin
Vdrain
Vdrain
Vin/L
Vout
Vin
If next cycle does not start
then Vdrain rings towards Vin
+
IL
Vin Vdrain
Features of the NCP1608
The NCP1608 is an excellent controller for robust
medium power CrM boost PFC applications due to its
integrated safety features, low impedance driver, high
precision error amplifier, and low standby current
consumption.
For detailed information on the operation of the
NCP1608, please refer to NCP1608/D at www.onsemi.com.
A CrM boost pre-converter featuring the NCP1608 is
shown in Figure 3.
Figure 3. CrM Boost PFC Stage Featuring the NCP1608
+
AC Line EMI
Filter
1
4
3
2
8
5
6
7
+Cbulk
LOAD
(Ballast,
SMPS, etc.)
NCP1608
Vout
Rsense
Cin
RZCD
Rout1
Rout2
CCOMP
VCC
Ct
D
L
FB
Control
Ct
CS
GND
ZCD
DRV
VCC
Vin
NB:NZCD
M
The FB pin senses the boost output voltage through the
resistor divider formed by Rout1 and Rout2. The FB pin
includes overvoltage protection (OVP), undervoltage
protection (UVP), and floating pin protection (FPP). This
pin is the input to the error amplifier. The output of the error
amplifier is the Control pin.
A combination of resistors and capacitors connected
between the Control and ground pins forms a compensation
network that limits the bandwidth of the converter. For high
PF, the bandwidth is set to less than 20 Hz. A capacitor
connected to the Ct pin sets the maximum on time. The CS
pin provides cycle−by−cycle overcurrent protection. The

NCP1608BOOSTGEVB
http://onsemi.com
3
internal comparator compares the voltage developed across
Rsense (VCS) to an internal reference (VILIM). The driver
turns off when VCS reaches VILIM. The ZCD pin senses the
demagnetization of the boost inductor to turn on the drive.
The drive on time begins after the ZCD pin voltage (VZCD)
exceeds VZCD(ARM) and then decreases to less than
VZCD(TRIG). A resistor in series with the ZCD winding
limits the ZCD pin current.
The NCP1608 features a powerful output driver on the
DRV pin. The driver is capable of switching the gates of
large MOSFETs efficiently because of its low source and
sink impedances. The driver includes active and passive
pull−down circuits to prevent the output from floating high
when the NCP1608 is disabled.
The VCC pin is the supply pin of the controller. When VCC
is less than the turn on voltage (VCC(on)), the current
consumption of the device is less than 35 mA. This results in
fast startup times and reduced standby power losses.
Design Procedure
The design of a CrM boost PFC converter is discussed in
many ON Semiconductor application notes. Table 1 lists
some examples.
This application note describes the design procedure for
a 400 V, 100 W converter using the features of the NCP1608.
A dedicated NCP1608 design tool that enables users to
determine component values quickly is available at
www.onsemi.com.
Table 1. Additional Resources for the Design and Understanding of CrM Boost PFC Circuits Available at
www.onsemi.com.
AND8123 Power Factor Correction Stages Operating in Critical Conduction Mode
AND8016 Design of Power Factor Correction Circuits Using the MC33260
AND8154 NCP1230 90 W, Universal Input Adapter Power Supply with Active PFC
HBD853 Power Factor Correction Handbook
DESIGN STEP 1: Define the Required Parameters
The converter parameters are shown in Table 2.
Table 2. CONVERTER PARAMETERS
Parameter Name Symbol Value Units
Minimum Line Input Voltage VacLL 85 Vac
Maximum Line Input Voltage VacHL 265 Vac
Minimum Line Frequency fline(MIN) 47 Hz
Maximum Line Frequency fline(MAX) 63 Hz
Output Voltage Vout 400 V
Full Load Output Current Iout 250 mA
Full Load Output Power Pout 100 W
Maximum Output Voltage Vout(MAX) 440 V
Minimum Switching Frequency fSW(MIN) 40 kHz
Minimum Full Load Efficiency h92 %
Minimum Full Load Power Factor PF 0.9 −
DESIGN STEP 2: Calculate the Boost Inductor
The value of the boost inductor (L) is calculated using
Equation 1:
Lv
Vac2@ǒVout
2
Ǹ*VacǓ@h
2
Ǹ@Vout @Pout @fSW(MIN)
(eq. 1)
To ensure that the switching frequency exceeds the
minimum frequency, L is calculated at both the minimum
and maximum rms input line voltage:
LLL v
852@ǒ400
2
Ǹ*85Ǔ@0.92
2
Ǹ@400 @100 @40 k +581 mH
Where LLL is the inductor value calculated at VacLL.
LHL v
2652@ǒ400
2
Ǹ*265Ǔ@0.92
2
Ǹ@400 @100 @40 k +509 mH
Where LHL is the inductor value calculated at VacHL.
A value of 400 mH is selected. The inductance tolerance
is ±15%. The maximum inductance (LMAX) value is
460 mH. Equation 2 is used to calculate the minimum
frequency at full load.
fSW +Vac2@h
2@LMAX @Pout @ǒ1*2
Ǹ@Vac
Vout Ǔ(eq. 2)

NCP1608BOOSTGEVB
http://onsemi.com
4
fSW(LL) +852@0.92
2@460 m@100 @ǒ1*2
Ǹ@85
400 Ǔ+50.5 kHz
fSW(HL) +2652@0.92
2@460 m@100 @ǒ1*2
Ǹ@265
400 Ǔ+44.3 kHz
fSW is equal to 50.5 kHz at VacLL and 44.3 kHz at VacHL.
DESIGN STEP 3: Size the Ct Capacitor
The Ct capacitor is sized to set the maximum on time for
minimum line input voltage and maximum output power.
The maximum on time is calculated using Equation 3:
ton(MAX) +2@LMAX @Pout
h@VacLL 2(eq. 3)
ton(MAX) +2@460 m@100
0.92 @852+13.8 ms
Sizing Ct to an excessively large value causes the
application to deliver excessive output power and reduces
the control range at VacHL or low output power. It is
recommended to size the Ct capacitor to a value slightly
larger than that calculated by Equation 4:
Ct w
2@Pout @LMAX @Icharge
h@VacLL 2@VCt(MAX)
(eq. 4)
Where Icharge and VCt(MAX) are specified in the NCP1608
datasheet. To ensure that the controller sets the maximum on
time to a value sufficient to deliver the required output
power, the maximum Icharge and the minimum VCt(MAX)
values are used in the calculations for Ct.
From the NCP1608 datasheet:
−VCt(MAX) = 4.775 V (minimum)
−Icharge = 297 mA (maximum)
Ct is equal to:
Ct w2@100 @460 m@297 m
0.92 @852@4.775 +860 pF
A normalized value of 1 nF (±10%) provides sufficient
margin. A value of 1.22 nF is selected for Total Harmonic
Distortion (THD) reduction (see the Additional THD
Reduction section of this application note for more
information).
DESIGN STEP 4: Determine the ZCD Turns Ratio
To activate the ZCD detector of the NCP1608, the ZCD
turns ratio is sized such that at least VZCD(ARM) (1.55 V
maximum) is applied to the ZCD pin during all operating
conditions (see Figure 4). The boost winding to ZCD
winding turns ratio (N = NB:NZCD) is calculated using
Equation 5.
Nv
Vout *ǒ2
Ǹ@VacHLǓ
VZCD(ARM)
(eq. 5)
Nv
400 *ǒ2
Ǹ@265Ǔ
1.55 +16
Figure 4. Realistic CrM Waveforms Using a ZCD
Winding with RZCD and the ZCD Pin Capacitance
DRV
0 A
0 V
0 V
0 V
0 V
Diode Conduction
MOSFET Conduction
tz
RZCD
Delay
Minimum Voltage Turn on
ton
toff
TSW
tdiode
VCL(NEG)
VZCD(TRIG)
VZCD(ARM)
VCL(POS)
VZCD(WIND),on
VZCD
VZCD(WIND),off
VZCD(WIND)
Vout
Vdrain
IL(peak)
IL
IL(NEG)
A turns ratio of 10 is selected for this design. RZCD is
connected between the ZCD winding and the ZCD pin to
limit the ZCD pin current. This current must be limited
below 10 mA. RZCD is calculated using Equation 6:
RZCD w2
Ǹ@VacHL
IZCD(MAX) @N(eq. 6)
RZCD w2
Ǹ@265
10 m @10 +3.75 kW
The value of RZCD and the parasitic capacitance of the
ZCD pin determine when the ZCD winding signal is
detected and the drive turn on begins. A large RZCD value
creates a long delay before detecting the ZCD event. In this
case, the controller operates in DCM and the PF is reduced.
If the RZCD value is too small, the drive turns on when the
drain voltage is high and efficiency is reduced. A popular
strategy for selecting RZCD is to use the RZCD value that
achieves minimum drain voltage turn on. This value is found
experimentally.
During the delay caused by RZCD and the ZCD pin
capacitance, the equivalent drain capacitance (CEQ(drain))
discharges through the path shown in Figure 5.

NCP1608BOOSTGEVB
http://onsemi.com
5
Figure 5. Equivalent Drain Capacitance Discharge Path
+
AC Line EMI
Filter
+
D
L
Iin
Cin
IL
Cbulk
Vout
CEQ(drain)
CEQ(drain) is the combined parasitic capacitances of the
MOSFET, the diode, and the inductor. Cin is charged by the
energy discharged by CEQ(drain). The charging of Cin reverse
biases the bridge rectifier and causes the input current (Iin)
to decrease to zero. The zero input current causes THD to
increase. To reduce THD, the ratio (tz/ TSW) is minimized,
where tZis the period from when IL= 0 A to when the drive
turns on. The ratio (tz/ TSW) is inversely proportional to the
square root of L.
DESIGN STEP 5: Set the FB, OVP, and UVP Levels
Rout1 and Rout2 form a resistor divider that scales down
Vout before it is applied to the FB pin. The error amplifier
adjusts the on time of the drive to maintain the FB pin
voltage equal to the error amplifier reference voltage
(VREF). The divider network bias current (Ibias(out))
selection is the first step in the calculation. The divider
network bias current is selected to optimize the tradeoff of
noise immunity and power dissipation. Rout1 is calculated
using the optimized bias current and output voltage using
Equation 7:
Rout1 +Vout
Ibias(out)
(eq. 7)
A bias current of 100 mA provides an acceptable tradeoff
of power dissipation to noise immunity.
Rout1 +400
100 m+4MW
The output voltage signal is delayed before it is applied to
the FB pin due to the time constant set by Rout1 and the FB
pin capacitance. Rout1 must not be sized too large or this
delay may cause overshoots of the OVP detection voltage.
Rout2 is dependent on Vout, Rout1, and the internal
feedback resistor (RFB, shown in the NCP1608 specification
table). Rout2 is calculated using Equation 8:
Rout2 +Rout1 @RFB
RFB @ǒVout
VREF *1Ǔ*Rout1
(eq. 8)
Rout2 +4M@4.6 M
4.6 M @ǒ400
2.5 *1Ǔ*4M+25.3 kW
Rout2 is selected as 25.5 kWfor this design.
Using the selected resistor, the resulting output voltage is
calculated using Equation 9:
Vout +VREF @ǒRout1 @Rout2 )RFB
Rout2 @RFB )1Ǔ(eq. 9)
Vout +2.5 @ǒ4M@25.5 k )4.6 M
25.5 k @4.6 M )1Ǔ+397 V
The low bandwidth of the PFC stage causes overshoots
during transient loads or during startup. The NCP1608
includes an integrated OVP circuit to prevent the output
from exceeding a safe voltage. The OVP circuit compares
VFB to the internal overvoltage detect threshold voltage to
determine if an OVP fault occurs. The OVP detection
voltage is calculated using Equation 10:
Vout(OVP) +VOVP
VREF @VREF @ǒRout1 @Rout2 )RFB Rout2 @RFB )1Ǔ
(eq. 10)
Vout(OVP) +1.06 @2.5 @
ǒ
4M@25.5 k )4.6 M
25.5 k @4.6 M )1
Ǔ
+421 V
The output capacitor (Cbulk) value is sized to be large
enough so that the peak-to-peak output voltage ripple
(Vripple(peak-peak)) is less than the OVP detection voltage.
Cbulk is calculated using Equation 11:
Cbulk wPout
2@p@Vripple(peak−peak) @fline @Vout
(eq. 11)
Where fline = 47 Hz is the worst case for the ripple voltage
and Vripple(peak-peak) < 42 V.
Cbulk w100
2@p@42 @47 @400 +20 mF

NCP1608BOOSTGEVB
http://onsemi.com
6
The value of Cbulk is selected as 68 mF to reduce
Vripple(peak-peak) to less than 15 V. This results in a peak
output voltage of 406.25 V, which is less than the peak output
OVP detection voltage (421 V).
The NCP1608 includes undervoltage protection (UVP).
During startup, Cbulk charges to the peak of the ac line
voltage. If Cbulk does not charge to a minimum voltage, the
NCP1608 detects an UVP fault. The UVP detection voltage
is calculated using Equation 12:
Vout(UVP) +VUVP @ǒRout1 @Rout2 )RFB
Rout2 @RFB )1Ǔ(eq. 12)
Vout(UVP) +0.31 @ǒ4M@25.5 k )4.6 M
25.5 k @4.6 M )1Ǔ+49 V
The UVP feature protects against open loop conditions in
the feedback loop. If the FB pin is inadvertently floating
(perhaps due to a bad solder joint), the coupling within the
system may cause VFB to be within the regulation range (i.e.
VUVP < VFB < VREF). The controller responds by delivering
maximum power. The output voltage increases and over
stresses the components. The NCP1608 includes a feature to
protect the system if FB is floating. The internal pull-down
resistor (RFB) ensures that VFB is below the UVP threshold
if the FB pin is floating.
If the FB pin floats during operation, VFB begins
decreasing from VREF. The rate of decrease depends on RFB
and the FB pin parasitic capacitance. As VFB decreases,
VControl increases, which causes the on time to increase until
VFB < VUVP
. When VFB < VUVP , the UVP fault is detected
and the controller is disabled. The sequence is depicted in
Figure 6.
Figure 6. UVP Operation if Loop is Opened During
Operation
Loop is Opened
UVP Fault
Ct(offset)
VEAH
VUVP
VREF
VFB
VControl
Vout
Vout
VCC
VCC(off)
VCC(on)
DESIGN STEP 6: Size the Power Components
The power components are sized such that there is
sufficient margin to sustain the currents and voltages applied
to them. At minimum line input voltage and maximum
output power the inductor peak current is at the maximum,
which causes the greatest stress to the power components.
The components are referenced in Figure 3.
1. The inductor peak current (IL(peak)) is calculated
using Equation 13:
IL(peak) +2
Ǹ@2@Pout
h@Vac (eq. 13)
IL(peak) +2
Ǹ@2@100
0.92 @85 +3.62 A
The inductor rms current (IL(RMS)) is calculated using
Equation 14:
IL(RMS) +2@Pout
3
Ǹ@Vac @h(eq. 14)
IL(RMS) +2@100
3
Ǹ@85 @0.92 +1.48 A
2. The output diode (D) rms current (ID(RMS)) is
calculated using Equation 15:
ID(RMS) +4
3@2
Ǹ@2
p
Ǹ@Pout
h@Vac @Vout
Ǹ(eq. 15)
ID(RMS) +4
3@2
Ǹ@2
p
Ǹ@100
0.92 @85 @400
Ǹ+0.75 A
The diode maximum voltage is equal to VOVP (421 V)
plus the overshoot caused by parasitic contributions. For this
evaluation board, the maximum voltage is 450 V. A 600 V
diode provides a 25% derating factor. The MUR460
(4 A/600 V) diode is selected for this design.
3. The MOSFET (M) rms current (IM(RMS)) is
calculated using Equation 16:
IM(RMS) +2
3
Ǹ@ǒPout
h@VacǓ@1*ǒ2
Ǹ@8@Vac
3@p@Vout Ǔ
Ǹ
(eq. 16)
IM(RMS) +2
3
Ǹ@ǒ100
0.92 @85Ǔ@1−ǒ2
Ǹ@8@85
3@p@400Ǔ
Ǹ
+1.27 A
The MOSFET maximum voltage is equal to VOVP
(421 V) plus the overshoot caused by parasitic
contributions. For this evaluation board, the maximum
voltage is 450 V. A 560 V MOSFET provides a 20% derating
factor. The SPP12N50C3 (11.6 A/560 V) MOSFET is
selected for this design.
4. The current sense resistor (Rsense) limits the
maximum inductor peak current of the MOSFET
and is calculated using Equation 17:
Rsense +VILIM
IL(peak)
(eq. 17)
Where VILIM is specified in the NCP1608 datasheet.

NCP1608BOOSTGEVB
http://onsemi.com
7
Rsense +0.5
3.62 +0.138 W
The current sense resistor is selected as 0.125 Wfor
decreased power dissipation. The resulting maximum
inductor peak current is 4 A. Since the MOSFET continuous
current rating is 7 A (for TC= 100°C as specified in the
manufacturer’s datasheet) and the inductor saturation
current is 4.7 A, the maximum peak inductor current of 4 A
is sufficiently low.
The power dissipated by Rsense is calculated using
Equation 18:
PRsense +IM(RMS) 2@Rsense (eq. 18)
PRsense +1.272@0.125 +0.202 W
5. The output capacitor (Cbulk) rms current is
calculated using Equation 19:
IC(RMS) +2
Ǹ@32 @Pout 2
9@p@Vac @Vout @h2*Iload(RMS) 2
Ǹ(eq. 19)
IC(RMS) +2
Ǹ@32 @1002
9@p@85 @400 @0.922*0.252
Ǹ+0.7 A
The value of Cbulk is calculated in Step 5 to ensure a ripple
voltage that is sufficiently low to not trigger OVP. The value
of Cbulk may need to be increased so that the rms current
does not exceed the ratings of Cbulk.
The voltage rating of Cbulk is required to be greater than
Vout(OVP). Since Vout(OVP) is 421 V, Cbulk is selected to have
a voltage rating of 450 V.
DESIGN STEP 7: Supply VCC Voltage
The typical method to charge the VCC capacitor (CVcc) to
VCC(on) is to connect a resistor between Vin and VCC. The
low startup current consumption of the NCP1608 enables
most of the resistor current to charge CVcc during startup.
The low startup current consumption enables faster startup
times and reduces standby power dissipation. The startup
time (tstartup) is approximated with Equation 20:
tstartup +
CVCC @VCC(on)
2
Ǹ@Vac
Rstart *ICC(startup)
(eq. 20)
Where ICC(startup) = 24 mA (typical).
If CVcc is selected as a 47 mF capacitor and Rstart is
selected as 660 kW, tstartup is equal to:
tstartup +47 m@12
2
Ǹ@85
660 k *24 m
+3.57 s
Once VCC reaches VCC(on), the internal references and
logic of the NCP1608 turn on. The NCP1608 includes an
undervoltage lockout (UVLO) feature that ensures that the
NCP1068 remains enabled unless VCC decreases to less than
VCC(off). This hysteresis ensures sufficient time for another
supply to power VCC.
The ZCD winding is a possible solution, but the voltage
induced on the winding may be less than the required
voltage. An alternative is to implement a charge pump to
supply VCC. A schematic is illustrated in Figure 7.
Figure 7. The ZCD Winding Supplies VCC using a
Charge Pump Circuit
+
1
4
3
2
8
5
6
7
GND
ZCD
NCP1608
+
Cin
Rstart
D1
R1
CVcc
RZCD
C3IAUX
DAUX
DRV
VCC
FB
Control
Ct
CS
C3 stores the energy for the charge pump. R1 limits the
current by reducing the rate of voltage change. DAUX supplies
current to C3 when its cathode is negative. When its cathode
is positive it limits the maximum voltage applied to VCC.
The voltage change across C3 over one period is
calculated using Equation 21:
DVC3 +Vout
N*VCC (eq. 21)
The current that charges CVcc is calculated using
Equation 22:
IAUX +C3 @fSW @DVC3 +C3 @fSW @ǒVout
N*VCCǓ
(eq. 22)
For off−line ac-dc applications that require PFC, a 2-stage
approach is typically used. The first stage is the CrM boost
PFC. This supplies the 2nd stage, which is traditionally an
isolated flyback or forward converter. This solution is
cost−effective and exhibits excellent performance. During
low output power conditions the PFC stage is not required
and reduces efficiency. Advanced controllers, such as the
NCP1230 and NCP1381 detect the low output power
condition and shut down the PFC stage by removing
PFC(VCC) (Figure 8).

NCP1608BOOSTGEVB
http://onsemi.com
8
Figure 8. Using the SMPS Controller to Supply Power to the NCP1608
1
7
6
5
2
3
4
NCP1608
++
+
+
1
7
6
5
2
3
4
NCP1230
PFC(VCC)
88
+
D
Cbulk
VCC +
−
DESIGN STEP 8: Limit the Inrush Current
The sudden application of the ac line voltage to the PFC
pre−converter causes an inrush current and a resonant
voltage overshoot that is several times the normal value.
Resizing the power components to handle inrush current and
a resonant voltage overshoot is cost prohibitive.
1. External Inrush Current Limiting Resistor
A NTC (negative temperature coefficient) thermistor
connected in series with the diode limits the inrush current
(Figure 9). The resistance of the NTC decreases from a few
ohms to a few milliohms as the NTC is heated by the I2R
power dissipation. However, an NTC resistor may not be
sufficient to protect the inductor and Cbulk from inrush
current during a brief interruption of the ac line voltage, such
as during ac line dropout and recovery.
2. Startup Bypass Rectifier
A rectifier is connected from Vin to Vout (Figure 10). This
bypasses the inductor and diverts the startup current directly
to Cbulk. Cbulk is charged to the peak ac line voltage without
resonant overshoot and without excessive inductor current.
After startup, Dbypass is reverse biased and does not interfere
with the boost converter.
Figure 9. Use a NTC to Limit the Inrush Current
Through the Inductor
NCP1608
+
Vac
NTC
Vin
Vout
Figure 10. Use a Second Diode to Route the
Inrush Current Away from the Inductor
NCP1608
+
Vac
Vin
Vout
Dbypass
DESIGN STEP 9: Develop the Compensation Network
The pre−converter is compensated to ensure stability over
the input voltage and output power range. To compensate the
loop, a compensation network is connected between the
Control and ground pins. To ensure high PF, the bandwidth
of the loop is set below 20 Hz. A type 2 compensation
network is selected for this design to increase the phase
margin. The type 2 compensation network is shown in
Figure 11.
Figure 11. Type 2 Compensation Network
FB
Control
+
−
E/A
+
gm
CCOMP RCOMP1
CCOMP1
Rout2
Rout1
VControl
Vout
RFB VREF
Compensation
Network

NCP1608BOOSTGEVB
http://onsemi.com
9
The type 2 network is composed of CCOMP , CCOMP1, and
RCOMP1. CCOMP1 sets the crossover frequency (fCROSS) and
is calculated using Equation 23:
CCOMP1 +gm
2@p@fCROSS
(eq. 23)
For this design, fCROSS is set to 5 Hz at the average input
voltage (175 Vac) to decrease THD and gm is specified in the
NCP1608 datasheet:
CCOMP1 +110 m
2@p@5+3.5 mF
A normalized value of 3.3 mF is selected, which sets
fCROSS to 5.3 Hz.
The addition of RCOMP1 causes a zero in the loop
response. The zero frequency (fzero) is typically set to half
the crossover frequency, which is 2.5 Hz for this case.
RCOMP1 is calculated using Equation 24:
RCOMP1 +1
2@p@fzero @CCOMP
(eq. 24)
RCOMP1 +1
2@p@2.5 @3.3 m+19.3 kW
RCOMP1 is selected as 20 kW.
CCOMP is used to filter high frequency noise and is set to
between 1/10 and 1/5 of CCOMP1. For this design, CCOMP is
selected to be 1/5 of CCOMP1.
CCOMP +ǒ1
5Ǔ@3.3 m+0.66 mF
CCOMP is selected as 0.68 mF.
The phase margin and crossover frequency change with
the ac line voltage. It is critical that the gain and phase are
measured for all operating conditions. The measurement
setup using a network analyzer is shown in Figure 12.
Ch A
High−Voltage
(> 450 V)
Isolation Probe
Ch B
High−Voltage
(> 450 V)
Isolation Probe
Figure 12. Gain-Phase Measurement Setup for a Boost PFC Pre−Converter
+
AC Line
EMI
Filter
GND
ZCD
+
Load
Vout
Ct
Isolator
Network Analyzer
L
NCP1608
D
MCbulk
Rsense
1 kW
VCC
Cin
RZCD
Rout1
Rout2
CCOMP
VCC
DRV
4
3
2
1
CS
Ct
Control
FB
5
6
7
8
There is a tradeoff of transient response for PF and THD.
The low bandwidth of the feedback loop reduces the Control
pin ripple voltage. The reduction of the Control pin ripple
voltage increases PF and reduces THD, but increases the
magnitude of overshoots and undershoots.
Additional THD Reduction
The constant on time architecture of the NCP1608
provides flexibility in optimizing each design.
The following design guidelines provide methods to
further improve PF and THD.
1. Improve the THD/PF at Maximum Output Power by
Increasing the On Time at the Zero Crossing:
One disadvantage of constant on time CrM control is that
at the zero crossing of the ac line, the instantaneous input
voltage is not large enough to store sufficient energy in the
inductor during the constant on time. Minimal energy is
processed and “zero crossing distortion” is produced as
shown in Figure 13.

NCP1608BOOSTGEVB
http://onsemi.com
10
Zero
Crossing
Distortion
Vout (10V/div, ac coupled)
Iin (500mA/div)
Vin (100V/div)
Figure 13. Full Load Input Current (Vin = 230 Vac 50 Hz, Iout = 250 mA)
The zero crossing distortion increases the THD and
decreases the PF of the pre-converter. To meet
IEC61000-3-2 requirements, this is generally not an issue as
the NCP1608 reduces input current distortion with sufficient
margin. If improved THD or PF is required, then zero
crossing distortion must be reduced. To reduce the zero
crossing distortion, the on time is increased as the
instantaneous input voltage is decreasing to zero. This
increases the time for the inductor current to build up and
reduces the instantaneous input voltage at which the
distortion begins.
This method is implemented by connecting a resistor from
Vin to Ct as shown in Figure 14. The resistor current (ICTUP)
is proportional to the instantaneous line voltage and is
summed with Icharge to increase the charging current of Ct.
ICTUP is maximum at the peak of Vin and is approximately
zero at the zero crossing.
Figure 14. .Add RCTUP to Modulate the On Time and Reduce Zero Crossing Distortion
+
AC Line
Ct +
−
PWM
Ct
L
ton
Ct(offset)
VControl
VDD
Icharge
DRV
Vin
Cin RCTUP
ICTUP +Vin
RCTUP
The increased charging current at the peak of Vin enables
the increased sizing of the Ct capacitor without reducing the
control range at VacHL or low output power. The larger value
of the Ct capacitor increases the on time near the zero
crossing and reduces the zero crossing distortion as shown
in Figure 15. This reduces the frequency variation over the
ac line cycle. The tradeoff is that the standby power
dissipation is increased by RCTUP
. The designer must
balance the desired THD and PF performance with the
standby power dissipation requirements.