ON Semiconductor NCP1060 User manual

©Semiconductor Components Industries, LLC, 2017
September, 2017 − Rev. 6 1Publication Order Number:
NCP1060/D
NCP1060, NCV1060,
NCP1063, NCV1063
High-Voltage Switcher for
Low Power Offline SMPS
The NCP106X products integrate a fixed frequency current mode
controller with a 700 V MOSFET. Available in a PDIP−7, SOIC−10 or
SOIC−16 package, the NCP106X offer a high level of integration,
including soft−start, frequency−jittering, short−circuit protection,
skip−cycle, adjustable peak current set point, ramp compensation, and a
Dynamic Self−Supply (eliminating the need for an auxiliary winding).
Unlike other monolithic solutions, the NCP106X is quiet by nature:
during nominal load operation, the part switches at one of the available
frequencies (60 kHz or 100 kHz). When the output power demand
diminishes, the IC automatically enters frequency foldback mode and
provides excellent efficiency at light loads. When the power demand
reduces further, it enters into a skip mode to reduce the standby
consumption down to a no load condition.
Protection features include: a timer to detect an overload or a
short−circuit event, Overvoltage Protection with auto−recovery and
AC input line voltage detection (A version).
The ON proprietary integrated Over Power Protection (OPP) lets
you harness the maximum delivered power without affecting your
standby performance simply via external resistors.
For improved standby performance, the connection of an auxiliary
winding stops the DSS operation and helps to reduce input power
consumption below 50 mW at high line.
NCP106x can be seamlessly used both in non−isolated and in
isolated topologies.
Features
•Built−in 700 V MOSFET with RDS(on) of 34 W(NCP1060) and
11.4 W(NCP1063)
•Large Creepage Distance Between High−voltage Pins
•Current−Mode Fixed Frequency Operation – 60 kHz or 100 kHz
(130 kHz on demand)
•Adjustable Peak Current: see below table
•Fixed Ramp Compensation
•Direct Feedback Connection for Non−isolated Converter
•Internal and Adjustable Over Power Protection (OPP)
Circuit
•Skip−Cycle Operation at Low Peak Currents Only
•Dynamic Self−Supply: No Need for an Auxiliary
Winding
•Internal 4 ms Soft−Start
•Auto−Recovery Output Short Circuit Protection with
Timer−Based Detection
•Auto−Recovery Overvoltage Protection with Auxiliary
Winding Operation
•Frequency Jittering for Better EMI Signature
•No Load Input Consumption < 50 mW
•Frequency Foldback to Improve Efficiency at Light
Load
•NCV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change
Requirements; AEC−Q100 Qualified and PPAP
Capable
•These Devices are Pb−Free and are RoHS Compliant
Typical Applications
•Auxiliary / Standby Isolated and Non−isolated Power
Supplies
•Power Meter SMPS
•Wide Vin Low Power Industrial SMPS
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PDIP−7
CASE 626A
AP SUFFIX
1
8
MARKING DIAGRAMS
See detailed ordering and shipping information in the package
dimensions section on page 28 of this data sheet.
ORDERING INFORMATION
SOIC−10
CASE 751BQ
AD or BD SUFFIX
SOIC−16
CASE 751B−05
D SUFFIX
1
10
x = Power Switch Circuit On−state Resistance
x = (0 = 34 W, 3 = 11.4 W)
f = Brown In (A = Yes, B = No)
yyy = Oscillator Frequency
yyy = (060 = 60 kHz, 100 = 100 kHz)
z = P (standard) or V (automotive)
u = blank (standard) or V (automotive)
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G= Pb−Free Package
P106xfyyy
AWL
YYWWG
u1060fyyy
ALYWX
G
1
10
NCz1063fyyyG
AWLYWW
1
16
1
16
1
7

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PRODUCT INFORMATION & INDICATIVE MAXIMUM OUTPUT POWER
Product RDS(on) IIPK(0)
230 Vac +15% 85 − 265 Vac
Adapter Open Frame Adapter Open Frame
NCP1060 60 kHz 34 W300 mA 3.3 W 8.3 W 1.9 W 4.7 W
NCP1063 100 kHz 11.4 W780 mA 6.2 W 15.5 W 3.3 W 7.8 W
NOTE: Informative values only, with Tamb = 25°C, Tcase = 100°C, PDIP−7 package, Self supply via Auxiliary winding and circuit mounted
on minimum copper area as recommended.
PDIP−7
DRAIN
DRAIN
COMP
GND
VCC
LIM/OPP
FB
SOIC−16
DRAIN
DRAIN
DRAIN
DRAIN
N.C.
N.C.
N.C.
N.C.
GND
GND
GND
GND
VCC
LIM/OPP
FB
COMP
SOIC−10
DRAIN
DRAIN
DRAIN
DRAIN
GND
VCC
LIM/OPP
FB
COMP DRAIN
Figure 1. Pin Connections
Table 1. PIN FUNCTION DESCRIPTION
Pin No
Pin Name Function Pin Description
PDIP 7 SOIC 10 SOIC 16
1 1 1−4 GND The IC Ground
2 2 5 VCC Powers the internal
circuitry This pin is connected to an external capacitor. The VDD
includes an auto−recovery over voltage protection.
3 3 6 LIM/OPP Ipeak set / Over
power limitation The current drown from the pin decreases Ipeak of the primary winding. If resistive divider from the auxiliary
winding is connected to this pin it sets the OPP compen-
sation level (it diminishes the peak current.)
4 4 7 FB Feedback signal
input This is the inverting input of the trans conductance error amplifier. It is normally connected to the switching power
supply output through a resistor divider.
5 5 8 Comp Compensation The error amplifier output is available on this pin. The
network connected between this pin and ground adjusts
the regulation loop bandwidth. Also, by connecting an
opto−coupler to this pin, the peak current set point is
adjusted accordingly to the output power demand.
69−12 This un−connected pin ensures adequate creepage dis-
tance
7,8 6−10 13−16 Drain Drain connection The internal drain MOSFET connection

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Table 2. TYPICAL APPLICATIONS
•If the output voltage is
above 9.0 V typ. between
VCC(ON) level and VOVP
level − VCC supplied from
output via D2
•R2 limits maximal output
power
•Direct feedback, resistive
divider formed by R3, R4
sets output voltage
•VCC supplied from DSS
•Output voltage is below 9.0
V typ.
•LIM/OPP pin floating − no
limit output power
•Optocoupler feedback
Typical Non−isolated Application – Buck Converter
•If the output voltage is
above 9.0 V typ. between
VCC(ON) level and VOVP
level − VCC supplied from
output via D2
•R2 limits maximal output
power
•Direct feedback, resistive
divider formed by R3, R4
sets output voltage
•·VCC supplied from DSS
•·Output voltage is below
9.0 V typ.
•·LIM/OPP pin floating −
no limit output power
•·Direct feedback, resistive
divider formed by R2, R3
sets output voltage
Typical Non−isolated Application – Buck−Boost Converter

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Table 2. TYPICAL APPLICATIONS
•VCC supplied from DSS
•Output voltage is below 9.0
V typ.
•LIM/OPP pin floating − no
limit output power
•Resistive divider formed
by R2, R3 sets output volt-
age
•If the output voltage is
above 9.0 V typ. between
VCC(ON) level and VOVP
level − VCC supplied from
output via D4
•LIM/OPP pin floating − no
limit output power
•Resistive divider formed
by R2, R3 sets output volt-
age
Typical Non−isolated Application – Flyback Converter
•VCC supplied from auxil-
iary winding
•Resistive divider formed
by R2, R3 sets output pow-
er limit and over power
protection
•Optocoupler feedback, re-
sistive divider formed by
R6, R7 sets output voltage
Typical Isolated Application – Flyback Converter

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LIM/OPP
FB
COMP
GND
DRAIN
VCC
S
R
Q
VCC
Management Reset
UVLO
Vdd
tSCP Ipflag
SCP
trecovery
80−
ms Filter
Line
Detection
OFF UVLO
S
R
Q
RCOMP(up)
UVLO
TSD
LEB
Soft−Start
Reset
Reset SS as recoving from
SCP, TSD,VCC OVP or UVLO
ICOMP to CS setpoint
IFreeze Ipk(0)
VCC
OSC Sawtooth
Foldback
LineOK
LineOK
Sawtooth
Ipflag
Ramp
compensation
OFF
VCC OVP
SKIP=”1” èShut down some
blocks to reduce consumption
SKIP
ILMOP
VLMOP
ILMDEC
ILMDEC
ILMOP
0
IPKL
IFB
VCOMP(REF)
ICOMPskip
ICOMPfault
ILMOP (min) ILMOP (max )
Jittering
VOVP
FB/COMP
Processing
Figure 2. Simplified Internal Circuit Architecture

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Table 3. MAXIMUM RATING TABLE (All voltages related to GND terminal)
Rating Symbol Value Unit
Power supply voltage, VCC pin, continuous voltage VCC −0.3 to 20 V
Voltage on all pins, except Drain and VCC pin Vinmax −0.3 to 10 V
Drain voltage BVdss −0.3 to 700 V
Maximum Current into VCC pin ICC 10 mA
Drain Current Peak during Transformer Saturation (TJ= 150°C, Note 2):
NCP1060
NCP1063
Drain Current Peak during Transformer Saturation (TJ= 125°C, Note 2):
NCP1060
NCP1063
Drain Current Peak during Transformer Saturation (TJ= 25°C, Note 2):
NCP1060
NCP1063
IDS(PK) 300
850
335
950
520
1500
mA
Thermal Resistance Junction−to−Air – PDIP7 with 200 mm@of 35−mcopper area RθJA 115 °C/W
Thermal Resistance Junction−to−Air – SOIC10 with 200 mm@of 35−mcopper area RθJA 132 °C/W
Thermal Resistance Junction−to−Air – SOIC16 with 200 mm@of 35−mcopper area RθJA 104 °C/W
Junction Temperature Range TJ−40 to +150 °C
Storage Temperature Range Tstg −60 to +150 °C
Human Body Model ESD Capability (All pins except HV pin) per JEDEC JESD22−A114F HBM 2 kV
Charged−Device Model ESD Capability per JEDEC JESD22−C101E CDM 1 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
2. Maximum drain current IDS(PK) is obtained when the transformer saturates. It should not be mixed with short pulses that can be seen at turn
on. Figure 3 below provides spike limits the device can tolerate.
Figure 3. Spike Limits

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Table 4. ELECTRICAL CHARACTERISTICS
(For typical values TJ= 25°C, for min/max values TJ= −40°C to +125°C, VCC = 14 V unless otherwise noted)
Symbol Rating Pin Min Typ Max Unit
SUPPLY SECTION AND VCC MANAGEMENT
VCC(on) VCC increasing level at which the switcher starts operation 2 (5) 8.4 9.0 9.5 V
VCC(min) VCC decreasing level at which the HV current source restarts 2 (5) 7.0 7.5 7.8 V
VCC(off) VCC decreasing level at which the switcher stops operation (UVLO) 2 (5) 6.7 7.0 7.2 V
ICC1 Internal IC consumption, NCP1060 switching at 60 kHz, LIM/OPP = 0 A
Internal IC consumption, NCP1060 switching at 100 kHz, LIM/OPP = 0 A
Internal IC consumption, NCP1063 switching at 60 kHz, LIM/OPP = 0 A
Internal IC consumption, NCP1063 switching at 100 kHz, LIM/OPP = 0 A
2 (5) −
−
−
−
0.92
0.97
0.99
1.07
−
−
−
−
mA
ICCskip Internal IC consumption, COMP is 0 V (No switching on MOSFET) 2 (5) − 340 − mA
POWER SWITCH CIRCUIT
RDS(on) Power Switch Circuit on−state resistance
NCP1060 (Id = 50 mA)
Tj = 25°C
Tj = 125°C
NCP1063 (Id = 50 mA)
Tj = 25°C
Tj = 125°C
7, 8
(6−10)
(13−16) −
−
−
−
34
65
11.4
22
41
72
14.0
24
W
BVDSS Power Switch Circuit & Startup breakdown voltage
(ID(off) = 120 mA, Tj = 25°C) 7, 8
(6−10)
(13−16)
700 − − V
IDSS(off) Power Switch & Startup breakdown voltage off−state leakage current
Tj = 125°C (Vds = 700 V) 7, 8 (6−10)
(13−16)
− 84 − mA
tr
tf
Switching characteristics (RL= 50 W, VDS set for Idrain = 0.7 x Ilim)
Turn−on time (90% − 10%)
Turn−off time (10% − 90%)
7, 8
(6−10)
(13−16) −
−20 10 − −
ns
ton(min) Minimum on time
NCP1060
NCP1063
7, 8
(6−10)
(13−16) −
−200 230 − −
ns
INTERNAL START−UP CURRENT SOURCE
Istart1 High−voltage current source, VCC = VCC(on) – 200 mV 7, 8
(6−10)
(13−16)
5 8 12 mA
Istart2 High−voltage current source, VCC = 0 V 7, 8
(6−10)
(13−16)
− 0.5 − mA
VCCTH VCC Transient level for Istart1 to Istart2 toggling point 2 (5) − 1.4 − V
Vstart(min) Minimum startup voltage, VCC = 0 V 7, 8
(6−10)
(13−16)
21 V
CURRENT COMPARATOR
IIPK Maximum internal current setpoint at 50% duty cycle
FB = 2 V, LIM/OPP = 0 mA, Tj = 25°C
NCP1060
NCP1063 −
−− −250 650 − −
mA
IIPK(0) Maximum internal current setpoint at beginning of switching cycle
FB = 2 V, LIM/OPP pin open Tj = 25°C
NCP1060
NCP1063 −
−268 702 300 780 332 858
mA
3. The final switch current is: IIPK(0) / (Vin/LP+ Sa) x Vin/LP+ Vin/LPx tprop, with Sathe built−in slope compensation, Vin the input voltage,
LPthe primary inductor in a flyback, and tprop the propagation delay.
4. Oscillator frequency is measured with disabled jittering.

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Table 4. ELECTRICAL CHARACTERISTICS
(For typical values TJ= 25°C, for min/max values TJ= −40°C to +125°C, VCC = 14 V unless otherwise noted)
Symbol UnitMaxTypMinPinRating
CURRENT COMPARATOR
IIPKSW Final switch current with a primary slope of 200 mA/ms,
FSW = 60 kHz (Note 3), LIM/OPP pin open
NCP1060
NCP1063 −
−− −330 740 − −
mA
IIPKSW Final switch current with a primary slope of 200 mA/ms,
FSW = 100 kHz (Note 3), LIM/OPP pin open
NCP1060
NCP1063 −
−− −320 710 − −
mA
ILMDEC Maximum internal current setpoint at beginning of switching cycle
FB = 2 V, LIM/OPP = −285 mA, Tj = 25°C
NCP1060
NCP1063 −
−− −128 312 − −
mA
tSS Soft−start duration (guaranteed by design) − − 4 − ms
tprop Propagation delay from current detection to drain OFF state − − 70 − ns
tLEB Leading Edge Blanking Duration
NCP1060
NCP1063 −
−− −130 160 − −
ns
INTERNAL OSCILLATOR
fOSC Oscillation frequency, 60 kHz version, Tj = 25°C (Note 4) − 54 60 66 kHz
fOSC Oscillation frequency, 100 kHz version, Tj = 25°C (Note 4) − 90 100 110 kHz
fjitter Frequency jittering in percentage of fOSC − − ±6 − %
fswing Jittering swing frequency − − 300 − Hz
Dmax Maximum duty−cycle − 62 66 72 %
ERROR AMPLIFIER SECTION
VREF Voltage Feedback Input (VCOMP = 2.5 V) 4 (7) 3.2 3.3 3.4 V
IFB Input Bias Current (VFB = 3.3 V) 4 (7) − 1 − mA
GMTransconductance 5 (8) 2 mS
IOTAlim OTA maximum current capability (VFB > VOTAen)5 (8) ±150 mA
VOTAen FB voltage to disable OTA 4 (7) 0.7 1.3 1.7 V
COMPENSATION SECTION
ICOMPfault COMP current for which Fault is detected 5 (8) −−40 −mA
ICOMP100% COMP current for which internal current set−point is 100% (IIPK(0))5 (8) −−44 −mA
ICOMPfreeze COMP current for which internal current setpoint is:
IFreeze1 or 2(NCP1060/3) 5 (8) −−80 −mA
VCOMP(REF) Equivalent pull−up voltage in linear regulation range
(Guaranteed by design) 5 (8) − 2.7 − V
RCOMP(up) Equivalent feedback resistor in linear regulation range
(Guaranteed by design) 5 (8) − 17.7 − kΩ
VLMOP Voltage on LIM/OPP pin @ ILMOP = −35 mA
Voltage on LIM/OPP pin @ ILMOP = −250 mA, Tj = 25°C3 (6) 1.40
1.28 1.50 1.35 1.60 1.42 V
ILMOP Maximum current from LIM/OPP pin 3 (6) −330 −420 mA
ILMOP(min) Current at which LIM/OPP starts to decrease IPEAK 3 (6) −20 −26 −32 mA
ILMOP(max) Current at which LIM/OPP stops to decrease IPEAK 3 (6) −285 mA
ILMOP(neg) Negative Active Clamp Voltage (ILMOP = −2.5 mA) 3 (6) −0.7 V
3. The final switch current is: IIPK(0) / (Vin/LP+ Sa) x Vin/LP+ Vin/LPx tprop, with Sathe built−in slope compensation, Vin the input voltage,
LPthe primary inductor in a flyback, and tprop the propagation delay.
4. Oscillator frequency is measured with disabled jittering.

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Table 4. ELECTRICAL CHARACTERISTICS
(For typical values TJ= 25°C, for min/max values TJ= −40°C to +125°C, VCC = 14 V unless otherwise noted)
Symbol UnitMaxTypMinPinRating
COMPENSATION SECTION
ILMOP(pos) Positive Active Clamp (Guaranteed by design) 3 (6) 2.5 mA
FREQUENCY FOLDBACK & SKIP
ICOMPfold Start of frequency foldback COMP pin current level 5 (8) −−68 −mA
ICOMPfold(end) End of frequency foldback COMP pin current level, fsw = fmin 5 (8) −−100 −mA
fmin The frequency below which skip−cycle occurs − 21 25 29 kHz
ICOMPskip The COMP pin current level to enter skip mode 5 (8) −−120 −mA
IFreeze1 Internal minimum current setpoint (ICOMP = ICOMPFreeze) in NCP1060 −110 − mA
IFreeze2 Internal minimum current setpoint (ICOMP = ICOMPFreeze) in NCP1063 − 270 − mA
RAMP COMPENSATION
Sa(60) The internal ramp compensation @ 60 kHz:
NCP1060
NCP1063 −
−− −8.4 15.6 − −
mA/ms
Sa(100) The internal ramp compensation @ 100 kHz:
NCP1060
NCP1063 −
−− −14 26 − −
mA/ms
PROTECTIONS
tSCP Fault validation further to error flag assertion − 35 48 − ms
trecovery OFF phase in fault mode − − 400 − ms
VOVP VCC voltage at which the switcher stops pulsing 2 (5) 17.0 18.0 18.8 V
tOVP The filter of VCC OVP comparator − − 80 − ms
VHV(EN) The drain pin voltage above which allows MOSFET operate, which is
detected after TSD, UVLO, SCP, or VCC OVP mode. (A version only) 7,8 (6−10)
(13−16)
67 87 110 V
TEMPERATURE MANAGEMENT
TSD Temperature shutdown (Guaranteed by design) − 150 163 − °C
TSDhyst Hysteresis in shutdown (Guaranteed by design) − − 20 − °C
3. The final switch current is: IIPK(0) / (Vin/LP+ Sa) x Vin/LP+ Vin/LPx tprop, with Sathe built−in slope compensation, Vin the input voltage,
LPthe primary inductor in a flyback, and tprop the propagation delay.
4. Oscillator frequency is measured with disabled jittering.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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TYPICAL CHARACTERISTICS
Figure 4. VCC(on) vs. Temperature Figure 5. VCC(min) vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
8.85
8.90
8.95
9.00
9.05
9.10
9.15
100806040200−20−40
7.32
7.34
7.38
7.42
7.46
7.48
7.52
Figure 6. VCC(off) vs. Temperature Figure 7. IDSS(off) vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
6.88
6.90
6.92
6.94
6.96
6.98
7.00
100806040200−20−40
0
100
200
300
400
600
700
800
Figure 8. ICC1 60 kHz vs. Temperature Figure 9. ICC1 100 kHz vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
100806040200−20−40
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
VOLTAGE (V) VOLTAGE (V)
VOLTAGE (V)
CURRENT (mA)
CURRENT (mA) CURRENT (mA)
120 120
120
7.36
7.40
7.44
7.50
120
500
120 120

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TYPICAL CHARACTERISTICS
Figure 10. IIPK(0)1060 vs. Temperature Figure 11. IIPK(0)1063 vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
288
292
294
296
300
304
306
310
100806040200−20−40
720
725
735
740
750
755
765
770
Figure 12. Istart1 vs. Temperature Figure 13. Istart2 vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
0
2
4
8
10
12
100806040200−20−40
0
0.1
0.2
0.3
0.4
0.5
0.6
Figure 14. RDS(on)1060 vs. Temperature Figure 15. RDS(on)1063 vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
0
10
20
30
40
50
60
70
100806040200−20−40
0
5
10
15
20
25
CURRENT (mA) CURRENT (mA)
CURRENT (mA) CURRENT (mA)
RESISTIVITY (W) RESISTIVITY (W)
120
290
298
302
308
120
730
745
760
120
6
120
120120

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TYPICAL CHARACTERISTICS
Figure 16. fOSC60 vs. Temperature Figure 17. fOSC100 vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
55.5
56.0
57.0
57.5
58.0
58.5
59.5
60.0
100806040200−20−40
92
93
94
95
96
98
99
100
Figure 18. Ifreeze1060 vs. Temperature Figure 19. Ifreeze1063 vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
100
101
103
104
105
106
108
109
100806040200−20−40
256
258
262
264
266
268
272
274
Figure 20. D(max) vs. Temperature Figure 21. fmin vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
65.6
65.7
65.8
65.9
66.0
66.1
66.2
100806040200−20−40
24.4
24.6
24.8
25.0
25.2
25.4
25.6
25.8
FREQUENCY (kHz) FREQUENCY (kHz)
CURRENT (mA) CURRENT (mA)
DUTY CYCLE (%)
FREQUENCY (kHz)
120
56.5
59.0
120
97
120
102
107
120
260
270
120 120

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TYPICAL CHARACTERISTICS
Figure 22. trecovery vs. Temperature Figure 23. tSCP vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
385
390
400
405
410
415
425
430
100806040200−20−40
46
47
48
49
50
51
52
53
Figure 24. VOVP vs. Temperature Figure 25. VHV(EN) vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
17.4
17.5
17.6
17.8
17.9
18.0
18.1
18.2
100806040200−20−40
84
85
86
87
88
90
91
92
Figure 26. VREF vs. Temperature Figure 27. VOTAen vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
3.24
3.26
3.27
3.28
3.30
3.31
3.33
3.34
100806040200−20−40
0
0.2
0.4
0.6
0.8
1.2
1.4
1.6
TIME (ms) TIME (ms)
VOLTAGE (V) VOLTAGE (V)
VOLTAGE (V) VOLTAGE (V)
120
395
420
120
120
89
120
17.7
120
3.25
3.29
3.32
120
1.0

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TYPICAL CHARACTERISTICS
Figure 28. Drain Current Peak during Transformer
Saturation vs. Junction Temperature
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
0
1.0
1.5
2.5
IDS(PK) (A)
150
0.5
2.0 NCP1063
NCP1060
Figure 29. Breakdown Voltage vs. Temperature
TEMPERATURE (°C)
1007550250−25−50
0.925
0.95
0.975
1.025
1.05
1.075
BVDSS/BVDSS (25°C)(−)
125
1.0

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Application Information
Introduction
The NCP106X offers a complete current−mode control
solution. The component integrates everything needed to
build a rugged and cost effective Switch−Mode Power
Supply (SMPS) featuring low standby power. The Quick
Selection Table, Table 5, details the differences between
references, mainly peak current setpoints, RDS(on) value and
operating frequency.
•Current−mode operation: the controller uses
current−mode control architecture.
•700 V –_ Power MOSFET: Due to ON Semiconductor
Very High Voltage Integrated Circuit technology, the
circuit hosts a high−voltage power MOSFET featuring
a 34 Wor 11.4 WRDS(on) – Tj = 25°C. This value lets
the designer build a power supply up to 7.8 W or
15.5 W operated on universal mains. An internal
current source delivers the startup current, necessary to
crank the power supply.
•Dynamic Self−Supply: Due to the internal high
voltage current source, this device could be used in the
application without the auxiliary winding to provide
supply voltage.
•Short circuit protection: by permanently monitoring
the COMP line activity, the IC is able to detect the
presence of a short−circuit, immediately reducing the
output power for a total system protection. A tSCP timer
is started as soon as the COMP current is below
threshold, ICOMPfault, which indicates the maximum
peak current. If at the end of this timer the fault is still
present, then the device enters a safe, auto−recovery
burst mode, affected by a fixed timer recurrence,
trecovery. Once the short has disappeared, the controller
resumes and goes back to normal operation.
•Built−in VCC Over Voltage Protection: when the
auxiliary winding is used to bias the VCC pin (no DSS),
an internal comparator is connected to VCC pin. In case
the voltage on the pin exceeds a level of VOVP (18 V
typically), the controller immediately stops switching
and waits a full timer period (trecovery) before
attempting to restart. If the fault is gone, the controller
resumes operation. If the fault is still there, e.g. a
broken opto−coupler, the controller protects the load
through a safe burst mode.
•Line detection: An internal comparator monitors the
drain voltage as recovering from one of the following
situations:
♦Short Circuit Protection,
♦VCC OVP is confirmed,
♦UVLO,
♦TSD
•If the drain voltage is lower than the internal threshold
(VHV(EN)), the internal power switch is inhibited. This
avoids operating at too low ac input. This is also called
brown−in function in some fields. For applications not
using standard AC mains (24 Vdc industrial bus for
instance), the B version doesn’t incorporate this line
detection and let the device start as soon as voltage
supply reaches Vstart(min).
•Frequency jittering: an internal low−frequency
modulation signal varies the pace at which the
oscillator frequency is modulated. This helps spreading
out energy in conducted noise analysis. To improve the
EMI signature at low power levels, the jittering remains
active in frequency foldback mode.
•Soft−Start: a 4 ms soft−start ensures a smooth startup
sequence, reducing output overshoots.
•Frequency foldback capability: a continuous flow of
pulses is not compatible with no−load/light−load
standby power requirements. To excel in this domain,
the controller observes the COMP pin current
information and when it reaches a level of ICOMPfold,
the oscillator then starts to reduce its switching
frequency as the feedback current continues to increase
(the power demand continues to reduce). It can go
down to 25 kHz (typical) reached for a feedback level
of ICOMPfold(end) (100 mA roughly). At this point, if the
power continues to drop, the controller enters classical
skip−cycle mode.
•Skip: if SMPS naturally exhibits a good efficiency at
nominal load, it begins to be less efficient when the
output power demand diminishes. By skipping
un−needed switching cycles, the NCP106X drastically
reduces the power wasted during light load conditions.
•Ipeak set: If current in range 26 mA and 285 mA is
drawn from the pin, the peak current is proportionally
reduced down to 40% of its original value. This feature
enables to designer to set up the peak current to the
value which is ideal for the application.
By routing a portion of the negative voltage present during
the on−time on the auxiliary winding to the LIM/OPP pin,
the user has a simple and non−dissipative means to alter the
maximum peak current setpoint as the bulk voltage
increases.

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Application Information
Startup Sequence
When the power supply is first powered from the mains
outlet, the internal current source (typically 8.0 mA) is
biased and charges up the VCC capacitor from the drain pin.
Once the voltage on this VCC capacitor reaches the VCC(on)
level (typically 9.0 V), the current source turns off and
pulses are delivered by the output stage: the circuit is awake
and activates the power MOSFET if the bulk voltage is
above VHV(EN) level (87 V typically) for A version and if
bulk voltage is above Vstart(min) (21 V dc) for B version.
Figure 30 details the simplified internal circuitry.
+−
VCC(on)
VCC(min)
Istart1
Vbulk
5
8
1
CVCC
Rlimit
I1
ICC1
I2
VCC> 18V ?
à
OVP fault
Drain
+−
VOVP
Figure 30. The Internal Arrangement of the Start−up Circuitry
Being loaded by the circuit consumption, the voltage on
the VCC capacitor goes down. When VCC is below VCC(min)
level (7.5 V typically), it activates the internal current source
to bring VCC toward VCC(on) level and stops again: a cycle
takes place whose low frequency depends on the VCC
capacitor and the IC consumption. A 1.5 V ripple takes place
on the VCC pin whose average value equals (VCC(on) +
VCC(min))/2. Figure 31 portrays a typical operation of the
DSS.

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0
1
2
3
4
5
6
7
8
9
10
012345678910
VCC
9.0 V
VCCTH
Startup Duration
Figure 31. The Charge/Discharge Cycle Over a 1 mF VCC Capacitor
Device
Internal
Pulses
7.5 V
TIME (ms)
V (V)
As one can see, even if there is auxiliary winding to provide
energy for VCC, it happens that the device is still biased by
DSS during start−up time or some fault mode when the
voltage on auxiliary winding is not ready yet. The VCC
capacitor shall be dimensioned to avoid VCC crosses VCC(off)
level, which stops operation. The ΔV between VCC(min) and
VCC(off) is 0.5 V. There is no current source to charge VCC
capacitor when driver is on, i.e. drain voltage is close to zero.
Hence the VCC capacitor can be calculated using
CVCC wICC1 @Dmax
fOSC @DV(eq. 1)
Take the 60 kHz device as an example. CVCC should be
above
0.8 m @72%
54 kHz @0.5 +21 nF.
A margin that covers the temperature drift and the voltage
drop due to switching inside FET should be considered, and
thus a capacitor above 0.1 mF is appropriate.
The VCC capacitor has only a supply role and its value
does not impact other parameters such as fault duration or
the frequency sweep period for instance. As one can see on
Figure 30, an internal OVP comparator, protects the
switcher against lethal VCC runaways. This situation can
occur if the feedback loop optocoupler fails, for instance,
and you would like to protect the converter against an over
voltage event. In that case, the over voltage protection
(OVP) circuit and immediately stops the output pulses for
trecovery duration (400 ms typically). Then a new start−up
attempt takes place to check whether the fault has
disappeared or not. The OVP paragraph gives more design
details on this particular section.
Fault Condition – Short−circuit on VCC
In some fault situations, a short−circuit can purposely
occur between VCC and GND. In high line conditions (VHV
= 370 VDC) the current delivered by the startup device will
seriously increase the junction temperature. For instance,
since Istart1 equals 5 mA (the min corresponds to the highest
Tj), the device would dissipate 370 x 5 m = 1.85 W. To avoid
this situation, the controller includes a novel circuitry made
of two startup levels, Istart1 and Istart2. At power−up, as long
as VCC is below a 1.4 V level, the source delivers Istart2
(around 500 mA typical), then, when VCC reaches 1.4 V, the
source smoothly transitions to Istart1 and delivers its nominal
value. As a result, in case of short−circuit between VCC and
GND, the power dissipation will drop to 370 x 500 m=
185 mW. Figure 31 portrays this particular behavior.
The first startup period is calculated by the formula C x V
= I x t, which implies a 1 mx 1.4 / 500 m= 2.8 ms startup time
for the first sequence. The second sequence is obtained by
toggling the source to 8 mA with a delta V of VCC(on) –
VCCTH = 9.0 – 1.4 = 7.6 V, which finally leads to a second
startup time of 1 mx 7.6 / 8 m = 0.95 ms. The total startup
time becomes 2.8 m + 0.95 m = 3.75 ms. Please note that this
calculation is approximated by the presence of the knee in
the vicinity of the transition.

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Fault Condition – Output Short−circuit
As soon as VCC reaches VCC(on), drive pulses are
internally enabled. If everything is correct, the auxiliary
winding increases the voltage on the VCC pin as the output
voltage rises. During the start−sequence, the controller
smoothly ramps up the peak drain current to maximum
setting, i.e. IIPK, which is reached after a typical period of
4 ms. When the output voltage is not regulated, the current
coming through COMP pin is below ICOMPfault level (40 mA
typically), which is not only during the startup period but
also anytime an overload occurs, an internal error flag is
asserted, Ipflag, indicating that the system has reached its
maximum current limit set point. The assertion of this flag
triggers a fault counter tSCP (48 ms typically). If at counter
completion, Ipflag remains asserted, all driving pulses are
stopped and the part stays off in trecovery duration (about
400 ms). A new attempt to re−start occurs and will last
48 ms providing the fault is still present. If the fault still
affects the output, a safe burst mode is entered, affected by
a low duty−cycle operation (11%). When the fault
disappears, the power supply quickly resumes operation.
Figure 32 depicts this particular mode:
Figure 32. In case of short−circuit or overload, the NCP106X protects itself and the power supply via a low
frequency burst mode. The VCC is maintained by the current source and self−supplies the controller.
IpFlag
Timer
DRV
internal
48 ms typ.
400 ms typ.
Fault
Open loop FB
VCC(on)
VCC(min)
VCC
VCOMP
Auto−recovery Over Voltage Protection
The particular NCP106X arrangement offers a simple
way to prevent output voltage runaway when the
optocoupler fails. As Figure 33 shows, a comparator
monitors the VCC pin. If the auxiliary pushes too much
voltage into the CVCC capacitor, then the controller
considers an OVP situation and stops the internal drivers.
When an OVP occurs, all switching pulses are permanently
disabled. After trecovery delay, it resumes the internal drivers.
If the failure symptom still exists, e.g. feedback
opto−coupler fails, the device keeps the auto−recovery OVP
mode. It is recommended insertion of a resistor (Rlimit)
between the auxiliary dc level and the VCC pin to protect the
IC against high voltage spikes, which can damage the IC,
and to filter out the Vcc line to avoid undesired OVP
activation. Rlimit should be carefully selected to avoid
triggering the OVP as we discussed, but also to avoid
disturbing the VCC in low / light load conditions.
Self−supplying controllers in extremely low standby
applications often puzzles the designer. Actually, if a SMPS
operated at nominal load can deliver an auxiliary voltage of
an arbitrary 16 V (Vnom), this voltage can drop below 10 V
(Vstby) when entering standby. This is because the
recurrence of the switching pulses expands so much that the
low frequency re−fueling rate of the VCC capacitor is not
enough to keep a proper auxiliary voltage.

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VOVP GND
VCC
Drain
Shut down
Internal DRV
80 ms
filter
VCC (on ) =9.0V
VCC(min ) =7.5V Istart 1
Rlimit D1
CVCC CAUX NAUX
Figure 33. A more detailed view of the NCP106X offers better insight on how to properly wire an auxiliary winding
VCC
ICOMP
TIMER
DRV
internal
VCC(min)
VCC(on)
VOVP
Fault level
48 ms typ.
400 ms typ.
Figure 34. describes the main signal variations when the part operates in auto−recovery OVP:
Soft−start
The NCP106X features a 4 ms soft−start which reduces
the power−on stress but also contributes to lower the output
overshoot. Figure 35 shows a typical operating waveform.
The NCP106X features a novel patented structure which
offers a better soft−start ramp, almost ignoring the start−up
pedestal inherent to traditional current−mode supplies.

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Drain current
VCC VCCON
Max Ip
4ms
0V (fresh PON)
Figure 35. The 4 ms Soft−start Sequence
Jittering
Frequency jittering is a method used to soften the EMI
signature by spreading the energy in the vicinity of the main
switching component. The NCP106X offers a ±6%
deviation of the nominal switching frequency. The sweep
sawtooth is internally generated and modulates the clock up
and down with a fixed frequency of 300 Hz. Figure 36 shows
the relationship between the jitter ramp and the frequency
deviation. It is not possible to externally disable the jitter.
60 kHz
63.6 kHz
56.4 kHz
Jitter ramp
Internal
sawtooth
adjustable
Figure 36. Modulation Effects on the Clock Signal by the Jittering Sawtooth
Line Detection (for A version only)
An internal comparator monitors the drain voltage as
recovering from one of the following situations:
•Short Circuit Protection,
•VCC OVP is confirmed,
•UVLO
•TSD
If the drain voltage is lower than the internal threshold
VHV(EN) (87 Vdc typically), the internal power switch is
inhibited. This avoids operating at too low ac input.