Panasonic GP 31 Quick start guide

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Technical Guide
Colour Television
GP 31 Chassis
Circuit Explanations
Panasonic Panasonic AVC Networks
Kuala Lumpur Malaysia Sdn. Bhd.

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Contents
Introduction 3
Location of Control & Circuit Boards 4
GP-31 Chassis Block Diagram 5
1. Tuning Circuit
1.1 Signal Processing 6
1.2 IF Control 6
2. Ultimate One Chip IC601
2.1 Features 8
2.2 IIC Bus 9
2.3 Memory IC 9
2.4 Reset Circuit 10
2.5 IC601 Pin Configuration 11
3. Video Circuit
3.1 Video Signal Processing 14
4.AudioCircuit
4.1 Audio Processor 17
4.1.1 Sound Processor 17
4.1.2 Audio Amplifier 17
5. Deflection Circuit
5.1 Horizontal Output Circuit 20
5.1.1 Horizontal Output Operation 21
5.2 Vertical Output Circuit 23
5.2.1 Vertical Output Operation 23
6. Colour Output
6.1 Colour Output Stage 24
7. Protection Circuit 25
8.PowerCircuit
8.1 Start-up Circuit 29
8.2 Output Voltage Control 29
8.3 Regulation 30
8.4 Over Voltage Protection Circuit 30
8.5 Over Current Protection Circuit 31
8.6 Latch Circuit 31
8.7 Standby Operation 31

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! WARNING
This service information is designed for experienced repair technicians only and is not
designed for use by general public. It does not contain warnings or cautions to advise
non-technical individuals of potential dangers in attempting to service a product. Products
powered by electricity should be serviced or repaired only by experienced professional
technicians. Any attempt to service or repair the product or products dealt with in this
service information by anyone else could result in serious injury or death.
Introduction
We at Panasonic realise that the service engineer needs to understand the circuitry
inside the TV and for this need, we have produced this Technical Guide.
This Technical Guide contains information for GP 31 chassis and should be used
in conjunction with the relevant Service Manuals for this chassis.
As the Technical Guide for the GP 31 chassis covers such a wide range of models,
some differences may occur in circuit descriptions and component references.

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Location of Control & Circuit Boards
Board Name Function
A-Board Main Board
L-Board CRT Board
A- Board
L-Board

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GP-31 Chassis Block Diagram

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1. Tuning Circuit
Outline
The tuner is designed for reception of the conventional frequencies to date and the
intermediate special channel frequencies. The IF stage of the tuner contains the video and
audio demodulators which are designed for most widely used TV standards.
1.1 Signal Processing
1. The purpose of the tuner is to convert the VHF/ UHF TV broadcast signal (RF) into
intermediate frequency signal, IF (38.0MHz) [Fig 1.0].
2. The aerial intercepts the TV signal and amplified by the RF amplifier.
3. The local oscillator generates basic frequency to convert RF signal into IF signal
(intermediate signal) in the mixer.
4. Here the IF signals is output to UOC IC601 for video and sound processing.
1.2 IF Control
Control of internal Tuner-IF processing is performed by the UOC IC601, the
IC601 sending control information via I²C bus input via pin 71 (SCL) and 72 (SDA).
In addition to this, AGC control of the Tuner-IF stage is controlled by the UOC
via I²C. AFC information for Tuner-IF stage is fed back to the IC601 via control line
AGC (pin 22).
Fig 1.0

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UOC IC601

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2. Ultimate One Chip IC601
Outline
The IC601 TDA959xN, also known as UOC, is a high-quality single chip TV
processors IC which allow the economic integration of features in all classes of single-
scan TV sets. UOC combine the functions of a video processor together with a
microcontroller and teletext decoder.
The integrated microcontroller is supported by a powerful OSD generator with
integrated Teletext & Close Caption acquisition including on-chip page memory.
2.1 Features
a. TV Processor
•Multi-standard vision IF circuit
•Picture improvement features with peaking black stretching
•Multi-standard colour decoder with automatic search system
•Internal base-band delay line
•Horizontal and vertical geometry processing
•OSD/text gain reduction control
•White point and black level off-set adjustment
b. Micro-controller
•80C51 micro-controller core standard instruction set and timing
•1 µs machine cycle
•128K-byte ROM
•12K-byte RAM
•Data Back-up
Storage of tuning, switching, control and adjustment data to the memory
(IC1103) and reading out the data
•Switching and Control
Output of the control signal for picture and sound, etc., and switching signal
for TV/AV mode and so on
•Adjustment
Output of adjustment levels for UOC (IC601) through I²C bus.
c. Teletext Decoder
•Text memory for 1 or 10 pages
•Automatic detection of FASTEXT transmission
•Data Capture for US Closed Caption

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2.2 I²C bus
•The I²C bus is a two bus system consisting of a data line and a clock line.
•5V is set for SDA / SCL. [Fig 2.0]
•Allow a large number of switching and control functions of GP-31 chassis.
The UOC IC601 generates bus signals which control the following hardware
configuration.
1. EEPROM IC1103
These memories are 1K-byte, non-volatile memories of microchips, and bit pattern of
1024 x 8 bits.
2. Tuner TU001
To select a desired channel signal from the several RF signal from TV stations and
convert the selected RF signal into a signal of an intermediate frequency (IF).
3. Sound Processor IC2101
The sound processor IC will cover the sound processing of all analog TV-Standards
worldwide, as well as the NICAM digital sound standards.
2.3 Memory IC
Fig 2.1
Fig 2.0

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The memory IC1103 receives the data listed below as supplied from the UOC
IC601 through I²C bus [Fig 2.1]. It is input or output whenever it is necessary. This
memory IC is a non-volatile type, which data is maintained permanently although the
power is cut off.
Last Memory Location
These memory locations will contain the following information that must be
stored inside even if power to the EEPROM is interrupted.
1. 100 channels of BT voltage and band (VL, VH, U) information.
2. 100 channels of AFC, SKIP, COLOR SYSTEM and SIF information.
3. Last position for each switching mode.
4. Volume data.
5. TV/ AV1/ AV2 mode.
6. Recall ON/ OFF.
7. Power and auto off timer setting.
8. Service mode setting.
9. The COLOUR, NTSC TINT, BRIGHT, CONTRAST and SHARPNESS DAC
data, and each SUB-DAC data, CUT-OFF, RGB-DRIVE etc.
10. PICTURE MENU & SOUND MENU.
11. AVL
Pin No. Name Function
1 A0 GROUND
2 A1 GROUND
3 A2 GROUND
4 GND GROUND
5 SDA Serial Data In/Out
6 SCL Serial Clock Input
7 WP Write Protect Input
8 VCC 5V
2.4 Reset circuit
1. Power on reset is generated internally to the UOC IC601; hence no external reset
is required. (The TV processor generates the master reset in the system, which in
turn will reset the micro-controller.)
2. During power ON operation, or during a momentary drop in the +B voltage,
insufficient voltage supply to UOC IC601 may occur. Thus, there is a possibility
that incorrect operation of the UOC occur.
3. In order to prevent incorrect operation, a resetting pulse is activated until the
voltage fed to the UOC is normalized.
4. When the power switch is turned on, if the VDD of the UOC is less than 3.3V
then UOC starts to reset.
5. UOC start to function again when VDD becomes more than 3.3V.

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2.5 IC601 Pin Configuration
Pin No. Name Function
1 KEYSCAN Panel key
2 AUTO/MAN Geomagnetic controlling
H: Auto L: Manual
3 MSP RESET H: Normal
L: Reset (During power ON)
4 GND (D) Digital ground for µ-Controller core and periphery
5 AV/TV TV / AV search
H: AV / Auto Search L: TV
6 4.5V / OTHERS H: 4.5MHz L: Other / AV
7 VSSA Digital ground of TV-processor
8 SECPLL SECAM PLL decoupling
9 +8V 2nd supply voltage TV-processor
10 DECDIG Supply voltage decoupling of digital circuit of TV-
processor
11 PH2LF Phase-2 filter
12 PH1LF Phase-1 filter
13 GND3 Ground 3 for TV-processor
14 DECBG Bandgap decoupling
15 EWD East-West drive output
16 VDRB Vertical drive B output
17 VDRA Vertical drive A output
18 IFIN1 IF input 1
19 IFIN2 IF input 2
20 IFREF Reference current input
21 VSC Vertical sawtooth capacitor
22 AGCOUT Tuner AGC output
23 DEFM SIF input 1
24 DECUP SIF input 2
25 GND2 Ground 2 for TV-processor
26 SNDPLL Narrow band PLL filter
27 FSC Sub-carrier reference output
28 AV1L Audio 1 Left input
29 AV2R Audio 2 Right input
30 HOUT Horizontal output
31 FBISO Flyback input / Sandcastle output
32 DESCDEM Decoupling sound demodulator
33 QSS / DEAMP QSS intercarrier output / AM output in stereo applications
or deemphasis (front-end audio out) / AM output in mono
applications
34 EHT / PROTECT EHT / overvoltage protection input
35 PLLIF IF-PLL loop filter
36 SIFAGC AGC sound IF
37 INTCO Not used
38 IFVO/SVO IF video output / selected CVBS output
39 +8V Main supply voltage for TV-processor
40 CVBS1 Internal CVBS input

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41 GND Ground for TV-processor
42 AV1V Video AV1 input
43 GND Ground for TV-processor
44 AV2V Video AV2 input
45 C Chroma input
46 WHSTR White stretch capacitor
47 CVBSO CVBS output
48 AUDOUT / AMOUT Audio output / AM audio output (volume controlled)
49 SVM Not used
50 INSSW2 2nd RGB / YUV insertion input
51 VIN V (R-Y) input / PRinput
52 YIN Y input
53 UIN U (B-Y) input / PBinput
54 BCLIN Beam current limiter input
55 BLKIN Black current input / V-guard input
56 RO Red output
57 GO Green output
58 BO Blue output
59 +3.3V Analog supply of Teletext decoder and digital supply of
TV-processor (3.3V)
60 VPE OTP Programming Voltage
61 VDDC Digital supply to core (3.3V)
62 OSCGND Oscillator ground supply
63 XTALIN Crystal oscillator input
64 XTALOUT Crystal oscillator output
65 RESET Not used
66 +3.3V Digital supply to periphery (+3.3V)
67 LED Red LED (Wake up timer)
[Normal] H: STDBY L: Power off
[Wake up] H: ON (1 sec) L: OFF (1 sec)
[Protect Mode] 0.5 sec : ON 4 sec : OFF
68 YUV-L (SW) Input for YUV
H: YUV Input L: Manual
69 REM-IN Input for the remote control signal
70 STDBY / ON Power ON/OFF switching signal for main power circuit
H: ON L: Standby
71 SCL I²C-bus clock line (+5V)
72 SDA I²C-bus data line (+5V)
73 VOLUME Tuning PWM output (0 ~ 3.3V)
74 PWM0 Not used
75 EEPROM Write Protect H : Protect OFF L : Protect ON
76 AV-SW1 AV switch 1
H: AV1/DVD L: TV/AV2
77 AV-SW2 AV switch 2
H: AV2/DVD L: TV/AV1
78 REG / RELAY H: Relay ON
L: Relay OFF
79 SYNC_FILTER Sync filter input
80 MUTE Monitor defeat controlling
H: Monitor defeat
L: Defeat OFF

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Video Circuit

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3. Video Circuit
Outline
Video signal processing is performed in the UOC IC601. The IF signal from tuner,
video inputs from AV1, AV2 and YUV are fed to UOC IC601 for video processing. RGB
output from UOC IC601 is then fed to CRT drive circuit to drive the CRT.
3.1 Video Signal Processing
IF signals from tuner are input to IC601 at pin 18 & 19. It is then fed to an
external sound trap at pin 38 to remove the unwanted SIF component and output signal is
fed to pin 40 IC601. Video inputs from AV1 (pin 42), AV2 (pin 44) and IF signal are fed
to internal Video Switch. The selected video signal will go through YC separation and
colour decoding where output (YUV) is then fed to an internal YUV switch.
YUV signal is input at pin 52, 53 and 51 to IC601. Internal YUV switch will feed
the selected YUV signals to RGB matrix to produce RGB signals. RGB signals are then
send to CRT drive circuit located on L-Board via pin 56, 57 and 58 to drive the CRT.
Fig 3.0

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Audio Circuit
Stereo / AV Stereo

16
Mono

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4. Audio Circuit
Outline
Three sound modulations available in GP-31 chassis which are STEREO, AV
STEREO and MONO. Depending upon the version of the UOC IC601 and MSP IC2101
used, gives different sound modulation.
4.1 Audio Processor
Two different sound processors are used in GP-31. IC2101 is used as Sound
Processor and IC2301 as Audio Amplifier.
4.1.1 Sound Processor (IC2101)
Outline
The IC2101 is a single-chip multi-standard sound processor covers the sound
processing of all analog TV-standards worldwide, as well as the NICAM digital sound
standards. The full TV sound processing, starting with analog sound IF signal-in, down to
processed analog AF-out, is performed on this single chip.
For STEREO model, audio signals from AV terminals are fed to pin 53 & 54
(AV1), pin 56 & 57 (AV2) and pin 47 & 48 (YUV) of MSP IC2101 for sound processing.
SIF signal from UOC IC601 pin 33 is fed to pin 67 of IC2101. The audio signals are then
fed to Audio amplifier IC2301 before output to loudspeakers.
For AV STEREO model, audio signals from AV terminals are fed to pin 53 & 54
(AV1), pin 56 & 57 (AV2) and pin 47 & 48 (YUV) of MSP IC2101. SIF signal is from
UOC IC601 pin 48 is fed to pin 60 of IC2101. The audio signals are then fed to Audio
amplifier IC2301 before output to loudspeakers.
As for MONO model, audio signals are fed directly to pin 28 (AV1 Left-channel)
and pin 29 (AV2 Right-channel) of UOC IC601 for sound processing. The audio output
is then fed to Audio amplifier IC2301A for amplification before loudspeakers via pin 48
of IC601.
4.1.2 Audio Amplifier (IC2301 & IC2301A)
Outline
The audio signal from IC2101 is amplified by IC2301 and passes it to loudspeakers.

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Deflection Circuit

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Horizontal Output Circuit
COLLECTOR
(FBT)
140V
H-DRIVE
FBI
H-OUT

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5.1 Horizontal Output Circuit
Outline
1. The horizontal synchronous pulse output from IC601 pin 30 is then input to the
Horizontal Drive Circuit (Q501, T553).
2. The horizontal drive circuit creates a base current (drive current) fully sufficient to
turn the horizontal output circuit (Q551) ON and OFF quickly, and inputs this current
to the horizontal output circuit (Q551).
3. The horizontal output circuit (Q551) has the function of sending the deflection current
to DY in order to make the electrical beam scans horizontally. Beside this, it also has
an additional function of generating a high voltage in the second stage voltage coil of
the Flyback Transformer (T501) and supplying this voltage to the CRT anode pole
and the focus pole.
4. A number of voltages are taken for using in Focus, CRT, and Heaters etc from the
secondary of the Flyback Transformer.
Fig 5.0
3
3
D
D556
D557
C
C562
C565
C568
H-OUT
Q551
4
3
Coil
Current
Collector
Current
Base
Voltage
OFF ON OFF ON OFF
Collector
Voltage
Damper
Current
t1 t2 t3 t4 t’1 t’2 t’3 t’4