Pentek 4284 User manual

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Pentek Model 4284 Operating Manual Page 1
Manual Part No: 800.42840 Rev: F.2 − July 26, 2000
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OPERATING MANUAL
MODEL 4284
TMS320C40 Digital Signal Processor
MI Baseboard for VMEbus Systems
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Pa ge 2 Pentek Model 4284 Operating Manual
Pentek Model 4284 Operating Manual − Revision History
References made in this manual to the Texas Instruments TMS320C4 User's Guide are made specifically to Revision C of that publication, dated August 1993
WARRANTY
Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are free from defects in mate−
rials and workmanship for a period of one year from the date of delivery when used under normal operating conditions and within the
service conditions for which they were furnished
The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any product
which in Pentek’s sole opinion proves to be defective within the scope of the warranty
Pentek must be notified in writing of the defect or nonconformity within the warranty period and the affected product returned to Pentek
within thirty days after discovery of such defect or nonconformity
Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Pentek for warranty service Pentek shall pay
for the return of products to buyer except for products returned from another country
Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized modification, misuse, neglect, inade−
quate maintenance, accident or for any product which has been repaired or altered by anyone other than Pentek or its authorized representatives
The warranty described above is buyer’s sole and exclusive remedy and no other warranty, whether written or oral, is expressed or implied
Pentek specifically disclaims fitness for a particular purpose Under no circumstances shall Pentek be liable for any direct, indirect, special,
incidental or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or any other legal theory
Date Rev Applicable Serial #’s Comments
01/03/94 Pre 9401003 − 9441043 Initial Product Release − Manual generated by Engineering Dept
06/03/94 A 9401003 − 9441043 Complete rewrite, reformat and update Changed pinout of TCK connector Added Software
examples and Appendices
06/10/94 A 1 9401003 − 9441043 Added header file listings to sample 4284 setup code in Appendix A, Section A 1
07/08/94 B 9401003 − 9441043 Listed Pentek part # for ordering Comm Port cables Minor change to detail block diagram Add
section 4 8 on memory usage & table of transfer times
10/11/94 B 1 9401003 − 9441043 Changes to Tables 4−8 to properly represent transfer timing for 50 MHz 'C40 Delete Table 4−9 &
refer to 'C40 Manual for DMA timing info Changes to Sections 2 11 4 and 3 2 1, regarding which
signals are inputs and which are outputs
11/11/94 B 2 9401003 − 9441042 Correct pin numbering error in Table 2−12 System Clock jumper installed between pins 1−2, not 11−12
12/29/94 C 9441043 − Forward New features: Flash EEPROM and Turbo−MIX Properly identify jumper blocks SW1 and SW2 in
Figure 2−2 Expanded discussion of Reset Operation Add more transfer timing tables for 40 and
50 MHz parts, using block repeat, DMA and Turbo−MIX Descriptions of these tables updated
Turbo−MIX example added to Appendix A Flash EEPROM programming code added to Appen−
dix A Update Boot Code in Appendix B
01/27/95 C 1 9441043 − Forward Add info re:Option 010, in which A32 address is independent of A24 address, and Memory Window
jumpers affect A24 window only Correct Table 2−2 (A16 address 8700 is reserved) A24 inhibit bit also
prevents A32 access This change affects Section 2 4 3, Section 3 11 2 4, and Table 3−12
01/05/96 C 2 9441043 − Forward Mention FTL in Section 1 9 (Software Support) Add info on mating connector for front panel Serial
and GPIO connectors (Sec 2 11) Add Section 2 14, describing blinking of Front Panel LED on
power−up Correction to note in Section 4 2 1, reference to EPROM rev should be Revision E, not B
Indicate that use of the Linker Command File shown in Sections 4 3 1 and A 6 requires a change to
main Changes to Hex File Loader & Starter in Section A 7
09/10/96 D 9441043 − Forward Sec 3 8 5: 'C40 Int to VME Status bit in Transfer Mode Reg is accessible to the 'C40 (not VME) for read
only Add Tables & Figures to Table of Contents Update MIX Appendix to Rev F 1
07/02/97 D 1 9441043 − Forward IACK Vector Register must be re−written to clear VME interrupts generated by 4284 This infor−
mation added as a Note in Section 3 11 1, and to text in Section 4 6 1
09/22/97 D 2 9441043 − Forward Section 4 2 1 − The code that triggers a boot from Flash EEPROM is A55A 5AA5, not A55A A55A −
this changes the last paragraph on pg 52, the first paragraph on pg 53, Table 4−4, and the first
paragraph on page 57
05/04/98 E 9441043 − Forward Add Parallel C to Software Development Support section (1 9) Replaced board diagram with VSB ver−
sion of board Added section 3 12 on VSB Modified Table 3−7 to include VSB addresses
05/21/98 E 1 9441043 − Forward Revisions to VSB section (3−12) − renamed Table 3−14 (VSB Control Register) and renamed some bits
in the table Add Tables 3−15 − 3−17 illustrating bit field usages in VSB Control Register Add VSB
interface to Detailed Block Diagram (Fig 4−1) In SW Development Support section (1 9) Parallel C is
now called Diamond
7/23/98 E 2 9441043 − Forward Correct & cross reference to Table 3−16 in Table 3−14
10/12/98 E 3 9441043 − Forward Correct address range for VME Master Access in Table 3−7 (0xB000 0000 − 0xBFFF FFFF)
10/22/98 F 9441043 − Forward Regardless of DRAM Window size, DRAM must be mapped on an address bounmdary that is a multiple
of the actual DRAM size This changes text in Secs 2 4 2 and 2 4 3, and Tables 2−5 − 2−7, and deletes
Tables 2−8 & 2−9 (these tables all concerned base address vs window size) Add note to Sec 2 4 3 indi−
cating that for DRAM access, each ‘C40 address is equivalent to four VME addresses Reinforce same
concept in Sec 4 10 Give VME address of DRAM in Sec 3 10 & add a note to the ‘C40 memory Map stat−
ing that DRAM is shared w/ VME Sec 4 2 3 − Host Control Reset does NOT reset MIX or VSB Change
timer address in Sec A 4 (1st executable line under main()) to 0x100020 Remove MIX Appendix & refer−
ences to it (this info now included in 800 00001)
12/06/99 F 1 9441043 − Forward Sec 1 9 − Removed SPOX, FTL & Diamond from Software Support list Corrections to Tables 2−5 thru
2−7, which were correct up until last Rev Sec 2 1 2 1 − Comm Port Cable is Model 2104, not 2014 Table
4−3: Removed extra ‘0’ in last row of address column Added NOTEs to Sec’s 4 2 4 & 4 3 5 about initial−
izing the Local Control Register if you do not boot from the factory EPROM Remove Sec 4 4 2 (Down−
loading SPOX programs), and the sentence referencing SPOX in Sec 4 4
7/26/00 F 2 9441043 − Forward Sec 1−12: delete reference to Opt 060 Additional corrections to Tables 2−5 thru 2−7 Update Boot Code
listing in Appendix B
Printed in the United States of America All rights reserved Contents of this publication may not be reproduced in any form without written permission
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Pentek Model 4284 Operating Manual Page 9
Rev.: F.2
Chapter 1: Overview
1.1 General Description
The Model 4284 MIX Baseboard for VMEbus systems s based on the Texas Instruments
TMS320C40 Float ng Po nt D g tal S gnal Processor. The 4284’s ‘C40 acts as both a
VMEbus Master and a MIX bus Master. It serves as a powerful 40 or 50 MFlop D g tal
S gnal Processor, as well as a complete DMA controller.
Th s manual w ll descr be the nstallat on and operat on of the Model 4284 n several
typ cal VMEbus env ronments.
1.2 MIX Bus Support
The Model 4284’s MIX nterface supports h gh−speed, mult −master control and data
transfer to any of Pentek’s MIX modules. Mapped d rectly nto the ‘C40’s local bus, th s
32−b t data channel ncludes support for full nterrupt handl ng and generat on, to
ensure opt mum real−t me performance.
1.3 TMS320C40 Comm Port Interface
The s x h gh−speed Commun cat ons Ports of the ‘C40 are buffered, and brought
out to conven ent front panel connectors. Any MIX module stacked on the 4284
thus becomes Comm Port compat ble. In th s manner, the 4284 acts as a Comm
Port based I/O controller for other ‘C40 systems.
1.4 Fle ible VMEbus Control
The Model 4284 has master, slave and system controller capab l t es on the VMEbus.
As a bus master, t can read from and wr te to the ent re 32−b t address space of the
VMEbus, thus access ng any external slave dev ce. As a system controller, t can act as
a bus arb ter for mult ple−master systems.
1.5 Local and Global Static RAM
Two separate banks of SRAM are prov ded for the ‘C40, one on ts local bus and the
other on the global bus. Each bank may be e ther 1 or 2 MBytes deep, depend ng upon
the opt ons ordered. These resources max m ze the use of the ‘C40’s dual−bus arch −
tecture and ts ab l ty to conduct data and program cycles n parallel on the two busses.
Both the local and global SRAMs operate w th zero wa t state performance.
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Page 10 Pentek Model 4284 Operating Manual
Rev.: F.2
1.6 Dual Access DRAM
A 4, 8 or 16 MByte dual−access DRAM prov des an extremely powerful structure for
pass ng data and programs between the ‘C40 and the VMEbus. From the VMEbus, th s
resource appears as relocatable slave memory n A24 or A32 address space. From the
‘C40, t s mapped d rectly onto the global bus.
1.7 Local EPROM
In order to support nonvolat le storage of programs or data, the Model 4284 s
equ pped w th a user−programmable 32 kByte EPROM, located on the ‘C40’s local bus.
Ideal for embedded systems, that self−boot from power−up, th s memory s also used
for system f rmware.
1.8 Flash EEPROM Option
The Model 4284 may opt onally be equ pped w th a 128 kByte (Opt on 002) or 512 kByte
(Opt on 003) n−c rcu t programmable Flash EEPROM. The Flash EEPROM s mapped
as a 'C40 Local Bus resource, and code programmed nto t may be executed at boot t me.
1.9 Software Development Support
No DSP hardware product offer ng s complete w thout a full complement of develop−
ment software. The Model 4284 software products are descr bed br efly below.
SwiftTools
Development
Environment
Pentek’s Sw ftTools s a complete software development env ronment for
PC−AT and SUN workstat ons. It s ta lored to work d rectly w th
Pentek’s fam ly of d g tal s gnal process ng products wh ch ncorporate
TMS320C40 and TMS320C30 d g tal s gnal processors. Sw ftTools
ntegrates all of the operat ons nvolved n a typ cal software develop−
ment project and supports full C language source code generat on and
debugg ng w th a comprehens ve su te of powerful tools for a w de range
of appl cat ons. Sw ftTools ncludes an n−l ne assembler and
d sassembler for on−screen changes to object code n RAM. Reg sters can
be exam ned and loaded, and memory reg ons can be exam ned, f lled,
and moved. Full f le upload ng and download ng rout nes are prov ded
and prov s ons for EPROM byte man pulat on are ncluded.
SwiftNet
Communications
Protocols
Pentek’s Sw ftNet s a software product that supports a network of d str buted
VMEbus systems connected v a Ethernet to a host computer, such as a
SUN workstat on or PC−AT. All software development tools are run on
the host w th remote target access prov ded transparently to the user.
Sw ftNet ut l zes the ndustry standard TCP/IP nterface for Ethernet,
mak ng t qu te portable across many Operat ng System env ronments.
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Pentek Model 4284 Operating Manual Page 11
Rev.: F.2
1.9 Software Development Support (cont nued)
Macro
Assembler/
Linker
The assembler translates assembly language source code nto mach ne
language object f les n common object f le format (COFF). The l nker sect on
comb nes the COFF object f les nto an executable object module. The
arch ver supports a macro l brary access ble by the assembler.
C Compiler The comp ler s a full mplementat on of Kern ghan and R tch e C
language, generat ng assembly language compat ble w th the Macro
Assembler/L nker. T me cr t cal assembly language rout nes are callable
w th n the C program.
Code Composer Go−DSP’s Code Composer s a fully ntegrated development
env ronment w th advanced features spec f cally tuned for DSP code
Des gners. It allows code des gners to ed t, bu ld, manage projects,
debug and prof le from a s ngle appl cat on.
XDS−510
Emulator
The Texas Instruments XDS510 Emulator allows the user to access
the ‘C40 through a ‘back door’ port prov ded by a spec al 14−p n
connector on the board. The emulator board s nstalled n a PC/AT
computer where all software development can take place.
Bus Adapters Pentek offers bus adapters to prov de a connect ng l nk between the
computer your ‘C40 programs w ll be developed on and the VMEbus
card cage where those programs w ll be run. Supported platforms
nclude PC/AT compat bles, SUN SPARCStat ons and HP Workstat ons.
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Page 12 Pentek Model 4284 Operating Manual
Rev.: F.2
1.10 VSB Interface (Option 012)
The VME Subsystem Bus (VSB) s a secondary bus ut l z ng the outer rows of p ns
(rows A and C) on the VME P2 connector, wh ch are unused n the standard VMEbus
mplementat on. The Model 4284 operates as a VSB master and nterrupt handler us ng
the VSB1400A/B ch p set from PLX Technolog es.
1.11 Block Diagram
A s mpl f ed block d agram of the Model 4284 TMS320C40 DSP/MIX Baseboard for
VMEbus systems s presented as F gure 1−1, below. More deta l can be found n the
d agram presented as F gure 4−1, on page 58 of th s manual. The elements of these
d agrams w ll be d scussed n deta l n Chapter 4 of th s manual.
Figure 1−1: Model 4284 − Simplified Block Diagram
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Pentek Model 4284 Operating Manual Page 13
Rev.: F.2
1.12 Specifications
Processor
Type: Texas Instruments TMS320C40
Clock Speed
Standard: 40 MHz
Option 015: 50 MHz
Address Bus: 32 Bits
ata Bus: 32 Bits
Dual−Access D AM
Size
Standard: 4 MBytes (1M x 32)
Option 007: 8 MBytes (2M x 32)
Option 008: 12 MBytes (3M x 32)
Option 009: 16 MBytes (4M x 32)
Arbitration: Hardware, fully transparent
‘C40 Access: Memory mapped on Global bus, 3 wait states
VMEbus Access: 4, 8, 12 or 16 MBytes of VMEbus slave memory
Relocatable on 1 MByte boundaries, 170 ns TACK delay
Local Static AM
Size
Standard: 256k x 32 (1 MByte)
Option 005: 512k x 32 (2 Mbyte)
‘C40 Access: Memory mapped on local bus, 0 wait states
Global Static AM
Size
Standard: 256k x 32 (1 MByte)
Option 006: 512k x 32 (2 Mbyte)
‘C40 Access: Memory mapped on global bus, 0 wait states
EP OM
Size
Standard: 32 kBytes
Option 016: 64 kBytes
‘C40 Access: Memory mapped on Local Bus, 1 wait state
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Page 14 Pentek Model 4284 Operating Manual
Rev.: F.2
1.12 Specifications (cont nued)
Flash EEPROM (optional)
Size
Opt on 002: 128 kBytes
Opt on 003: 512 kBytes
‘C40 Access: Memory mapped on Local Bus, 1 wa t state
VMEbus Compliance
Bus Master: D32 A32 I(1−7) IH(1−7)
Slave: D32 A32
Slot 1 Controller: Level 3 Arb ter, can dr ve SYSCLK and SYSRST
MIX Bus Compliance
Type: Conforms to Intel MIX Spec f cat ons, Master/Slave,
Interrupt generator and handler
Width: 32−b ts for data and address
Speed: 16 MBytes/sec typ cal
J−Tag XDS Support: 14−p n Connector for Texas Instruments XDS−510 J−Tag Emulator
Serial I/O Support: Front Panel 10−p n connector for RS−232 level s gnals.
Misc. I/O Support: Front Panel 10−p n connector for t mers, flags, etc.
VME Subsystem Bus (VSB) Interface: (Opt on 012 ONLY!)
Master, Interrupt Handler
Address Bus W dth: 32 b ts
Data Bus W dth: 32 b ts
Physical
Dimensions: 6U Eurocard − (160 mm x 233.35 mm)
Mult layer construct on.
Power: + 5 VDC @ 3A max.
– 5 VDC @ 0A (for MIX modules only)
+12 VDC @ 0A (for MIX modules only)
–12 VDC @ 0A (for MIX modules only)
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Pentek Model 4284 Operating Manual Page 15
Rev.: F.2
Chapter 2: Installation and Connections
2.1 Inspection
After unpack ng the un t, nspect t carefully for poss ble damage to connec−
tors or components. If any damage s d scovered, contact Pentek mmed ately
at (201) 818−5900. Please save the or g nal sh pp ng conta ner and pack ng
mater al n case re−sh pment s requ red.
2.2 Introduction
Th s sect on conta ns nformat on and nstruct ons for the conf gurat on and var ous
modes of operat on of the Model 4284. These are ach eved by sett ng jumper blocks on
the board, before t s nstalled n the VMEbus card cage.
The Model 4284 supports up to three expans on modules, wh ch may be attached to ts
MIX stack ng connector. These modules and the MIX nterface system are descr bed n
the manual ent tled “MIX Tutor al for VMEbus Systems”, ncluded w th your sh p−
ment. Pr or to attach ng any expans on modules you should successfully nstall the
Model 4284 by tself. Th s makes access to the jumper blocks and d agnos s of nstalla−
t on problems eas er.
2.3 Jumper Block Locations
A draw ng of the Model 4284’s the c rcu t board, show ng the locat on of jumper blocks
referred to n the sect ons below, s shown n F gure 2−2, on the follow ng page.
F gure 2−1, below, shows the p n number ng for double−row jumper blocks used n the
Model 4284. P n 1 of the jumper blocks s nd cated by the l ne extend ng from the box
that surrounds the header. All of the jumper blocks on the 4284 are r ght−angle head−
ers, located near the edges of the board. Th s makes them access ble w thout remov ng
the DRAM mezzan ne card or any attached MIX modules.
For most of the jumper blocks on the Model 4284, each jumper pos t on represents a b t.
Install ng a jumper n a g ven b t’s pos t on sets that b t to a ‘0’. Leav ng the jumper off
sets the b t to a ‘1’.
Figure 2−1: Jumper
Block Pi Numberi g
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Page 16 Pentek Model 4284 Operating Manual
Rev.: F.2
Figure 2−2: Model 4284 Circuit Board Showing Jumper Block Locations Option −012 (VSB) shown.
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Pentek Model 4284 Operating Manual Page 17
Rev.: F.2
2.4 VMEbus Slave Base Address Jumper Settings
The VMEbus Slave resources ava lable on the Model 4284 are the dual−access DRAM
(shared w th the ‘C40), access ble n A24 or A32 address space, and the Host Control
Reg ster and IACK Vector Reg ster, both accessed n A16 space. The base addresses for
these resources are determ ned by the placement of short ng jumpers on the jumper
blocks descr bed n the sect ons below.
2.4.1 A16 Base Address − Jumper Block JB6
The Host Control Reg ster allows a VMEbus Bus Master to control the reset
and nterrupt l nes nto the ‘C40. The IACK Vector Reg ster s an 8−b t reg−
ster loaded from the VMEbus wh ch stores a vector that the Model 4284
sends n response to an nterrupt acknowledge (IACK) cycle.
Both of these reg sters are mapped nto the VMEbus 16−b t address space,
for Address Mod f er Codes 29 and 2D. The addresses at wh ch they res de
are selected by the placement of short ng jumpers on jumper block JB6. If
there s more than one Model 4284 n a card cage, these jumpers can be set to
un quely conf gure the addresses for each board. The address set by th s
jumper block s referred to as the A16_base address.
Jumpers should ALWAYS be nstalled n pos t ons 9−10 and 11−12 on
jumper block JB6. For the rema n ng pos t ons, p ns 1−2 set the value of
address b t A8, p ns 3−4 set A9, p ns 5−6 set A10, and p ns 7−8 set the value
of A15. Any A16 address on the VMEbus s compared w th the sett ngs of
these jumpers to determ ne f th s s the board to be accessed.
For any g ven board, the IACK Vector Reg ster s mapped at the A16_base
address and the Host Control Reg ster s mapped at A16_base + 0x0004.
Table 2−1, below, descr bes the address b ts that are set by th s jumper
block, and the r hexadec mal we ghts. Table 2−2, on the next page, l sts the
16 ava lable A16 Base Addresses, and the jumper sett ngs used to obta n
each of them. Note that one of the 16 poss ble comb nat ons (all four jump−
ers removed) s not a val d select on.
Table 2−1: Model 4284 − A16 Base Address − Jumper Block JB6
Address Bits a d Hexadecimal Weights of Jumper Positio s
Pi s 11 − 12 Pi s 9 − 10 Pi s 7 − 8 Pi s 5 − 6 Pi s 3 − 4 Pi s 1 − 2
Jumpers must always be
installed on these pins
A15
(0x8000)
A10
(0x0400)
A9
(0x0200)
A8
(0x0100)
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Page 18 Pentek Model 4284 Operating Manual
Rev.: F.2
2.4 VMEbus Slave Base Address Jumper Settings (cont nued)
2.4.1 A16 Base Address (cont nued)
2.4.2 VME DRAM Window Size Jumpers − Jumper Block JB7
Jumper block JB7 s used to set the s ze of the area occup ed by the Model
4284’s DRAM n VME A24 or A32 Address space. These jumpers are set at
the factory for the memory nstalled n your un t. However, the nstalled
memory s ze s an mportant parameter to cons der when sett ng the Base
Address. Th s s because the memory must be mapped on address bound−
ar es that are mult ples of the w ndow s ze. For example, for the standard
(4 MByte) DRAM s ze, only four A24 base addresses (0x00 0000, 0x40 0000,
0x80 0000 and 0xC0 0000) are val d.
If you have 16 Mbytes of DRAM n your Model 4284 (Opt on 009), and are
restr cted to the use of A24 address space ( . e., your card cage or cage con−
troller has no VME P2 connectors), then the 4284’s DRAM occup es ALL of
your ava lable memory. In th s case, you may w sh to reduce the VMEbus’
w ndow on the DRAM by rearrang ng the jumpers on JB7 for less apparent
memory. Th s makes the upper port on of the DRAM naccess ble by
VME, but t s st ll ava lable to the ‘C40.
Table 2−2: Model 4284 − A16 Base Address − Jumper Block JB6
Jumper Setti gs for Available Base Addresses
Hex Address Pi s 7 − 8 Pi s 5 − 6 Pi s 3 − 4 Pi s 1 − 2
*0x0000 ON ON ON ON
0x0100 ON ON ON OFF
0x0200 ON ON OFF ON
0x0300 ON ON OFF OFF
0x0400 ON OFF ON ON
0x0500 ON OFF ON OFF
0x0600 ON OFF OFF ON
0x0700 ON OFF OFF OFF
0x8000 OFFONONON
0x8100 OFF ON ON OFF
0x8200 OFF ON OFF ON
0x8300 OFF ON OFF OFF
0x8400 OFF OFF ON ON
0x8500 OFF OFF ON OFF
0x8600 OFF OFF OFF ON
0x8700 Reserved
* − Factory deault setting
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Pentek Model 4284 Operating Manual Page 19
Rev.: F.2
2.4 VMEbus Slave Base Address Jumper Settings (cont nued)
2.4.2 VME DRAM Window Size Jumpers (cont nued)
For the 12 Mbyte DRAM s ze (Opt on 008), f all of DRAM s to be ava lable to
the VMEbus, set these jumpers for a 16 MByte w ndow.
Table 2−3, below, tells wh ch of JB7's jumper pos t ons corresponds to
wh ch address b t, and summar zes the sett ngs of the DRAM w ndow
s ze jumper block.
NOTES: 1) Opt on 010 for the Model 4284 handles the Memory W ndow
s ze ssue d fferently. On un ts equ pped w th th s opt on,
jumper block JB7 sets the W ndow S ze for A24 space ONLY.
All of the DRAM s ava lable n A32 space n these un ts,
regardless of the sett ngs of JB7.
2) Reduc ng the DRAM W ndow s ze does not change the
requ rement that the DRAM must be mapped on a VME
address boundary that s a mult ple of the full DRAM s ze.
In A24 space, the standard (4 MByte) DRAM can only be
mapped at addresses 0x00 0000, 0x40 0000, 0x80 0000 or
0xC0 0000. The Opt on 007 (8 MByte) DRAM must have a
base address of 0x00 0000 or 0x80 0000, and the Opt on 008
(12 MByte) and 009 (16 MByte) DRAMs must be mapped at
VME address 0x00 0000 n A24 space. See Sect on 2.4.3,
wh ch beg ns at the top of the next page, for nformat on
about sett ng the DRAM base address.
Table 2−3: Model 4284 − VMEbus DRAM Window Size − Jumper Block JB7
DRAM
Wi dow
Pi s 7 − 8
(A23)
Pi s 5 − 6
(A22)
Pi s 3 − 4
(A21)
Pi s 1 − 2
(A20)
1 Megabyte ON ON ON ON
2 Megabytes ON ON ON OFF
4 Megabytes ON ON OFF OFF
8 Megabytes ON OFF OFF OFF
16 Megabytes OFF OFF OFF OFF
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