Per Vices Crimson TNG User manual

CRIMSON TNG USER MANUAL
PER VICES CORPORATION

Contents
Contents 2
ChangeLog............................................ 5
Preface .............................................. 6
Disclaimer............................................. 8
ProductFunctionality ...................................... 8
Specifications........................................... 8
Warnings ............................................. 9
1 Specifications and Interfaces 10
AbsoluteMaximumRatings................................... 10
ObservedPerformance...................................... 11
ExternalInterfaces........................................ 13
OperatingSystem ........................................ 14
Network Interface Card (NIC) Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 14
OpticalFibreRequirements................................... 14
Mechanical ............................................ 14
RFChain ............................................. 15
2 System Architecture 16
Overview ............................................. 16
PowerDistribution........................................ 17
Digitalboard ........................................... 17
TimeBoard............................................ 18
ReceiveBoardRadioChain................................... 20
TransmitBoardRadioChain .................................. 20
FPGADSPChains........................................ 21
Bandwidth, Sample Rates, and Networking . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 System Operation 23
FlowControlandStartofBurst ................................ 23
Latency .............................................. 24
ReceiveorTransmitLatency ............................... 25
RoundTripLatency .................................... 28
MinimizingLatency .................................... 28
4 Triggers 30
Global(SMA)TriggerOverview ................................ 30
Global Trigger Direction and Channel Applicability . . . . . . . . . . . . . . . . . . . 30
GlobalTriggerSensitivity ................................. 31
TriggerGating ....................................... 31
PerChannel(U.Fl)Triggers................................... 31
2

CONTENTS 3
TriggerParameterSummary .................................. 32
TriggerParameterDescriptions................................. 32
sma_dir
........................................... 32
sma_pol
........................................... 32
edge_sample_num
........................................... 33
edge_backoff
........................................... 33
sma_mode
........................................... 33
trig_sel
........................................... 34
gating
........................................... 34
ufl_mode
........................................... 34
ufl_dir
........................................... 35
ufl_pol
........................................... 35
TriggerConfiguration ...................................... 35
Website ........................................... 35
SSH ............................................. 36
UHD............................................. 36
5 Installation and Configuration 37
HardwareSetUp......................................... 37
Crimson TNG NetworkConfiguration ............................ 38
Network Set Up: Host PC Management IP Address . . . . . . . . . . . . . . . . . . . . . 41
Network Set Up: Host PC SFP+ IP Addresses . . . . . . . . . . . . . . . . . . . . . . . . 42
Build Per Vices libUHD Driver and Install GNU Radio . . . . . . . . . . . . . . . . . . . 43
Network Set Up: Modifying Crimson Management IP Address . . . . . . . . . . . . . . . 48
Testing the Management IP address . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Pingtest ...................................... 49
Websitetest..................................... 49
uhd_find_devices, uhd_usrp_probe tests . . . . . . . . . . . . . . . . . . . . 49
Add New Management IP address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Removing Management IP address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Persistently Update Management IP address . . . . . . . . . . . . . . . . . . . . . . 51
LEDSequence .......................................... 52
6 Use and Operation 53
UHD................................................ 53
WebUI .............................................. 53
SSHandCommandLine..................................... 53
ExamplePrograms........................................ 53
7Crimson TNG Device Data Format 54
DataFormat ........................................ 54
8 Troubleshooting 55

CONTENTS 4
9 Updating Crimson TNG 57
MCUFirmware.......................................... 57
Automatic MCU Update Pre-requisites . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Automatic MCU Update Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Manual MCU Update Pre-requisites . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Manual MCU Firmware Update Procedure . . . . . . . . . . . . . . . . . . . . . . . 58
FPGAFirmware ......................................... 60
FPGAUpdatePre-requisites ............................... 60
FPGAUpdateProcedure ................................. 61
FPGASignalTap ........................................ 63
FPGA Signal Tap Pre-requisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
FPGA Signal Tap Attachment Procedure . . . . . . . . . . . . . . . . . . . . . . . . 63
10 Crimson TNG Mechanical 64

CONTENTS 5
Change Log
Date and Revision Notes
2016-05-02: Rev A: Initial Release
2016-05-18: Rev B: Populating Specifications
2016-07-12: Rev C: Update System Architecture Section and Diagrams
2016-09-22: Rev D: Update Top Level and Digital Board Architecture Diagrams
2016-10-20: Rev E: Include SMA Torque Specifications
2016-12-08: Rev F: Update Installation and Configuration Chapter
2017-06-12: Rev G: Update Networking section to include instructions on how to update Crimson
IP address
2017-07-24: Rev H: Adding RTM5 Clocking architecture, additional flow charts, troubleshooting
section.
2017-09-18: Rev I: Additional clocking information, sample rate information, and adding external
reference input limitations.
2017-11-08: Rev J: Adding additional information on jitter.
2017-12-07: Rev K: Adding flow control stub, fixing reference output section to indicate Crimson
outputs its own reference.
2018-03-01: Rev L: Updating Time board architecture section, fixing: latency tables, Management
IP address section, and table troubleshooting reference bug.
2018-05-17: Rev M: Updating UHD build instructions.
2018-09-09: Rev N: Adding Trigger Chapter.
2018-10-09: Rev P: Adding gnuradio compilation notes.
2020-03-09: Rev Q: Adding additional gnuradio compilation notes.

CONTENTS 6
Preface
Crimson TNG
Crimson TNG is a high performance, wide band, high gain, direct conversion quadrature software
defined radio transceiver and signal processing platform. It has four channels, each comprised of
independent receive and transmit blocks, capable of processing up to 325MHz of instantaneous
RF bandwidth from DC to 6.8GHz and synchronized using a JESD204B subclass 1 link to ensure
deterministic latency. Data may be processed on the device itself (there is an Altera Arria V
ST FPGA SoC on-board), or sent over low latency dual 10GB Ethernet links by connecting the
integrated SFP+ headers to a compatible 10GBASE-R network device.
Crimson TNG is intended for advanced signal processing and data collection applications.

CONTENTS 7
Congratulations!
Congratulations on your purchase of the Per Vices Crimson TNG Transceiver! This manual is
intended to provide you with useful information regarding the safe operation and use of your new
transceiver. Although it may be updated from time to time, you’ll always be able to find the latest
version of the manual on the Per Vices website1.
In building Crimson TNG, we aimed to provide advanced capabilities at the lowest possible price.
This product provides a sophisticated platform capable of advanced RF Signal processing and
includes a robust and fully integrated RF chain.
Our hope is that you will find Crimson TNG to be a useful and dependable companion in your
engineering, development, and research efforts.
We welcome your feedback so please feel free to contact us.
Copyright ©Per Vices Corporation, 2017. All rights reserved.
Contact Information:
Per Vices Corporation
2440 Dundas St West Unit 204
Toronto, Ontario
M6P 1W9
Canada
www.pervices.com
[e-mail]
1http://www.pervices.com

Obligatory Warnings
This chapter contains important safety and regulatory information. Please pay attention to the
following disclaimers, warnings, and cautions. This device is intended for engineering, research, or
science laboratory use only - it is not for open office or residential use.2
Disclaimer
This product is provided «As Is». Per Vices is under no obligation to provide updates, upgrades,
support, or maintenance of any kind. Per Vices specifically disclaims any and all warranties and
guarantees, express, implied, or otherwise, arising with respect to the use of this product including,
but not limited, to the warranty of merchantability, the warranty of fitness for a particular purpose,
and any warranty of non-infringement of the intellectual property rights of any third party. Per
Vices neither assumes nor authorizes any person to assume for it any other liability.
Use of this device is at your own risk. Per Vices shall not be liable for any damages, direct or
indirect, incurred or arising from the use of this product. In no event will Per Vices be liable for loss
of profits, loss of use, loss of data, business interruption, nor for punitive, incidental, consequential,
or special damages of any kind, however caused, and on any theory of liability, whether in contract,
strict liability, or tort (including negligence or otherwise), arising in any way out of the use of this
product, even if advised of the possibility of such damages.
Product Functionality
Every effort has been made to ensure that the device you receive is fully functional - each device is
fully tested prior to shipping. Risk of damage or loss is transferred immediately upon delivery to
you - we do not generally accept returns or refunds on successfully delivered packages. That being
said, we do want to ensure your experience with Per Vices and Crimson TNG is a pleasant one
and we encourage you to contact us at [e-mail] if you have any problems.
Specifications
Every effort has been made to test and measure the validity of this equipment. However, we cannot
guarantee the accuracy of specifications, and they may change at any time.
2This device has not been tested or approved by any agency or approvals body for Electrical Safety, Electromag-
netic Compatibility, or Telecommunications at the time of distribution! Use this device at your own risk.
8

CONTENTS 9
Warnings
WARNING
RISK OF ELECTRIC SHOCK
Do not attempt to modify or touch the internals of this device.
Ensure host computer is properly grounded during operation.
Disconnect AC power during installing or removal.
WARNING
HOT SURFACE
This device may become very hot during operation; avoid contact.
Ensure adequate ventilation and that unobstructed fan inlets.
WARNING
LABORATORY USE ONLY
This device has not been approved by any agency or approvals
body for Electrical Safety, Electromagnetic Compatibility, or
Telecommunications at the time of distribution. Research use only!
ATTENTION
OBSERVE ESD PRECAUTIONS
This device contains electrostatically sensitive components: it
may be damaged by static discharges. Observe ESD precautions &
proper grounding when handling, installing, or removing device.
ATTENTION
RF TRANSMITTER
This device is capable of RF transmission on bands or frequencies
subject to regulatory oversight. Operators are responsible to ensure
use of this device meets local regulatory and legal standards, as
they may apply to you and the band of interest.
This device is intended for test and measurement use only.

1
Specifications and Interfaces
Crimson TNG is a wide band, high gain, direct conversion quadrature transceiver1and signal
processing platform. Using analogue and digital conversion, it is capable of processing signal band-
widths up to 325MHz from approximately DC to 6.8GHz. Crimson TNG is compatible with GNU
Radio and includes source code for many of its drivers and peripherals.
Absolute Maximum Ratings
Stresses beyond those listed in the Absolute Ratings Table (Table 1.1) may cause permanent damage
to the device. These ratings are stress specifications only. Functional operation of the product at
these conditions is not implied. Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability and is, therefore, not recommended.
WARNING
EXCEEDING ABSOLUTE RATINGS MAY DAMAGE DEVICE AND
MAY CAUSE DANGEROUS FIRE OR ELECTRICAL HAZARDS
Exceeding these ratings may substantially damage device, and the
resulting hazards may cause serious personal injury or death.
Table 1.1: Absolute Ratings: Exposure or sustained operation at absolute ratings may permanently
damage Crimson TNG. Ensure fan inlets (located on both sides of the device) are not blocked during
operation.
Specifications Min Max Units Notes
Operating Temperature 5 40 C At fan inlet
Operating Humidity 5 100 % Non-Condensing
Storage Temperature 0 40 C
Storage Humidity 20 95 % Non-Condensing
Input RF Power 10 dBm Do not exceed.
IO and TRIG Voltage 2.6 V Do not exceed: Direct to FPGA.
External Reference 3 Vpp Do not exceed.
SMA Torque 0.6 0.7 Nm
1As Crimson TNG is capable of Digital Down/Up Conversion, superhet architectures can be implemented using
Digital Down/Up Conversion on the FPGA.
10

1. SPECIFICATIONS AND INTERFACES 11
Observed Performance
Crimson TNG is a very flexible radio and signal processing platform that supports high bandwidth
communications over a wide tuning range. The hardware and signal processing capabilities may be
configured to support a very wide variety of applications, each with their own figures of merit. It
is, therefore, fairly challenging to provide uniform performance specifications across those different
configurations.
To provide a general idea of what this product is capable of, Table 1.2 on the next page lists some
conservative figures of its out-of-box performance. Configuration of the product towards a specific
application may see some of these figures exceed at the expense of others. For more information,
please do not hesitate to contact us at: [e-mail].

1. SPECIFICATIONS AND INTERFACES 12
Table 1.2: Observed Performance. These specifications reference observations taken during internal
use and development. Calibration Measurements relative to 20˚C
Specification Min Nom Max Units
Common Radio RF Stage (ADF4355) 110 6800 MHz
Baseband Stage 0.1 140 MHz
Dynamic Range 25 70 dB
SFDR 65 dB
Receive Radio RF Input Power -40 dBm
Noise Figure, Rx RF St 3.1 7 dB
Power Gain Low 15 45 dB
High -10 65 dB
Group Delay (Radio Chain)1Low 13.7 ns
High 20 ns
ADC Independent Channels 4 -
(Receive Converter) ADC resolution 16 bits
ADC Sample Rate 325 325 MSPS
Rx Sampling Bandwidth 325 MHz
Latency (input to serial)150 ns
Receive DSP and FPGA Decimation ( fs
n) 1 256 -
Specifications Latency (FPGA DSP)150 500 750 ns
(Default firmware)
Transmit Radio Transmit Power Low -30 18 dBm
High -10 15 dBm
Group Delay (radio chain)1Low 5 ns
High 11 ns
DAC Tx Output Bandwidth 325 MHz
(Transmit Converter) DAC resolution 16 bits
DAC Sample Rate 325 MSPS
Latency (serial to output)150 655 804 ns
Transmit DSP and FPGA Interpolation (n·fs) 1 256 -
Specifications Latency (FPGA DSP)196 160 ns
Digital FPGA - Arria V ST SOC 5ASTMD3E3F31 -
On Board Processor Core ARM Cortex-A9 MP
LPDDR2 RAM 4 Gb
NAND Flash (x8) 4 Gb
Networking 10GBASE-R, Full Duplex2each 10 Gbps
Default IP, SFP+ Port A 10.10.10.2 -
Default IP, SFP+ Port B 10.10.11.2 -
Int. Reference (10MHz) Frequency Stability -5 5 ppb
Ext. Reference (10MHz) Input Voltage Swing 2.2 2.4 3 Vpp
IO, PPS, and TRIG FPGA IO Voltage Range 0 2.5 2.6 V
1For additional information on latency, please refer to the Latency section on page 24.
2For additional information on bandwidth and sample rate, Bandwidth section on page 24.

1. SPECIFICATIONS AND INTERFACES 13
External Interfaces
Crimson TNG has a number of user accessible interfaces through which the device can connect
to external sources and sinks. Management functions are carried out over a web page hosted by
the Crimson TNG transceiver and accessible using the Management Ethernet port on the front
face of the device. Data is sent over the 10Gbps SFP+ ports and receive and transmit antennas
connect to the SMA connectors on the front of the device. Other peripherals ports provide access
or the capability to improve functionality.
10/100 Management Port This connects to a Linux system running on the Hard Processing Sys-
tem located on the FPGA silicon, and provides a unified interface by
which to control and configure the remaining devices.
10GBASE-R SFP+ There are two SFP+ ports on the front panel of the device that use
10GBASE-R encoding to directly communicate with an optical module
and interface with a ten gigabit network. These ports directly inter-
face with the FPGA fabric and support high bandwidth, low latency
communication between the ADCs and DACs.2
50Ω SMA There are sixteen standard SMA headers. These are used to connect
to external antennas, sinks, or sources, including:
Rx (x4) The four independent receive channels may be connected
to external sources or antennas
Tx (x4) The four independent transmit channels may be connected
to external antennas or sinks
Ext. Osc For the most demanding applications, an external oscillator
may be used to drive the LMK04828 outputs. This implies
a completely external synchronization solution
Ext. PLL A reference clock for local oscillator generation for the fre-
quency synthesizers for receive and transmit PCBs
Ext. Sys The system reference clock for converter devices and the
FPGA; only present when a sysref command is issued
Ext. Dev An external 322.265625MHz clock directly to the converter
devices as well as the FPGA
Ext. Ref An external 10MHz reference may be applied to this port
in lieu of the default, internal, 10MHz reference
Ref. Out Crimson TNG may output its internal reference clock to
other systems.
PPS This port can be used to synchronize internal time keeping
(note: this will be enabled in future releases)
TRIG This port can be used as a trigger (note: this will be enabled
in future releases)
USB 2.0 A USB port connects to the Linux system running on the Hard Pro-
cessor System.
2Please note, not all 10Gbps NICs support 10GBASE-R protocols - it is important that you ensure the card you
select supports communication using 10GBASE-R. If you have questions about this, please do not hesitate to contact
us.

1. SPECIFICATIONS AND INTERFACES 14
Micro-SD Slot The FPGA and Hard Processor System may be rebooted or configured
using an external Micro-SD card.
Industrial Mini I/O GPIO connects to the FPGA
IEC320 C14 Power A standard «computer» cable plugs into this connector to power the
unit. The power supply accepts 120V or 240V.
Operating System
Although Crimson TNG may be used with any operating system, we strongly recommend using
a Linux operating system. This ensures you will be able to take advantage of a very large body
of high performance that exists to support high performance computing applications, while also
providing a more comprehensive development environment. It will also users to more easily use our
existing example code, it’s best to set up the GnuRadio and UHD applications.
After connecting the Crimson TNG Transceiver to an external network or computer using its ded-
icated Ethernet management port, you may configure the device using the provided web interface.
It is also possible to SSH into the small Linux distribution running on the on-board processor.
Network Interface Card (NIC) Requirements
Crimson TNG uses a 10-gigabit Ethernet connection to quickly send and receive data. The
Crimson TNG uses a 10GBASE-SR3PHY that interfaces with each SFP+ port using a single,
10.3125Gbps serial lane and a scrambled 64B/66B coding scheme. It is very important to ensure
that network devices or interfaces intended to be used to connect to Crimson TNG support
10GBASE-SR.
If you have any questions or concerns about NIC card requirements, please do not hesitate to
contact us.
Optical Fibre Requirements
Crimson TNG requires active optical cabling: using passive, direct connect, SFP+ cables is
not supported. Our product ships with high quality, direct attach, SFP+ active optical cabling
(AOC) that uses OM-1 type optical fibre. Alternatively, you may also choose to use a compatible
10GBASE-R SFP+ optical transceiver module, along with fibre cable. We suggest using Optical
Multimode (OM) grade fibre (ie. OM1, OM2, OM3, or OM4). In a production environment, or
when integrating the product into existing infrastructure, you may use legacy FDDI grade fibre for
short runs, though we advise testing worst-case performance across the longest run prior to wide
scale deployment.
If you have any questions or concerns about optical fibre requirements, please do not hesitate to
contact us.
Mechanical
Crimson TNG conforms to a 1U form factor and 19-inch+ rack. A mechanical diagram is included
in Chapter 10.
3There is a significant difference between a 10GBASE-X interface (4 serial lanes specified to 3.125Gbps using
8b/10b coding), and the 10GBASE-R interface (1 serial lane specified to 10.3125Gbps using 64b/66b coding) that
Crimson TNG uses. Although both standards may expose the same mechanical SFP+ interface (and thereby
allowing you to mechanically connect the two interfaces) the standards are fundamentally incompatible. Connecting
Crimson TNG (10GBASE-R) to a network card that only supports 10GBASE-X or 10GBASE-T will not work.

1. SPECIFICATIONS AND INTERFACES 15
RF Chain
Simulated RF chain performance (based on component specifications) yield the simulated perfor-
mance indicated in Table 1.3. As both the receive and transmission chains use variable stages,
the figures were calculated using midpoint references for attenuation and gain stages. With proper
tuning and calibration, you should expect better values. More information on the specific RF chain
used may be found in the System Architecture Chapter 2 on the following page.
Table 1.3: These specifications are intended to serve as a broad guide, with variable gain and at-
tenuation stages set at midpoints. As variable stages are adjusted, performance generally improves.
Specification Value Units
Input Parameters Input Power -55 dBm
Frequency 2000 MHz
Analysis B/W 150 MHz
Rx Chain Analysis lna lna+pa
NF 4.8 3.1 dB
SFDR 55 47 dB
IMD -113 -81 dB
IIP3 -1.3 -17 dBm
SNR 32 33 dB
Rx Sensitivity -86 -87 dBm
Input P1dB -28 -44 dBm
Tx Chain Analysis Power Gain -20 – 5 dBm
SFDR 40 – 70 dB

2
System Architecture
Overview
Crimson TNG uses a highly modular design consisting of five boards. Each board is connected
using shielded, high speed cabling to support its operation (Figure 2.1). The power board provides
power to the digital, time, receive (Rx), and transmit (Tx) boards. The digital board provides an
interface to control, configure, and send/receive data to/from the receive (Rx), transmit (Tx), and
time boards. Clock distribution extends from the Time board, which provides a very clean and
stable clock distribution network. The default receive and transmit boards each comprise of four
fully independent channels.
FPGA
HPS
HPS - FPGA
B r idge
AR R IA V
DIGITAL
POWER
RESET
Rx A
MCU
ADC A
ADC B
ADC C
ADC D
RFE A
RFE B
RFE C
RFE D
RECEIVE (RX)
Rx B
Rx C
Rx D
MCU
DAC A
DAC C
RFE A
RFE B
RFE C
RFE D
TRANSMIT (TX)
Tx A
Tx B
Tx C
Tx D
SFP+A
SFP+B
TIME
RESET
SYSREF
DEVCLK
PLL
OSCOUT
REFOUT
REFCLK
10GBASER
10GBASER
10/100 ETHERNET
MGMT
TX
RX
TIME
DIGITAL
(RxA, RxC, TxA, TxC)
(RxB, RxD, TxB, TxD)
Figure 2.1: Overall system block diagram.
16

2. SYSTEM ARCHITECTURE 17
Power Distribution
Crimson TNG is powered by an internal 12V, 200W, over current protected, DC power supply
plugged into a standard IEC320 C13 120-240VAC computer power cable at the rear of the unit.
The power board distributes power to the four daughter boards as shown in Figure 2.2.
Power
Debug &
Programming
5.5V
3.6V
Prog.
Debug &
Programming
5.5V
3.6V
Prog.
Debug &
Programming
5.5V
3.6V
Prog.
Debug &
Programming
5.5V
3.6V
Prog.
Time TX RX Spare
5.5V Spare
5.5V Digital
12V, 200W
DC Power Supply
IEC 320 C14
120-240V
Figure 2.2: Power board system block diagram
Digital board
The Crimson TNG digital board provides the digital processing that powers the Crimson TNG
transceiver. It consists of an Altera Arria V ST SOC FPGA, which includes an ARM Cortex-A9
processor on the FPGA (Figure 2.3 on the next page). The ARM (HPS) portion of the board hosts
the web server through which Crimson TNG can be configured, and a UART serial port, which is
used to communicate with the Rx, Tx, and time modules. A separate high speed link allows serial
data to be shared directly between the Rx and Tx boards and the FPGA fabric. This link also
allows the data to be shared between the FPGA fabric and the 10Gbps interface (accessed using
the SFP+ ports on the front of the device). Other peripherals, including USB devices, are accessed
through the HPS portion of the FPGA.

2. SYSTEM ARCHITECTURE 18
SFP+A
SFP+B
10GBASER
10GBASER
ADC A
ADC B
ADC C
ADC D
DAC A
DAC C
TX
RX
TIME
DAC A
DAC C
10/100 ETHERNET
MGMT
FPGA
HPS
FIFO DSP JESD 204B
FIFO DSP JESD 204B
FIFO DSP JESD 204B
FIFO DSP JESD 204B
FIFO DSP JESD 204B
FIFO DSP JESD 204B
FIFO DSP JESD 204B
FIFO DSP JESD 204B
10G BASER
PHY
10G BASER
PHY
Rx A
Rx B
Rx C
Rx D
Tx A
Tx B
Tx C
Tx D
SERVER UART
USB
HPS - FPGA
Bridge
ARRIA V ST SoC
RESET POWER
Figure 2.3: Digital board system block diagram.
Time Board
Clock distribution on the Crimson TNG transceiver is fairly robust. The internal reference source
is an oven-controlled crystal oscillator (OCXO) that provides a very stable (5ppb) and accurate
10MHz signal and may be tuned using the AD5624R nanoDAC. A single ended external reference
clock may also be used, provided it meets the input swing requirements listed on the specifications
page1.
For RTM5 units (Figure 2.5), the default clock configuration sees the 10MHz reference input fre-
quency divided by two, and passed to the CDCLVP1204 2:1 clock buffer, where it is distributed to
the LMK low jitter integrated PLL+VCO synthesizers. One of the buffered outputs is also accessi-
ble using the “Ref Out” port. Note that the default configuration uses an internal 5MHz signal to
support the default 325MHz sample rate, and to support phase coherent operation.
For RTM4 devices (and Figure 2.4), the CDCLVP1204 2:1 clock buffer selects either the internal or
external references and provides two outputs. The secondary output is a buffered reference output
(see Ref. Out on front panel of transceiver). The primary output (which originates from either the
internal or external reference, depending on the configuration) goes to the HMC988. The HMC988
provides additional dividers (disabled by default) and phase shift/group delay capabilities. After
the HMC988, the output goes to the first LMK04828 low jitter clock generator.
The LMK04828, by default, has a 10MHz input and uses the internal Phase Locked Loop (PLL1)to
control a 100MHz low phase-noise VCXO. This locks the ultra low phase-noise 100MHz VCXO to
the stability provided by the 10MHz input. The 100MHz VCXO output subsequently drives PLL2
of the first LMK04828. This provides a 322 MHz JESD204B (subclass 1) device clock and sysref
clock to the converters and transceivers (ADC, DAC, and FPGA).
1The default external reference frequency should be 10 MHz, but it is possible to use an unless using custom
dividers/logic (the hardware supports various external reference frequencies, but this is not exposed to the user).

2. SYSTEM ARCHITECTURE 19
A buffered copy of the 100MHZ VCXO output is also provided to a second LMK04828, through
a second HMC 988. The buffered output drives the second PLL of the second LMK04828 and
provides clocking to all frequency synthesizers for each front end channel. A buffered output of
the analog reference signal is also provided (Ext.PLL) and a buffered copy of the original 100MHz
reference signal is available on Ext. OSCout.
The default configuration has been factory calibrated to provide a known (in-phase), deterministic
relationship for all LMK04828 outputs. The Leading edge of all outputs and internal VCOs have
been synchronized at the reference inputs of all frequency synthesizers, converters, and transceivers.
CDCLVP1204
AOCJY-10.000MHz
Vtune
ΔtRX ADC
ΔtTX DAC
ΔtFPGA
Δt
ΔtExt. PLL
TX PLL
Δt
ΔtRX PLL
FPGA PLL
,÷N
Δt
HMC988
LMK04828
,÷N
Δt
HMC988
LMK04828
Ext. RefClk
Ref. Out
CVHD-950-100
Ext. SysRef
Δt
Ext. DevClk
Δt
AD5624R
nanoDAC
}
}
JESD204B
Class 1
CW Reference
to Frequency
Ext. OSCout
FPGA REF
Figure 2.4: RTM4 Time Board Architecture.
CDCLVP1204
AOCJY-10.000MHz
Vtune
ΔtRX ADC
ΔtTX DAC
ΔtFPGA
Ext. PLL
RX PLL
Ext. RefClk
Ref. Out
CVHD-950-100
Ext. SysRef
Δt
Ext. DevClk
Δt
AD5624R
nanoDAC
}
}
JESD204B
Subclass 1
LO
Reference
to Rx and Tx
Ext. OSCout
FPGA PLL
TX PLL
LMK04828
Δt
Δt
Δt
CVHD-950-100
LMK04821
Δt
FPGA REF
,÷N
Δt
HMC988
,÷N
Δt
HMC988
Figure 2.5: RTM5 Time Board Architecture.

2. SYSTEM ARCHITECTURE 20
Receive Board Radio Chain
The Crimson TNG receive board consists of a radio front end terminating with the Texas In-
struments dual channel ADC16DX370 analog-to-digital converter, as shown in Figure 2.6. This
architecture is duplicated four times, once for each channel.
PE43704
High Stage
Low Stage
I
Q
AG403-89G
ADL5380
BFP843
PMA3-83LN+
PE42920
Low Noise Amplifier
RF Gain
Variable
Attenuator
Frequency
Synthesizer
BB Gain
Gain Bypass
ADF4355
Low
Low
SMA
Input
IQ Down
Converter
LMH6521
ADC Driver
ADC16DX370
ADC
Altera Arria V ST
5ASTMD3E
FPGA + HPS
Anti Aliasing
Filter
Anti Aliasing
Filter
SKY13374-397LF
SKY13374-397LF SKY13374-397LF
Figure 2.6: Rx Board RF Channel
Transmit Board Radio Chain
The Crimson TNG transmit board consists of a radio front end originating with the Texas In-
struments quad channel DAC38J84 digital-to-analog converter, as shown in Figure 2.7. The radio
front end is duplicated four times. Channels A and B connect to one DAC, and channels C and D
connect to another DAC.
AI Filter
ADF4355
Frequency
Synthesizer
RF Gain
BB Gain
IQ Up
Converter
DAC
5ASTMD3E
FPGA + HPS
DAC38J84
TRF370417 PHA-1+ PHA-1+
PE43704 PHA-1+
AG403-89G
PE43704
High Stage
Low Stage
I
Q
I
Q
SMA
Output
Altera Arria V ST
PE42920 SKY13374-397LF
RF Gain Variable
Attenuator
Variable
Attenuator
BB Gain
Figure 2.7: Tx Board RF Channel