Philips Sc28l91 Operational manual





SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

Product data sheet

Supersedes data of 2000 Sep 22 2004 Oct 21

INTEGRATED CIRCUITS

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2

2004 Oct 21

DESCRIPTION

The SC28L91 is a new member of the IMPACT family of Serial

Communications Controllers. It is a single channel UART operating

at 3.3 V and 5.0 V VCC, 8 or 16 byte FIFOs and is quite compatible

with software of the SC28L92 and previous UARTs offered by

Philips. It is a new part that is similar to our previous one channel

part but is vastly improved. The improvements being: 16 character

receiver, 16 character transmit FIFOs, watch dog timer for the

receiver, mode register 0 is added, extended baud rate, over all

faster bus and data speeds, programmable receiver and transmitter

interrupts and versatile I/O structure. (The previous one channel

part, SCC2691, is NOT being discontinued.)

Pin programming will allow the device to operate with either the

Motorola or Intel bus interface. Bit 3 of the MR0 register allows the

device to operate in an 8-byte FIFO mode if strict compliance with

an 8-byte FIFO structure is required.

The Philips Semiconductors SC28L91 Universal Asynchronous

Receiver/Transmitter (UART) is a single-chip CMOS-LSI

communications device that provides a full-duplex asynchronous

receiver/transmitter channel in a single package. It interfaces

directly with microprocessors and may be used in a polled or

interrupt driven system with modem and DMA interface.

The operating mode and data format of the channel can be

programmed independently. Additionally, the receiver and

transmitter can select its operating speed as one of 28 fixed baud

rates; a 16X clock derived from a programmable counter/timer, or an

external 1X or 16X clock. The baud rate generator and counter/timer

can operate directly from a crystal or from external clock inputs. The

ability to independently program the operating speed of the receiver

and transmitter make the UART particularly attractive for dual-speed

channel applications such as clustered terminal systems.

The receiver and transmitter is buffered by 8 or 16 character FIFOs

to minimize the potential of receiver overrun, transmitter underrun

and to reduce interrupt overhead in interrupt driven systems. In

addition, a flow control capability is provided via RTS/CTS signaling

to disable a remote transmitter when the receiver buffer is full.

DMA interface is and other general purpose signals are provided on

the SC28L91 via a multipurpose 7-bit input port and a multipurpose

8-bit output port. These can be used as general-purpose ports or

can be assigned specific functions (such as clock inputs or

status/interrupt outputs, FIFO conditions) under program control.

The SC28L91 is available in two package versions: a 44-pin PLCC

and 44-pin plastic quad flat pack (PQFP).

FEATURES

•Member of IMPACT family: 3.3 to 5.0 volt , –40°C to +85°C and

68K for 80xxx bus interface for all devices.

•A full-duplex independent asynchronous receiver/transmitter

•16 character FIFOs for each receiver and transmitter

•Pin programming selects 68K or 80xxx-bus interface

•Programmable data format

–5 to 8 data bits plus parity

–Odd, even, no parity or force parity

–– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments

•16-bit programmable Counter/Timer

•Programmable baud rate for each receiver and transmitter

selectable from:

–28 fixed rates: 50 to 230.4 k baud

–Other baud rates to 1 MHz at 16X

–Programmable user-defined rates derived from a programmable

counter/timer

–External 1X or 16X clock

•Parity, framing, and overrun error detection

•False start bit detection

•Line break detection and generation

•Programmable channel mode

–Normal (full-duplex)

–Automatic echo

–Local loop back

–Remote loop back

–Multi-drop mode (also called ‘wake-up’ or ‘9-bit’)

•Multi-function 7-bit input port (includes IACKN)

–Can serve as clock or control inputs

–Change of state detection on four inputs

–Inputs have typically >100 kΩpull-up resistors

–Change of state detectors for modem control

•Multi-function 8-bit output port

–Individual bit set/reset capability

–Outputs can be programmed to be status/interrupt signals

–FIFO status for DMA interface

•Versatile interrupt system

–Single interrupt output with eight maskable interrupting

conditions

–Output port can be configured to provide a total of up to six

separate interrupt outputs that may be wire ORed.

–Each FIFO can be programmed for four different interrupt levels

–Watchdog timer for the receiver

•Maximum data transfer rates:

1X – 1 Mbit/s, 16X – 1 Mbit/s

•Automatic wake-up mode for multi-drop applications

•Start-end break interrupt/status with mid-character break detect.

•On-chip crystal oscillator

•Power-down mode

•Receiver time-out mode

•Single +3.3 V or +5 V power supply

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 3

ORDERING INORMATION

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Industrial

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

VCC = +3.3 V ±10 %, +5 V ±10 %

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description

ÁÁÁÁÁÁÁÁÁÁÁ

Tamb = –40 °C to +85 °C

ÁÁÁÁÁÁÁÁÁÁÁ

Drawing Number

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

44-Pin Plastic Leaded Chip Carrier (PLCC)

ÁÁÁÁÁÁÁÁÁÁÁ

SC28L91A1A

ÁÁÁÁÁÁÁÁÁÁÁ

SOT187-2

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

44-Pin Plastic Quad Flat Pack (PQFP)

ÁÁÁÁÁÁÁÁÁÁÁ

SC28L91A1B

ÁÁÁÁÁÁÁÁÁÁÁ

SOT307-2

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 4

PIN CONFIGURATION DIAGRAM

80XXX PIN CONFIGURATION

Pin Function

1A3

2 IP0

3 WRN

4 RDN

5V

CC

6 No Connection

7 OP1

8 OP3

9 OP5

10 OP7

11 I/M

12 D1

13 D3

14 D5

15 D7

Pin Function

16 GND

17 GND

18 INTRN

19 D6

20 D4

21 D2

22 D0

23 NC

24 OP6

25 OP4

26 OP2

27 OP0

28 TxDA

29 RxDA

30 x1/clk

Pin Function

31 x2

32 RESET

33 CEN

34 IP2

35 IP6

36 IP5

37 IP4

38 VCC

39 VCC

40 A0

41 IP3

42 A1

43 IP1

44 A2

PQFP

44 34

1

11

33

23

12 22

SD00698

1

39

17

28

40

29

18

7

PLCC

6

SD00699

Pin Function

1NC

2A0

3 IP3

4A1

5 IP1

6A2

7A3

8 IP0

9 WRN

10 RDN

11 VCC

12 I/M

13 No Connection

14 OP1

15 OP3

Pin Function

16 OP5

17 OP7

18 D1

19 D3

20 D5

21 D7

22 VSS

23 NC

24 INTRN

25 D6

26 D4

27 D2

28 D0

29 OP6

30 OP4

Pin Function

31 OP2

32 OP0

33 TxDA

34 NC

35 RxDA

36 X1/CLK

37 X2

38 RESET

39 CEN

40 IP2

41 IP6

42 IP5

43 IP4

44 VCC

Note: Pins marked “No Connection” must NOT be connected.

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 5

PIN CONFIGURATION DIAGRAM

68XXX PIN CONFIGURATION

Pin Function

1A3

2 IP0

3 R/WN

4 DACKN

5V

CC

6 No Connection

7 OP1

8 OP3

9 OP5

10 OP7

11 I/M

12 D1

13 D3

14 D5

15 D7

Pin Function

16 GND

17 GND

18 INTRN

19 D6

20 D4

21 D2

22 D0

23 NC

24 OP6

25 OP4

26 OP2

27 OP0

28 TxDA

29 RxDA

30 x1/clk

Pin Function

31 x2

32 RESETN

33 CEN

34 IP2

35 IACKN

36 IP5

37 IP4

38 VCC

39 VCC

40 A0

41 IP3

42 A1

43 IP1

44 A2

PQFP

44 34

1

11

33

23

12 22

SD00700

1

39

17

28

40

29

18

7

PLCC

6

SD00701

Pin Function

1NC

2A0

3 IP3

4A1

5 IP1

6A2

7A3

8 IP0

9 R/WN

10 DACKN

11 VCC

12 I/M

13 No Connection

14 OP1

15 OP3

Pin Function

16 OP5

17 OP7

18 D1

19 D3

20 D5

21 D7

22 VSS

23 NC

24 INTRN

25 D6

26 D4

27 D2

28 D0

29 OP6

30 OP4

Pin Function

31 OP2

32 OP0

33 TxDA

34 NC

35 RxDA

36 X1/CLK

37 X2

38 RESETN

39 CEN

40 IP2

41 IACKN

42 IP5

43 IP4

44 VCC

Note: Pins marked “No Connection” must NOT be connected.

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 6

8

D0–D7

RDN

WRN

CEN

A0–A3

RESET

INTRN

X1/CLK

X2

4

BUS BUFFER

OPERATION CONTROL

ADDRESS

DECODE

R/W CONTROL

INTERRUPT CONTROL

IMR

ISR

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

COUNTER/

TIMER

XTAL OSC

CSR

ACR

CTL

DATA CHANNEL

16 BYTE TRANSMIT

FIFO

TRANSMIT

SHIFT REGISTER

16 BYTE RECEIVE

FIFO

MRA0, 1, 2

CRA

SRA

INPUT PORT

CHANGE OF

STATE

DETECTORS (4)

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPCR

TxDA

RxDA

IP0-IP6

OP0-OP7

VCC

VSS

CONTROL

TIMING

INTERNAL DATABUS

IPCR

ACR

OPR

CTU

8

7

WATCH DOG TIMER

RECEIVE SHIFT

REGISTER

SD00702

GP

Figure 1. Block Diagram (80XXX mode)

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 7

8

D0–D7

R/WN

CEN

A0–A3

RESETN

INTRN

X1/CLK

X2

4

BUS BUFFER

OPERATION CONTROL

ADDRESS

DECODE

R/W CONTROL

INTERRUPT CONTROL

IMR

ISR

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

COUNTER/

TIMER

XTAL OSC

CSR

ACR

CTL

DATA CHANNEL

16 BYTE TRANSMIT

FIFO

TRANSMIT

SHIFT REGISTER

16 BYTE RECEIVE

FIFO

MRA0, 1, 2

CRA

SRA

INPUT PORT

CHANGE OF

STATE

DETECTORS (4)

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPCR

TxDA

RxDA

IP0-IP5

OP0-OP7

VCC

VSS

CONTROL

TIMING

INTERNAL DATABUS

IPCR

ACR

OPR

CTU

8

6

WATCH DOG TIMER

RECEIVE SHIFT

REGISTER

SD00703

IVR

DACKN

IACKN

Figure 2. Block Diagram (68XXX mode)

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 8

PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL)

Symbol Pin

type Name and function

I/M IBus Configuration: When high or not connected configures the bus interface to the Conditions shown in this table.

D0–D7 I/O Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the

CPU. D0 is the least significant bit.

CEN IChip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on

D0–D7 as controlled by the WRN, RDN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condi-

tion.

WRN IWrite Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed register. The

transfer occurs on the rising edge of the signal.

RDN IRead Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be presented on the

data bus. The read cycle begins on the falling edge of RDN.

A0–A3 IAddress Inputs: Select the UART internal registers and ports for read/write operations.

RESET IReset: A High level clears internal registers (SR, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state, stops the

counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets MR point-

er to MR1. See Figure 4

INTRN OInterrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable in-

terrupting conditions are true. This pin requires a pull-up device.

X1/CLK ICrystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a

crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).

X2 OCrystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin

to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.

RxD IReceiver Serial Data Input: The least significant bit is received first. “Mark” is High; “space” is Low.

TxD OTransmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the “mark” condition

when the transmitter is disabled, idle or operating in local loop back mode. “Mark” is High; “space” is Low.

OP0 OOutput 0: General-purpose output or request to send (RTSN, active-Low). Can be deactivated automatically on re-

ceive or transmit.

OP1 OOutput 1: General-purpose output.

OP2 OOutput 2: General-purpose output, or transmitter 1X or 16X clock output, or receiver 1X clock output.

OP3 OOutput 3: General-purpose output.

OP4 OOutput 4: General-purpose output or open-drain, active-Low, Rx interrupt ISR[1] output. DMA Control

OP5 OOutput 5: General-purpose output

OP6 OOutput 6: General-purpose output or open-drain, active-Low, Tx interrupt ISR[0] output. DMA Control

OP7 OOutput 7: General-purpose output.

IP0 IInput 0: General-purpose input or clear to send active-Low input (CTSN). Has Change of State Dector.

IP1 IInput 1: General-purpose input. Has Change of State Dector.

IP2 I Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector.

IP3 IInput 3: General-purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-

mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.

IP4 IInput 4: General-purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,

the received data is sampled on the rising edge of the clock.

IP5 IInput 5: General-purpose input

IP6 IInput 6: General-purpose input

VCC Pwr Power Supply: +3.3 V or +5 V supply input ±10 %

GND Pwr Ground

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 9

PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA)

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Symbol

ÁÁÁ

Á

ÁÁÁ

type

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Name and function

ÁÁÁÁ

I/M

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bus Configuration: When low configures the bus interface to the Conditions shown in this table.

ÁÁÁÁ

D0–D7

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the

CPU. D0 is the least significant bit.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

CEN

ÁÁÁ

Á

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on

D0–D7 as controlled by the R/WN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condition.

ÁÁÁÁ

R/WN

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read/Write: Input Signal. When CEN is low R/WN high input indicates a read cycle; when low indicates a write cycle.

ÁÁÁÁ

IACKN

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Acknowledge: Active low input indicating an interrupt acknowledge cycle. Usually asserted by the CPU in

response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

DACKN

ÁÁÁ

Á

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data Transfer Acknowledge: A3-State active-low output asserted in a write, read, or interrupt acknowledge cycle to

indicate proper transfer of data between the CPU and the UART.

ÁÁÁÁ

A0–A3

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Inputs: Select the UART internal registers and ports for read/write operations.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

RESETN

ÁÁÁ

Á

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset: A low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state,

stops the counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets

MR pointer to MR1. See Figure 4

ÁÁÁÁ

INTRN

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable

interrupting conditions are true. This pin requires a pullup.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

X1/CLK

ÁÁÁ

Á

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When

a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).

ÁÁÁÁ

X2

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this

pin to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.

ÁÁÁÁ

RxD

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

TxD

ÁÁÁ

Á

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’ condition

when the transmitter is disabled, idle, or when operating in local loop back mode. ‘Mark’ is High; ‘space’ is Low.

ÁÁÁÁ

OP0

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 0: General purpose output or request to send (RTSAN, active-Low). Can be deactivated automatically on

receive or transmit.

ÁÁÁÁ

OP1

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 1: General-purpose output.

ÁÁÁÁ

OP2

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 2: General purpose output or transmitter 1X or 16X clock output, or receiver 1X clock output.

ÁÁÁÁ

OP3

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 3: General purpose output.

ÁÁÁÁ

OP4

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 4: General purpose output or open-drain, active-Low, RxA interrupt ISR [1] output. DMA Control

ÁÁÁÁ

OP5

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 5: General-purpose output.

ÁÁÁÁ

OP6

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 6: General purpose output or open-drain, active-Low, TxA interrupt ISR[0] output. DMA Control

ÁÁÁÁ

OP7

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 7: General-purpose output.

ÁÁÁÁ

IP0

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 0: General purpose input or clear to send active-Low input (CTSAN). Has Change of State Dector.

ÁÁÁÁ

IP1

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 1: General purpose input. Has Change of State Dector.

ÁÁÁÁ

IP2

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector.

ÁÁÁÁ

IP3

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 3: General purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-

mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

IP4

ÁÁÁ

Á

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 4: General purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,

the received data is sampled on the rising edge of the clock.

ÁÁÁÁ

IP5

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 5: General purpose input.

ÁÁÁÁ

VCC

ÁÁÁ

Pwr

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power Supply: +3.3 or +5V supply input ±10%

ÁÁÁÁ

GND

ÁÁÁ

Pwr

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ground

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 10

ABSOLUTE MAXIMUM RATINGS1

Symbol Parameter Rating Unit

Tamb Operating ambient temperature range2Note 4 °C

Tstg Storage temperature range –65 to +150 °C

VCC Voltage from VCC to GND3–0.5 to +7.0 V

VSVoltage from any pin to GND3–0.5 to VCC +0.5 V

PDPackage power dissipation (PLCC44) 2.4 W

PDPackage power dissipation (PQFP44) 1.78 W

Derating factor above 25 °C (PLCC44) 19 mW/°C

Derating factor above 25 °C (PQFP44) 14 mW/°C

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not

implied.

2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.

3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Parameters are valid over specified temperature and voltage range.

DC ELECTRICAL CHARACTERISTICS1, 2, 3

VCC = 5 V ±10 %, Tamb = –40 °C to +85 °C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VIL Input low voltage 0.8 V

VIH Input high voltage (except X1/CLK) 2.4 1.5 V

VIH Input high voltage (X1/CLK) 0.8VCC 2.4 V

VOL Output low voltage IOL = 2.4 mA 0.2 0.4 V

VOH Output high voltage (except OD outputs)4IOH = –400 µAVCC – 0.5 V

IIX1PD X1/CLK input current - power down VIN = 0 V to VCC 0.5 0.05 0.5 µA

IILX1 X1/CLK input low current - operating VIN = 0 V –130 0µA

IIHX1 X1/CLK input high current - operating VIN = VCC 0 130 µA

Input leakage current:

IIAll except input port pins VIN = 0 V to VCC –0.5 0.05 +0.5 µA

Input port pins5VIN = 0 V to VCC –8 0.05 +0.5 µA

IOZH Output off current high, 3-State data bus VIN = VCC 0.5 µA

IOZL Output off current low, 3-State data bus VIN = 0 V –0.5 µA

IODL Open-drain output low current in off-state VIN = 0 V –0.5 µA

IODH Open-drain output high current in off-state VIN = VCC 0.5 µA

Power supply current6

ICC Operating mode CMOS input levels 7 25 mA

Power down mode CMOS input levels ≤1 5 mA

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of

5 ns maximum. For X1/CLK, this swing is between 0.4 V and 0.8VCC. All time measurements are referenced at input voltages of 0.8 V and

2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.

3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: CL= 125 pF, except open drain outputs. Test conditions for open drain outputs: CL= 125 pF,

constant current source = 2.6 mA.

5. Input port pins have active pull-up transistors that will source a typical 2 µA from VCC when the input pins are at VSS.

Input port pins at VCC source 0.0 µA.

6. All outputs are disconnected. Inputs are switching between CMOS levels of VCC – 0.2 V and VSS + 0.2 V.

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 11

DC ELECTRICAL CHARACTERISTICS1, 2, 3

VCC = 3.3 V ±10 %, Tamb = –40 °C to +85 °C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VIL Input low voltage 0.65 0.2*VCC V

VIH Input high voltage 0.8*VCC 1.7 V

VOL Output low voltage IOL = 2.4 mA 0.2 0.4 V

VOH Output high voltage (except OD outputs)4IOH = –400 µAVCC – 0.5 VCC – 0.2 V

IIX1PD X1/CLK input current - power down VIN = 0 V to VCC –0.5 0.05 +0.5 µA

IILX1 X1/CLK input low current - operating VIN = 0 V –80 0µA

IIHX1 X1/CLK input high current - operating VIN = VCC 0 80 µA

Input leakage current:

IIAll except input port pins VIN = 0 V to VCC –0.5 0.05 +0.5 µA

Input port pins5VIN = 0 V to VCC –8 0.5 +0.5 µA

IOZH Output off current high, 3-State data bus VIN = VCC 0.5 µA

IOZL Output off current low, 3-State data bus VIN = 0 V –0.5 µA

IODL Open-drain output low current in off-state VIN = 0 V –0.5 µA

IODH Open-drain output high current in off-state VIN = VCC 0.5 µA

Power supply current6

ICC Operating mode CMOS input levels 5 mA

Power down mode CMOS input levels ≤1 5.0 mA

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of

5 ns maximum. For X1/CLK, this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8 V and

2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.

3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: CL= 125 pF, except open drain outputs. Test conditions for open drain outputs: CL= 125 pF,

constant current source = 2.6 mA.

5. Input port pins have active pull-up transistors that will source a typical 2 µA from VCC when the input pins are at VSS.

Input port pins at VCC source 0.0 µA.

6. All outputs are disconnected. Inputs are switching between CMOS levels of VCC – 0.2 V and VSS + 0.2 V.

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 12

AC CHARACTERISTICS (5 VOLT) 1, 2, 3, 4

VCC = 5.0 V ±10 %, Tamb = –40 °C to +85 °C, unless otherwise specified.

ÁÁÁÁ

Symbol

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Parameter

ÁÁÁ

Min

ÁÁÁ

Typ

ÁÁÁÁ

Max

ÁÁÁÁ

Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset Timing (See Figure 4)

ÁÁÁÁ

tRES

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset pulse width

ÁÁÁ

100

ÁÁÁ

18

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bus Timing5(See Figure 5)

ÁÁÁÁ

t*AS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A0–A3 setup time to RDN, WRN Low

ÁÁÁ

10

ÁÁÁ

6

ÁÁÁÁ

ns

ÁÁÁÁ

t*AH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A0–A3 hold time from RDN, WRN low

ÁÁÁ

20

ÁÁÁ

12

ÁÁÁÁ

ns

ÁÁÁÁ

t*CS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN setup time to RDN, WRN low

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*CH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN Hold time from RDN. WRN low

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*RW

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

WRN, RDN pulse width (Low time)

ÁÁÁ

15

ÁÁÁ

8

ÁÁÁÁ

ns

ÁÁÁÁ

t*DD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data valid after RDN low (125pF load. See Figure 3 for smaller loads.)

ÁÁÁ

40

ÁÁÁÁ

55

ÁÁÁÁ

ns

ÁÁÁÁ

t*DA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RDN low to data bus active6

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*DF

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data bus floating after RDN or CEN high

ÁÁÁ

ÁÁÁÁ

20

ÁÁÁÁ

ns

ÁÁÁÁ

t*DI

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RDN or CEN high to data bus invalid7

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*DS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data bus setup time before WRN or CEN high (write cycle)

ÁÁÁ

25

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*DH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data hold time after WRN high

ÁÁÁ

0

ÁÁÁ

–12

ÁÁÁÁ

ns

ÁÁÁÁ

t*RWD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High time between read and/or write cycles5, 7

ÁÁÁ

17

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port Timing5(See Figure 9)

ÁÁÁÁ

t*PS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port in setup time before RDN low (Read IP ports cycle)

ÁÁÁ

0

ÁÁÁ

–20

ÁÁÁÁ

ns

ÁÁÁÁ

t*PH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port in hold time after RDN high

ÁÁÁ

0

ÁÁÁ

–20

ÁÁÁÁ

ns

ÁÁÁÁ

t*PD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

OP port valid after WRN or CEN high (OPR write cycle)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Timing (See Figure 10)

ÁÁÁÁ

t*IR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

INTRN (or OP3–OP7 when used as interrupts) negated from:

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read RxFIFO (RxRDY/FFULL interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write TxFIFO (TxRDY interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset Command (delta break change interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Stop C/T command (Counter/timer interrupt

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read IPCR (delta input port change interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write IMR (Clear of change interrupt mask bit(s))

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Clock Timing (See Figure 11)

ÁÁÁÁ

t*CLK

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1/CLK high or low time

ÁÁÁ

30

ÁÁÁ

20

ÁÁÁÁ

ns

ÁÁÁÁ

f*CLK

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1/CLK frequency8(for higher speeds contact factory)

ÁÁÁ

0.1

ÁÁÁ

3.686

ÁÁÁÁ

8.0

ÁÁÁÁ

MHz

ÁÁÁÁ

f*CTC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

C/T Clk (IP2) high or low time (C/T external clock input)

ÁÁÁ

30

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

f*CTC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

C/T Clk (IP2) frequency8(for higher speeds contact factory)

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

8.0

ÁÁÁÁ

MHz

ÁÁÁÁ

t*RX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC high or low time (16X)

ÁÁÁ

30

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

f*RX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC Frequency (16X)(for higher speeds contact factory)

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

16

ÁÁÁÁ

MHz

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC Frequency (1x)8, 9

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

1

ÁÁÁÁ

MHz

ÁÁÁÁ

t*TX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC High or low time (16X)

ÁÁÁ

30

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

f*TX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC frequency (16X) (for higher speeds contact factory)

ÁÁÁ

ÁÁÁÁ

16

ÁÁÁÁ

MHz

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC frequency (1X)8, 9

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

1

ÁÁÁÁ

MHz

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmitter Timing, external clock (See Figure 12)

ÁÁÁÁ

t*TXD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxD output delay from TxC low (TxC input pin)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

t*TCS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output delay from TxC output pin low to TxD data output

ÁÁÁ

6

ÁÁÁÁ

30

ÁÁÁÁ

ns

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 13

ÁÁÁÁ

Unit

ÁÁÁÁ

Max

ÁÁÁ

Typ

ÁÁÁ

Min

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Parameter

ÁÁÁÁ

Symbol

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Timing, external clock (See Figure 13)

ÁÁÁÁ

t*RXS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data setup time to RxC high

ÁÁÁ

50

ÁÁÁ

40

ÁÁÁÁ

ns

ÁÁÁÁ

t*RXH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data hold time from RxC high

ÁÁÁ

50

ÁÁÁ

40

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

68000 or Motorola bus timing (See Figures 6, 7, 8)10

ÁÁÁÁ

tDCR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN Low (read cycle) from X1 High10

ÁÁÁ

15

ÁÁÁÁ

35

ÁÁÁÁ

ns

ÁÁÁÁ

tDCW

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN Low (write cycle) from X1 High

ÁÁÁ

15

ÁÁÁÁ

35

ÁÁÁÁ

ns

ÁÁÁÁ

tDAT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN High impedance from CEN or IACKN High

ÁÁÁ

8

ÁÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

tCSC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN or IACKN setup time to X1 High for minimum DACKN cycle

ÁÁÁ

16

ÁÁÁ

ÁÁÁÁ

ns

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of

5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8 V and

2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.

3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: CL= 125 pF,

constant current source = 2.6 mA.

4. Typical values are the average values at +25 °C and 5 V.

5. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and

WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.

6. Guaranteed by characterization of sample units.

7. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must

be negated for tRWD to guarantee that any status register changes are valid.

8. Minimum frequencies are not tested but are guaranteed by design.

9. Clocks for 1X mode should maintain a 60/40 duty cycle or better.

10.Minimum DACKN time is tDCR = tDSC + tDCR + two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used

while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be

written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the

bus cycle. DACKN low or CEN high completes the write cycle.

0 20 40 60 80 100 120 140 160 180 200 220 240

60

55

50

45

40

35

30

25

20

15

10

5

0

VCC = 3.3 V @ +25 °C

5.0 V @ +25 °C

pF

Tdd

(ns)

125 pF30 pF 230 pF

SD00684

12 pF 100 pF

NOTES:

Bus cycle times:

(80XXX mode): tDD + tRWD = 70 ns @ 5V, 40 ns @ 3.3 V + rise and fall time of control signals

(68XXX mode) = tCSC + tDAT + 1 cycle of the X1 clock @ 5 V + rise and fall time of control signals

Figure 3. Port Timing vs. Capacitive Loading at typical conditions

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 14

AC CHARACTERISTICS (3.3 VOLT) 1, 2, 3, 4

VCC = 3.3 V ±10 %, Tamb = –40 °C to +85 °C, unless otherwise specified.

ÁÁÁÁ

Symbol

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Parameter

ÁÁÁ

Min

ÁÁÁ

Typ

ÁÁÁÁ

Max

ÁÁÁÁ

Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset Timing (See Figure 4)

ÁÁÁÁ

tRES

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset pulse width

ÁÁÁ

100

ÁÁÁ

20

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bus Timing5(See Figure 5)

ÁÁÁÁ

t*AS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A0–A3 setup time to RDN, WRN Low

ÁÁÁ

10

ÁÁÁ

6

ÁÁÁÁ

ns

ÁÁÁÁ

t*AH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A0–A3 hold time from RDN, WRN low

ÁÁÁ

33

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*CS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN setup time to RDN, WRN low

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*CH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN Hold time from RDN. WRN low

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*RW

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

WRN, RDN pulse width (Low time)

ÁÁÁ

20

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

t*DD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data valid after RDN low (125pF load. See Figure 3 for smaller loads.)

ÁÁÁ

46

ÁÁÁÁ

75

ÁÁÁÁ

ns

ÁÁÁÁ

t*DA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RDN low to data bus active6

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*DF

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data bus floating after RDN or CEN high

ÁÁÁ

15

ÁÁÁÁ

20

ÁÁÁÁ

ns

ÁÁÁÁ

t*DI

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RDN or CEN high to data bus invalid7

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*DS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data bus setup time before WRN or CEN high (write cycle)

ÁÁÁ

43

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*DH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data hold time after WRN high

ÁÁÁ

0

ÁÁÁ

–15

ÁÁÁÁ

ns

ÁÁÁÁ

t*RWD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High time between read and/or write cycles5, 7

ÁÁÁ

27

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port Timing5(See Figure 9)

ÁÁÁÁ

t*PS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port in setup time before RDN low (Read IP ports cycle)

ÁÁÁ

0

ÁÁÁ

–20

ÁÁÁÁ

ns

ÁÁÁÁ

t*PH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port in hold time after RDN high

ÁÁÁ

0

ÁÁÁ

–20

ÁÁÁÁ

ns

ÁÁÁÁ

t*PD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

OP port valid after WRN or CEN high (OPR write cycle)

ÁÁÁ

50

ÁÁÁÁ

75

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Timing (See Figure 10)

ÁÁÁÁ

t*IR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

INTRN (or OP3–OP7 when used as interrupts) negated from:

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read RxFIFO (RxRDY/FFULL interrupt)

ÁÁÁ

40

ÁÁÁÁ

79

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write TxFIFO (TxRDY interrupt)

ÁÁÁ

40

ÁÁÁÁ

79

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset Command (delta break change interrupt)

ÁÁÁ

40

ÁÁÁÁ

79

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Stop C/T command (Counter/timer interrupt)

ÁÁÁ

40

ÁÁÁÁ

79

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read IPCR (delta input port change interrupt)

ÁÁÁ

40

ÁÁÁÁ

79

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write IMR (Clear of change interrupt mask bit(s))

ÁÁÁ

40

ÁÁÁÁ

79

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Clock Timing (See Figure 11)

ÁÁÁÁ

t*CLK

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1/CLK high or low time

ÁÁÁ

35

ÁÁÁ

25

ÁÁÁÁ

ns

ÁÁÁÁ

f*CLK

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1/CLK frequency8(for higher speeds contact factory)

ÁÁÁ

0.1

ÁÁÁ

3.686

ÁÁÁÁ

8

ÁÁÁÁ

MHz

ÁÁÁÁ

f*CTC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

C/T Clk (IP2) high or low time (C/T external clock input)

ÁÁÁ

30

ÁÁÁ

15

ÁÁÁÁ

ns

ÁÁÁÁ

f*CTC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

C/T Clk (IP2) frequency8(for higher speeds contact factory)

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

8

ÁÁÁÁ

MHz

ÁÁÁÁ

t*RX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC high or low time (16X)

ÁÁÁ

30

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

f*RX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC Frequency (16X) (for higher speeds contact factory)

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

16

ÁÁÁÁ

MHz

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC Frequency (1x)8, 9

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

1

ÁÁÁÁ

MHz

ÁÁÁÁ

t*TX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC High or low time (16X)

ÁÁÁ

30

ÁÁÁ

15

ÁÁÁÁ

ns

ÁÁÁÁ

f*TX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC frequency (16X) (for higher speeds contact factory)

ÁÁÁ

ÁÁÁÁ

16

ÁÁÁÁ

MHz

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC frequency (1X)8, 9

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

1

ÁÁÁÁ

MHz

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmitter Timing, external clock (See Figure 12)

ÁÁÁÁ

t*TXD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxD output delay from TxC low (TxC input pin)

ÁÁÁ

40

ÁÁÁÁ

78

ÁÁÁÁ

ns

ÁÁÁÁ

t*TCS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output delay from TxC output pin low to TxD data output

ÁÁÁ

8

ÁÁÁÁ

30

ÁÁÁÁ

ns

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 15

ÁÁÁÁ

Unit

ÁÁÁÁ

Max

ÁÁÁ

Typ

ÁÁÁ

Min

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Parameter

ÁÁÁÁ

Symbol

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Timing, external clock (See Figure 13)

ÁÁÁÁ

t*RXS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data setup time to RxC high

ÁÁÁ

50

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

t*RXH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data hold time from RxC high

ÁÁÁ

50

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

68000 or Motorola bus timing (See Figures 6, 7, 8)10

ÁÁÁÁ

tDCR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN Low (read cycle) from X1 High10

ÁÁÁ

18

ÁÁÁÁ

57

ÁÁÁÁ

ns

ÁÁÁÁ

tDCW

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN Low (write cycle) from X1 High

ÁÁÁ

18

ÁÁÁÁ

57

ÁÁÁÁ

ns

ÁÁÁÁ

tDAT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN High impedance from CEN or IACKN High

ÁÁÁ

10

ÁÁÁÁ

15

ÁÁÁÁ

ns

ÁÁÁÁ

tCSC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN or IACKN setup time to X1 High for minimum DACKN cycle

ÁÁÁ

30

ÁÁÁ

10

ÁÁÁÁ

ns

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of

5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8 V and

2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.

3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: CL= 125 pF,

constant current source = 2.6 mA.

4. Typical values are the average values at +25 °C and 3.3 V.

5. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and

WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.

6. Guaranteed by characterization of sample units.

7. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must

be negated for tRWD to guarantee that any status register changes are valid.

8. Minimum frequencies are not tested but are guaranteed by design.

9. Clocks for 1X mode should maintain a 60/40 duty cycle or better.

10.Minimum DACKN time is tDCR = tDSC + tDCR + two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used

while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be

written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the

bus cycle. DACKN low or CEN high completes the write cycle.

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 16

Block Diagram

The SC28L91 UART consists of the following seven major sections:

data bus buffer, operation control, interrupt control, timing, Rx and

Tx FIFO Buffers, input port and output port control. Refer to the

Block Diagram.

Data Bus Buffer

The data bus buffer provides the interface between the external and

internal data buses. It is controlled by the operation control block to

allow read and write operations to take place between the controlling

CPU and the UART.

Operation Control

The operation control logic receives operation commands from the

CPU and generates appropriate signals to internal sections to

control device operation. It contains address decoding and read and

write circuits to permit communications with the microprocessor via

the data bus.

Interrupt Control

A single active-Low interrupt output (INTRN) is provided which is

activated upon the occurrence of any of eight internal events.

Associated with the interrupt system are the Interrupt Mask Register

(IMR) and the Interrupt Status Register (ISR). The IMR can be

programmed to select only certain conditions to cause INTRN to be

asserted. The ISR can be read by the CPU to determine all currently

active interrupting conditions. Outputs OP3–OP7 can be

programmed to provide discrete interrupt outputs for the transmitter,

receiver, and counter/timer. Programming the OP3 to OP7 pins as

interrupts causes their output buffers to change to an open drain

active low configuration. The OP pins may be used for DMA and

modem control as well. (See output port notes).

FIFO Configuration

Each receiver and transmitter has a 16 byte FIFO. These FIFOs

may be configured to operate at a fill capacity of either 8 or 16 bytes.

This feature may be used if it is desired to operate the 28L91 in

close compliance to 26C92 software. The 8-byte/16-byte mode is

controlled by the MR0[3] bit. A 0 value for this bit sets the 8-bit mode

( the default); a 1 sets the 16-byte mode.

The FIFO fill interrupt level automatically follow the programming of

the MR0[3] bit. See Tables 3 and 4.

68XXX mode

When the I/M pin is connected to VSS (ground), the operation of the

SC28L91 switches to the bus interface compatible with the Motorola

bus interfaces. Several of the pins change their function as follows:

•IP6 becomes IACKN input

•RDN becomes DACKN

•WRN becomes R/WN

The interrupt vector is enabled and the interrupt vector will be placed

on the data bus when IACKN is asserted low. The interrupt vector

register is located at address 0xC. The contents of this register are

set to 0x0F on the application of RESETN.

The generation of DACKN uses two positive edges of the X1 clock

as the DACKN delay from the falling edge of CEN. If the CEN is

withdrawn before two edges of the X1 clock occur, the

generation of DACKN is terminated. Systems not strictly requiring

DACKN may use the 68XXX mode with the bus timing of the 80XXX

mode greatly decreasing the bus cycle time.

TIMING CIRCUITS

Crystal Clock

The timing block consists of a crystal oscillator, a baud rate

generator, a programmable 16-bit counter/timer, and four clock

selectors. The crystal oscillator operates directly from a crystal

connected across the X1/CLK and X2 inputs. If an external clock of

the appropriate frequency is available, it may be connected to

X1/CLK. The clock serves as the basic timing reference for the Baud

Rate Generator (BRG), the counter/timer, and other internal circuits.

A clock signal within the limits specified in the specifications section

of this data sheet must always be supplied to the UART. If an

external clock is used instead of a crystal, X1 should be driven using

a configuration similar to the one in Figure 11. X2 should be open or

driving a nominal gate load. Nominal crystal rate is 3.6864 MHz.

Rates up to 8 MHz may be used.

BRG

The baud rate generator operates from the oscillator or external

clock input and is capable of generating 28 commonly used data

communications baud rates ranging from 50 to 38.4 K baud.

Programming bit 0 of MR0 to a “1” gives additional baud rates of

57.6 kB, 115.2 kB and 230.4 kB (500 kHz with X1 at 8.0 MHz).

These will be in the 16X mode. A 3.6864 MHz crystal or external

clock must be used to get the standard baud rates. The clock

outputs from the BRG are at 16X the actual baud rate. The

counter/timer can be used as a timer to produce a 16X clock for any

other baud rate by counting down the crystal clock or an external

clock. The four clock selectors allow the independent selection, for

the receiver and transmitter, of any of these baud rates or external

timing signal.

Counter/Timer

The counter timer is a 16-bit programmable divider that operates in

one of three modes: counter, timer, and time out. In the timer mode it

generates a square wave. In the counter mode it generates a time

delay. In the time out mode it monitors the time between received

characters. The C/T uses the numbers loaded into the

Counter/Timer Lower Register (CTLR) and the Counter/Timer Upper

Register (CTUR) as its divisor.

The counter/timer clock source and mode of operation (counter or

timer) is selected by the Auxiliary Control Register bits 6 to 4

(ACR[6:4]). The output of the counter/timer may be used for a baud

rate and/or may be output to the OP pins for some external function

that may be totally unrelated to data transmission. The counter/timer

also sets the counter/timer ready bit in the Interrupt Status Register

(ISR) when its output transitions from 1 to 0. A register read address

(see Table 1) is reserved to issue a start counter/timer command

and a second register read address is reserved to issue a stop

command. The value of D[7:0] is ignored. The START command

always loads the contents of CTUR, CTLR to the counting registers.

The STOP command always resets the ISR[3] bit in the interrupt

status register.

Timer Mode

In the timer mode a symmetrical square wave is generated whose

half period is equal in time to division of the selected counter/timer

clock frequency by the 16-bit number loaded in the CTLR CTUR.

Thus, the frequency of the counter/timer output will be equal to the

counter/timer clock frequency divided by twice the value of the

CTUR CTLR. While in the timer mode the ISR bit 3 (ISR[3]) will be

set each time the counter/timer transitions from 1 to 0. (High to low)

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 17

This continues regardless of issuance of the stop counter command.

ISR[3] is reset by the stop counter command.

NOTE: Reading of the CTU and CTL registers in the timer mode is

not meaningful. When the C/T is used to generate a baud rate and

the C/T is selected through the CSR then the receiver and/or

transmitter will be operating in the 16x mode. Calculation for the

number ‘n’ to program the counter timer upper and lower registers is

shown below.

N+cńtclockrate

2 * 16 * Baud rate

Often this division will result in a non-integer number; 26.3 for

example. One can only program integer numbers to a digital divider.

Therefore 26 would be chosen. This gives a baud rate error of

0.3/26.3 which is 1.14%; well within the ability of the asynchronous

mode of operation.

Counter Mode

In the counter mode the counter/timer counts the value of the CTLR

CTUR down to zero and then sets the ISR[3] bit and sets the

counter/timer output from 1 to 0. It then rolls over to 65,365 and

continues counting with no further observable effect. Reading the

C/T in the counter mode outputs the present state of the C/T. If the

C/T is not stopped, a read of the C/T may result in changing data on

the data bus.

Timeout Mode

The timeout mode uses the received data stream to control the

counter. The time-out mode forces the C/T into the timer mode.

Each time a received character is transferred from the shift register

to the RxFIFO, the counter is restarted. If a new character is not

received before the counter reaches zero count, the counter ready

bit is set, and an interrupt can be generated. This mode can be used

to indicate when data has been left in the Rx FIFO for more than the

programmed time limit. If the receiver has been programmed to

interrupt the CPU when the receive FIFO is full, and the message

ends before the FIFO is full, the CPU will not be interrupted for the

remaining characters in the RxFIFO.

By programming the C/T such that it would time out in just over one

character time, the above situation could be avoided. The processor

would be interrupted any time the data stream had stopped for more

than one character time. NOTE: This is very similar to the watch dog

timer of MR0. The difference is in the programmability of the delay

timer and that this indicates that the data stream has stopped. The

watchdog timer is more of an indicator that data is in the FIFO is not

enough to cause an interrupt. The watchdog is restarted by either a

receiver load to the RxFIFO or a system read from it.

This mode is enabled by writing the appropriate command to the

command register. Writing an ‘0xAn’ to CR will invoke the timeout

mode for that channel. Writing a ‘Cx’ to CR will disable the timeout

mode. The timeout mode disables the regular START/STOP counter

commands and puts the C/T into counter mode under the control of

the received data stream. Each time a received character is

transferred from the shift register to the RxFIFO, the C/T is stopped

after one C/T clock, reloaded with the value in CTUR and CTLR and

then restarted on the next C/T clock. If the C/T is allowed to end the

count before a new character has been received, the counter ready

Bit, ISR[3], will be set. If IMR[3] is set, this will generate an interrupt.

Since receiving a character restarts the C/T, the receipt of a

character after the C/T has timed out will clear the counter ready bit,

ISR [3], and the interrupt. Invoking the ‘Set Timeout Mode On’

command, CRx = 0xAn, will also clear the counter ready bit and stop

the counter until the next character is received. The counter timer is

controlled with six commands: Start/Stop C/T, Read/Write

Counter/Timer lower register and Read/Write Counter/Timer upper

register. These commands have slight differences depending on the

mode of operation. Please see the detail of the commands under the

CTLR CTUR Register descriptions.

Time Out Mode Caution

When operating in the special time out mode it is possible to

generate what appears to be a “false interrupt”, i.e. an interrupt

without a cause. This may result when a time-out interrupt occurs

and then, BEFORE the interrupt is serviced, another character is

received, i.e., the data stream has started again. (The interrupt

latency is longer than the pause in the data stream.) In this case,

when a new character has been receiver, the counter/timer will be

restarted by the receiver, thereby withdrawing its interrupt. If, at this

time, the interrupt service begins for the previously seen interrupt, a

read of the ISR will show the “Counter Ready” bit not set. If nothing

else is interrupting, this read of the ISR will return a x’00 character.

This action may present the appearance of a spurious interrupt.

Communications

The communications channel of the SC28L91 comprises a

full-duplex asynchronous receiver/transmitter (UART). The operating

frequency for the receiver and transmitter can be selected

independently from the baud rate generator, the counter/timer, or

from an external input. The transmitter accepts parallel data from the

CPU, converts it to a serial bit stream, inserts the appropriate start,

stop, and optional parity bits and outputs a composite serial stream

of data on the TxD output pin. The receiver accepts serial data on

the RxD pin, converts this serial input to parallel format, checks for

start bit, stop bit, parity bit (if any), or break condition and sends an

assembled character to the CPU via the receive FIFO. Three status

bits (Break Received, Framing and Parity Errors) are also FIFOed

with the data character.

Input Port

The inputs to this unlatched 7-bit (6-bit for 68xxx mode) port can be

read by the CPU by performing a read operation at address 0xD. A

High input results in a logic 1 while a Low input results in a logic 0.

D7 will always read as a logic 1. The pins of this port can also serve

as auxiliary inputs to certain portions of the UART logic, modem and

DMA.

Four change-of-state detectors are provided which are associated

with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High

transition of these inputs, lasting longer than 25–50 µs, will set the

corresponding bit in the input port change register. The bits are

cleared when the register is read by the CPU. Any change-of-state

can also be programmed to generate an interrupt to the CPU.

The input port change of state detection circuitry uses a 38.4 kHz

sampling clock derived from one of the baud rate generator taps.

This results in a sampling period of slightly more than 25 µs (this

assumes that the clock input is 3.6864 MHz). The detection circuitry,

in order to guarantee that a true change in level has occurred,

requires two successive samples at the new logic level be observed.

As a consequence, the minimum duration of the signal change is

25 µs if the transition occurs “coincident with the first sample pulse”.

The 50 µs time refers to the situation in which the change-of-state is

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 18

“just missed” and the first change-of-state is not detected until 25 µs

later.

Output Port

The output ports are controlled from six places: the OPCR, OPR,

MR, Command, SOPR and ROPR registers. The OPCR register

controls the source of the data for the output ports OP2 through

OP7. The data source for output ports OP0 and OP1 is controlled by

the MR and CR registers. When the OPR is the source of the data

for the output ports, the data at the ports is inverted from that in the

OPR register. The content of the OPR register is controlled by the

“Set Output Port Bits Command” and the “Reset Output Bits

Command”. These commands are at E and F, respectively. When

these commands are used, action takes place only at the bit

locations where ones exist. For example, a one in bit location 5 of

the data word used with the “Set Output Port bits” command will

result in OPR[5] being set to one. The OP5 would then be set to

zero (VSS). Similarly, a one in bit position 5 of the data word

associated with the “Reset Output Ports Bits” command would set

OPR[5] to zero and, hence, the pin OP5 to a one (VDD).

These pins along with the IP pins and their change of state detectors

are often used for modem and DMA control.

OPERATION

Transmitter

The SC28L91 is conditioned to transmit data when the transmitter is

enabled through the command register. The SC28L91 indicates to

the CPU that it is ready to accept a character by setting the TxRDY

bit in the status register. This condition can be programmed to

generate an interrupt request at OP6 or OP7 and INTRN. When the

transmitter is initially enabled the TxRDY and TxEMPT bits will be

set in the status register. When a character is loaded to the transmit

FIFO the TxEMPT bit will be reset. The TxEMPT will not set until: 1)

the transmit FIFO is empty and the transmit shift register has

finished transmitting the stop bit of the last character written to the

transmit FIFO, or 2) the transmitter is disabled and then re-enabled.

The TxRDY bit is set whenever the transmitter is enabled and the

TxFIFO is not full. Data is transferred from the holding register to

transmit shift register when it is idle or has completed transmission

of the previous character. Characters cannot be loaded into the

TxFIFO while the transmitter is disabled.

The transmitter converts the parallel data from the CPU to a serial

bit stream on the TxD output pin. It automatically sends a start bit

followed by the programmed number of data bits, an optional parity

bit, and the programmed number of stop bits. The least significant

bit is sent first. Following the transmission of the stop bits, if a new

character is not available in the TxFIFO, the TxD output remains

High and the TxEMT bit in the Status Register (SR) will be set to 1.

Transmission resumes and the TxEMT bit is cleared when the CPU

loads a new character into the TxFIFO.

If the transmitter is disabled it continues operating until the character

currently being transmitted and any characters in the TxFIFO,

including parity and stop bits, have been transmitted. New data

cannot be loaded to the TxFIFO when the transmitter is disabled.

When the transmitter is reset it stops sending data immediately.

The transmitter can be forced to send a break (a continuous low

condition) by issuing a START BREAK command via the CR

register. The break is terminated by a STOP BREAK command or a

transmitter reset.

If CTS option is enabled (MR2[4] = 1), the CTS input at IP0 or IP1

must be Low in order for the character to be transmitted. The

transmitter will check the state of the CTS input at the beginning of

the character transmitted. If it is found to be High, the transmitter will

delay the transmission of any following characters until the CTS has

returned to the low state. CTS going high during the serialization of

a character will not affect that character.

The transmitter can also control the RTSN outputs, OP0 or OP1 via

MR2[5]. When this mode of operation is set, the meaning of the OP0

or OP1 signals will usually be ‘end of message’. See description of

the MR2[5] bit for more detail. This feature may be used to

automatically “turn around” a transceiver in simplex systems.

Receiver

The SC28L91 is conditioned to receive data when enabled through

the command register. The receiver looks for a High-to-Low

(mark-to-space) transition of the start bit on the RxD input pin. If a

transition is detected, the state of the RxD pin is sampled the 16X

clock for 7–1/2 clocks (16X clock mode) or at the next rising edge of

the bit time clock (1X clock mode). If RxD is sampled high, the start

bit is invalid and the search for a valid start bit begins again. If RxD

is still Low, a valid start bit is assumed and the receiver continues to

sample the input at one-bit time intervals at the theoretical center of

the bit. When the proper number of data bits and parity bit (if any)

have been assembled, and one/half stop bit has been detected the

byte is loaded to the RxFIFO. The least significant bit is received

first. The data is then transferred to the Receive FIFO and the

RxRDY bit in the SR is set to a 1. This condition can be

programmed to generate an interrupt at OP4 or OP5 and INTRN. If

the character length is less than 8 bits, the most significant unused

bits in the RxFIFO are set to zero.

After the stop bit is detected, the receiver will immediately look for

the next start bit. However if a framing error occurs (a non-zero

character was received without a stop bit) and then RxD remains

low one/half bit time the receiver operates as if a new start bit was

detected. It then continues to assemble the next character.

The parity error, framing error, and overrun error (if any) are strobed

into the SR from the next byte to be read from the Rx FIFO.

If a break condition is detected (RxD is Low for the entire character

including the stop bit), a character consisting of all zeros will be

loaded into the RxFIFO and the received break bit in the SR is set to

1. The RxD input must return to high for two (2) clock edges of the

X1 crystal clock for the receiver to recognize the end of the break

condition and begin the search for a start bit.

This will usually require a high time of one X1 clock period or 3 X1

edges since the clock of the controller is not synchronous to the X1

clock.

Transmitter Reset and Disable

Note the difference between transmitter disable and reset. A

transmitter reset stops transmitter action immediately, clears the

transmitter FIFO and returns the idle state. A transmitter disable

withdraws the transmitter interrupts but allows the transmitter to

continue operation until all bytes in its FIFO and shift register have

been transmitted including the final stop bits. It then returns to its

idle state.

Receiver FIFO

The RxFIFO consists of a First-In-First-Out (FIFO) stack with a

capacity of 8 or 16 characters. Data is loaded from the receive shift

register into the topmost empty position of the FIFO. The RxRDY bit

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 19

in the status register is set whenever one or more characters are

available to be read, and a FFULL status bit is set if all 8 or 16 stack

positions are filled with data. Either of these bits can be selected to

cause an interrupt. A read of the RxFIFO outputs the data at the top

of the FIFO. After the read cycle, the data FIFO and its associated

status bits (see below) are ‘popped’ thus emptying a FIFO position

for new data.

A disabled receiver with data in its FIFO may generate an interrupt

(see “Receiver Status Bits”, below). Its status bits remain active and

its watchdog, if enabled, will continue to operate.

Receiver Status Bits

In addition to the data word, three status bits (parity error, framing

error, and received break) are also appended to the data character

in the FIFO. The overrun error, MR1[5], and the change of break

(ISR[2]) are not FIFOed.

The status of the Rx FIFO may be provided in two ways, as

programmed by the error mode control bit in the mode register

(MR1[5]). In the ‘character’ mode, status is provided on a

character-by-character basis; the status applies only to the

character at the top of the FIFO. In the ‘block’ mode, the status

provided in the SR for these three bits is the logical-OR of the status

for all characters coming to the top of the FIFO since the last ‘reset

error’ from the command register was issued. In either mode

reading the SR does not affect the FIFO. The FIFO is ‘popped’ only

when the RxFIFO is read. Therefore the status register should be

read prior to reading the FIFO.

If the FIFO is full when a new character is received, that character is

held in the receive shift register until a FIFO position is available. If

an additional character is received while this state exits, the

contents of the FIFO are not affected; the character previously in the

shift register is lost and the overrun error status bit (SR[4]) will be

set-upon receipt of the start bit of the new (overrunning) character.

The receiver can control the deactivation of RTS. If programmed to

operate in this mode, the RTSN output will be negated when a valid

start bit was received and the FIFO is full. When a FIFO position

becomes available, the RTSN output will be re-asserted (set low)

automatically. This feature can be used to prevent an overrun, in the

receiver, by connecting the RTSN output to the CTSN input of the

transmitting device.

If the receiver is disabled, the FIFO characters can be read.

However, no additional characters can be received until the receiver

is enabled again. If the receiver is reset, the FIFO and all of the

receiver status, and the corresponding output ports and interrupt are

reset. No additional characters can be received until the receiver is

enabled again.

Receiver Reset and Disable

Receiver disable stops the receiver immediately—data being

assembled in the receiver shift register is lost. Data and status in the

FIFO is preserved and may be read. A re-enable of the receiver

after a disable will cause the receiver to begin assembling

characters at the next start bit detected.

A receiver reset will discard the present shift register date, reset the

receiver ready bit (RxRDY), clear the status of the byte at the top of

the FIFO and re-align the FIFO read/write pointers.

Watchdog

A ‘watchdog timer’ is associated with the receiver. Its interrupt is

enabled by MR0[7]. The purpose of this timer is to alert the control

processor that characters are in the RxFIFO which have not been

read. This situation may occur at the end of a transmission when the

last few characters received are not sufficient to cause an interrupt.

This counter times out after 64 bit times. It is reset each time a

character is transferred from the receiver shift register to the

RxFIFO or a read of the RxFIFO is executed.

Receiver Time-out Mode

In addition to the watch dog timer described in the receiver section,

the counter/timer may be used for a similar function. Its 16-bit

programmability allows much greater precision of time out intervals.

The time-out mode uses the received data stream to control the

counter. Each time a received character is transferred from the shift

register to the RxFIFO, the counter is restarted. If a new character is

not received before the counter reaches zero count, the counter

ready bit is set, and an interrupt can be generated. This mode can

be used to indicate when data has been left in the RxFIFO for more

than the programmed time limit. Otherwise, if the receiver has been

programmed to interrupt the CPU when the receive FIFO is full, and

the message ends before the FIFO is full, the CPU may not know

there is data left in the FIFO. The CTU and CTL value would be

programmed for just over one character time, so that the CPU would

be interrupted as soon as it has stopped receiving continuous data.

This mode can also be used to indicate when the serial line has

been marking for longer than the programmed time limit. In this

case, the CPU has read all of the characters from the FIFO, but the

last character received has started the count. If there is no new data

during the programmed time interval, the counter ready bit will get

set, and an interrupt can be generated.

The time-out mode is enabled by writing the appropriate command

to the command register. Writing an 0xAn to CR will invoke the

time-out mode for that channel. Writing a ‘Cx’ to CR will disable the

time-out mode. The time-out mode should only be used by one

channel at once, since it uses the C/T. CTU and CTL must be

loaded with a value greater than the normal receive character

period. The time-out mode disables the regular START/STOP

Counter commands and puts the C/T into counter mode under the

control of the received data stream. Each time a received character

is transferred from the shift register to the RxFIFO, the C/T is

stopped after 1 C/T clock, reloaded with the value in CTU and CTL

and then restarted on the next C/T clock. If the C/T is allowed to end

the count before a new character has been received, the counter

ready bit, ISR[3], will be set. If IMR[3] is set, this will generate an

interrupt. Receiving a character after the C/T has timed out will clear

the counter ready bit, ISR[3], and the interrupt. Invoking the ‘Set

Time-out Mode On’ command, CRx = ‘Ax’, will also clear the counter

ready bit and stop the counter until the next character is received.

Watchdog and Time Out Mode Differences

The watchdog timer is restarted each time a character is read from

or written to the Rx FIFO. It is an indicator that data is in the FIFO

that has not been read. If the Rx FIFO is empty no action occurs. In

the time out mode the C/T is stopped and restarted each time a

character is written to the Rx FIFO. From this point of view the time

out of the C/T is an indication that the data stream has stopped.

After the time out mode is invoked the timer will not start until the

first character is written to the Rx FIFO.

Time Out Mode Caution

When operating in the special time out mode, it is possible to

generate what appears to be a “false interrupt”, i.e. an interrupt

without a cause. This may result when a time-out interrupt occurs

and then, BEFORE the interrupt is serviced, another character is

received, i.e., the data stream has started again. (The interrupt

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 20

latency is longer than the pause in the data stream.) In this case,

when a new character has been received, the counter/timer will be

restarted by the receiver, thereby withdrawing its interrupt. If, at this

time, the interrupt service begins for the previously seen interrupt, a

read of the ISR will show the “Counter Ready” bit not set. If nothing

else is interrupting, this read of the ISR will return a x’00 character.

Multi-drop Mode (9-bit or Wake-Up)

The UART is equipped with a wake up mode for multi-drop

applications. This mode is selected by programming bits MR1[4:3]or

to ‘11’. In this mode of operation, a ‘master’ station transmits an

address character followed by data characters for the addressed

‘slave’ station. The slave station(s) whose receiver(s) that are

normally disabled, examine the received data stream and ‘wakeup’

the CPU (by setting RxRDY) only upon receipt of an address

character. The CPU compares the received address to its station

address and enables the receiver if it wishes to receive the

subsequent data characters. Upon receipt of another address

character, the CPU may disable the receiver to initiate the process

again.

A transmitted character consists of a start bit, the programmed

number of data bits, and Address/Data (A/D) bit, and the

programmed number of stop bits. The polarity of the transmitted A/D

bit is selected by the CPU by programming bit MR1[2]. MR1[2]= 0

transmits a zero in the A/D bit position, which identifies the

corresponding data bits as data. MR1[2] = 1 transmits a one in the

A/D bit position, which identifies the corresponding data bits as an

address. The CPU should program the mode register prior to

loading the corresponding data bits into the TxFIFO.

MR1[2] = 1 transmits a one in the A/D bit position, which identifies

the corresponding data bits as an address. The CPU should

program the mode register prior to loading the corresponding data

bits into the TxFIFO.

In this mode, the receiver continuously looks at the received data

stream, whether it is enabled or disabled. If disabled, it sets the

RxRDY status bit and loads the character into the RxFIFO if the

received A/D bit is a one (address tag), but discards the received

character if the received A/D bit is a zero (data tag). If enabled, all

received characters are transferred to the CPU via the RxFIFO. In

either case, the data bits are loaded into the data FIFO while the

A/D bit is loaded into the status FIFO position normally used for

parity error (SR[5] ). Framing error, overrun error, and break detect

operate normally whether or not the receiver is enabled.

PROGRAMMING

The operation of the UART is programmed by writing control words

into the appropriate registers. Operational feedback is provided via

status registers which can be read by the CPU. The addressing of

the registers is described in Table 1.

The contents of certain control registers are initialized to zero on

RESET. Care should be exercised if the contents of a register are

changed during operation, since certain changes may cause

operational problems.

For example, changing the number of bits per character while the

transmitter is active may cause the transmission of an incorrect

character. In general, the contents of the MR, the CSR, and the

OPCR should only be changed while the receiver(s) and

transmitter(s) are not enabled, and certain changes to the ACR

should only be made while the C/T is stopped.

The channel has 3 mode registers (MR0, 1, 2) which control the

basic configuration of the channel. Access to these registers is

controlled by independent MR address pointers. These pointers are

set to 0 or 1 by MR control commands in the command register

“Miscellaneous Commands”. Each time the MR registers are

accessed the MR pointer increments, stopping at MR2. It remains

pointing to MR2 until set to 0 or 1 via the miscellaneous commands

of the command register. The pointer is set to 1 on reset for

compatibility with previous Philips Semiconductors UART software.

Refer to Table 2 for register bit descriptions. The reserved registers

at addresses 0x02 and 0x0A should never be read during normal

operation since they are reserved for internal diagnostics.

Table 1. SC28L91 register addressing

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Address Bits

A[3:0]

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

READ (RDN = 0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

WRITE (WRN = 0)

0000Mode Register(MR0, MR1, MR2) Mode Register(MR0, MR1, MR2)

0001Status Register(SR) Clock Select Register(CSR)

0 0 1 0 Reserved Command Register(CR)

0011Rx Holding Register(RxFIFO) Tx Holding Register(RxFIFO)

0100Input Port Change Register (IPCR) Aux. Control Register (ACR)

0101Interrupt Status Register (ISR) Interrupt Mask Register (IMR)

0110Counter/Timer Upper (CTU) C/T Upper Preset Register (CTPU)

0111Counter/Timer Lower (CTL) C/T Lower Preset Register (CTPL)

1100Interrupt vector (68K mode), Misc. register in Intel mode Interrupt vector (68K mode), Misc. register in Intel mode

1100IVR Motorola mode, Misc. register (Intel mode) IVR Motorola mode, Misc. register (Intel mode)

1101Input Port (IPR) Output Port Configuration Register (OPCR)

1110Start Counter Command Set Output Port Bits Command (SOPR)

1111Stop Counter Command Reset output Port Bits Command (ROPR)

NOTE:

1. The three MR registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and transmitter enable bits)

Philips SC28L91 Operational manual

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