Philips SC28L91 Operational manual



SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
Product data sheet
Supersedes data of 2000 Sep 22 2004 Oct 21
INTEGRATED CIRCUITS

Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2
2004 Oct 21
DESCRIPTION
The SC28L91 is a new member of the IMPACT family of Serial
Communications Controllers. It is a single channel UART operating
at 3.3 V and 5.0 V VCC, 8 or 16 byte FIFOs and is quite compatible
with software of the SC28L92 and previous UARTs offered by
Philips. It is a new part that is similar to our previous one channel
part but is vastly improved. The improvements being: 16 character
receiver, 16 character transmit FIFOs, watch dog timer for the
receiver, mode register 0 is added, extended baud rate, over all
faster bus and data speeds, programmable receiver and transmitter
interrupts and versatile I/O structure. (The previous one channel
part, SCC2691, is NOT being discontinued.)
Pin programming will allow the device to operate with either the
Motorola or Intel bus interface. Bit 3 of the MR0 register allows the
device to operate in an 8-byte FIFO mode if strict compliance with
an 8-byte FIFO structure is required.
The Philips Semiconductors SC28L91 Universal Asynchronous
Receiver/Transmitter (UART) is a single-chip CMOS-LSI
communications device that provides a full-duplex asynchronous
receiver/transmitter channel in a single package. It interfaces
directly with microprocessors and may be used in a polled or
interrupt driven system with modem and DMA interface.
The operating mode and data format of the channel can be
programmed independently. Additionally, the receiver and
transmitter can select its operating speed as one of 28 fixed baud
rates; a 16X clock derived from a programmable counter/timer, or an
external 1X or 16X clock. The baud rate generator and counter/timer
can operate directly from a crystal or from external clock inputs. The
ability to independently program the operating speed of the receiver
and transmitter make the UART particularly attractive for dual-speed
channel applications such as clustered terminal systems.
The receiver and transmitter is buffered by 8 or 16 character FIFOs
to minimize the potential of receiver overrun, transmitter underrun
and to reduce interrupt overhead in interrupt driven systems. In
addition, a flow control capability is provided via RTS/CTS signaling
to disable a remote transmitter when the receiver buffer is full.
DMA interface is and other general purpose signals are provided on
the SC28L91 via a multipurpose 7-bit input port and a multipurpose
8-bit output port. These can be used as general-purpose ports or
can be assigned specific functions (such as clock inputs or
status/interrupt outputs, FIFO conditions) under program control.
The SC28L91 is available in two package versions: a 44-pin PLCC
and 44-pin plastic quad flat pack (PQFP).
FEATURES
•Member of IMPACT family: 3.3 to 5.0 volt , –40°C to +85°C and
68K for 80xxx bus interface for all devices.
•A full-duplex independent asynchronous receiver/transmitter
•16 character FIFOs for each receiver and transmitter
•Pin programming selects 68K or 80xxx-bus interface
•Programmable data format
–5 to 8 data bits plus parity
–Odd, even, no parity or force parity
–– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
•16-bit programmable Counter/Timer
•Programmable baud rate for each receiver and transmitter
selectable from:
–28 fixed rates: 50 to 230.4 k baud
–Other baud rates to 1 MHz at 16X
–Programmable user-defined rates derived from a programmable
counter/timer
–External 1X or 16X clock
•Parity, framing, and overrun error detection
•False start bit detection
•Line break detection and generation
•Programmable channel mode
–Normal (full-duplex)
–Automatic echo
–Local loop back
–Remote loop back
–Multi-drop mode (also called ‘wake-up’ or ‘9-bit’)
•Multi-function 7-bit input port (includes IACKN)
–Can serve as clock or control inputs
–Change of state detection on four inputs
–Inputs have typically >100 kΩpull-up resistors
–Change of state detectors for modem control
•Multi-function 8-bit output port
–Individual bit set/reset capability
–Outputs can be programmed to be status/interrupt signals
–FIFO status for DMA interface
•Versatile interrupt system
–Single interrupt output with eight maskable interrupting
conditions
–Output port can be configured to provide a total of up to six
separate interrupt outputs that may be wire ORed.
–Each FIFO can be programmed for four different interrupt levels
–Watchdog timer for the receiver
•Maximum data transfer rates:
1X – 1 Mbit/s, 16X – 1 Mbit/s
•Automatic wake-up mode for multi-drop applications
•Start-end break interrupt/status with mid-character break detect.
•On-chip crystal oscillator
•Power-down mode
•Receiver time-out mode
•Single +3.3 V or +5 V power supply

Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21 3
ORDERING INORMATION
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
Industrial
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
VCC = +3.3 V ±10 %, +5 V ±10 %
ÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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Description
ÁÁÁÁÁÁÁÁÁÁÁ
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Tamb = –40 °C to +85 °C
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
Drawing Number
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
44-Pin Plastic Leaded Chip Carrier (PLCC)
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
SC28L91A1A
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
SOT187-2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
44-Pin Plastic Quad Flat Pack (PQFP)
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
SC28L91A1B
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
SOT307-2

Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21 4
PIN CONFIGURATION DIAGRAM
80XXX PIN CONFIGURATION
Pin Function
1A3
2 IP0
3 WRN
4 RDN
5V
CC
6 No Connection
7 OP1
8 OP3
9 OP5
10 OP7
11 I/M
12 D1
13 D3
14 D5
15 D7
Pin Function
16 GND
17 GND
18 INTRN
19 D6
20 D4
21 D2
22 D0
23 NC
24 OP6
25 OP4
26 OP2
27 OP0
28 TxDA
29 RxDA
30 x1/clk
Pin Function
31 x2
32 RESET
33 CEN
34 IP2
35 IP6
36 IP5
37 IP4
38 VCC
39 VCC
40 A0
41 IP3
42 A1
43 IP1
44 A2
PQFP
44 34
1
11
33
23
12 22
SD00698
1
39
17
28
40
29
18
7
PLCC
6
SD00699
Pin Function
1NC
2A0
3 IP3
4A1
5 IP1
6A2
7A3
8 IP0
9 WRN
10 RDN
11 VCC
12 I/M
13 No Connection
14 OP1
15 OP3
Pin Function
16 OP5
17 OP7
18 D1
19 D3
20 D5
21 D7
22 VSS
23 NC
24 INTRN
25 D6
26 D4
27 D2
28 D0
29 OP6
30 OP4
Pin Function
31 OP2
32 OP0
33 TxDA
34 NC
35 RxDA
36 X1/CLK
37 X2
38 RESET
39 CEN
40 IP2
41 IP6
42 IP5
43 IP4
44 VCC
Note: Pins marked “No Connection” must NOT be connected.

Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21 5
PIN CONFIGURATION DIAGRAM
68XXX PIN CONFIGURATION
Pin Function
1A3
2 IP0
3 R/WN
4 DACKN
5V
CC
6 No Connection
7 OP1
8 OP3
9 OP5
10 OP7
11 I/M
12 D1
13 D3
14 D5
15 D7
Pin Function
16 GND
17 GND
18 INTRN
19 D6
20 D4
21 D2
22 D0
23 NC
24 OP6
25 OP4
26 OP2
27 OP0
28 TxDA
29 RxDA
30 x1/clk
Pin Function
31 x2
32 RESETN
33 CEN
34 IP2
35 IACKN
36 IP5
37 IP4
38 VCC
39 VCC
40 A0
41 IP3
42 A1
43 IP1
44 A2
PQFP
44 34
1
11
33
23
12 22
SD00700
1
39
17
28
40
29
18
7
PLCC
6
SD00701
Pin Function
1NC
2A0
3 IP3
4A1
5 IP1
6A2
7A3
8 IP0
9 R/WN
10 DACKN
11 VCC
12 I/M
13 No Connection
14 OP1
15 OP3
Pin Function
16 OP5
17 OP7
18 D1
19 D3
20 D5
21 D7
22 VSS
23 NC
24 INTRN
25 D6
26 D4
27 D2
28 D0
29 OP6
30 OP4
Pin Function
31 OP2
32 OP0
33 TxDA
34 NC
35 RxDA
36 X1/CLK
37 X2
38 RESETN
39 CEN
40 IP2
41 IACKN
42 IP5
43 IP4
44 VCC
Note: Pins marked “No Connection” must NOT be connected.

Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21 6
8
D0–D7
RDN
WRN
CEN
A0–A3
RESET
INTRN
X1/CLK
X2
4
BUS BUFFER
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
INTERRUPT CONTROL
IMR
ISR
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL OSC
CSR
ACR
CTL
DATA CHANNEL
16 BYTE TRANSMIT
FIFO
TRANSMIT
SHIFT REGISTER
16 BYTE RECEIVE
FIFO
MRA0, 1, 2
CRA
SRA
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
OUTPUT PORT
FUNCTION
SELECT LOGIC
OPCR
TxDA
RxDA
IP0-IP6
OP0-OP7
VCC
VSS
CONTROL TIMING INTERNAL DATABUS
IPCR
ACR
OPR
CTU
8
7
WATCH DOG TIMER
RECEIVE SHIFT
REGISTER
SD00702
GP
Figure 1. Block Diagram (80XXX mode)

Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21 7
8
D0–D7
R/WN
CEN
A0–A3
RESETN
INTRN
X1/CLK
X2
4
BUS BUFFER
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
INTERRUPT CONTROL
IMR
ISR
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL OSC
CSR
ACR
CTL
DATA CHANNEL
16 BYTE TRANSMIT
FIFO
TRANSMIT
SHIFT REGISTER
16 BYTE RECEIVE
FIFO
MRA0, 1, 2
CRA
SRA
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
OUTPUT PORT
FUNCTION
SELECT LOGIC
OPCR
TxDA
RxDA
IP0-IP5
OP0-OP7
VCC
VSS
CONTROL TIMING INTERNAL DATABUS
IPCR
ACR
OPR
CTU
8
6
WATCH DOG TIMER
RECEIVE SHIFT
REGISTER
SD00703
IVR
DACKN
IACKN
Figure 2. Block Diagram (68XXX mode)

Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21 8
PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL)
Symbol Pin
type Name and function
I/M IBus Configuration: When high or not connected configures the bus interface to the Conditions shown in this table.
D0–D7 I/O Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the
CPU. D0 is the least significant bit.
CEN IChip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on
D0–D7 as controlled by the WRN, RDN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condi-
tion.
WRN IWrite Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed register. The
transfer occurs on the rising edge of the signal.
RDN IRead Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be presented on the
data bus. The read cycle begins on the falling edge of RDN.
A0–A3 IAddress Inputs: Select the UART internal registers and ports for read/write operations.
RESET IReset: A High level clears internal registers (SR, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state, stops the
counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets MR point-
er to MR1. See Figure 4
INTRN OInterrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable in-
terrupting conditions are true. This pin requires a pull-up device.
X1/CLK ICrystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a
crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).
X2 OCrystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin
to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.
RxD IReceiver Serial Data Input: The least significant bit is received first. “Mark” is High; “space” is Low.
TxD OTransmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the “mark” condition
when the transmitter is disabled, idle or operating in local loop back mode. “Mark” is High; “space” is Low.
OP0 OOutput 0: General-purpose output or request to send (RTSN, active-Low). Can be deactivated automatically on re-
ceive or transmit.
OP1 OOutput 1: General-purpose output.
OP2 OOutput 2: General-purpose output, or transmitter 1X or 16X clock output, or receiver 1X clock output.
OP3 OOutput 3: General-purpose output.
OP4 OOutput 4: General-purpose output or open-drain, active-Low, Rx interrupt ISR[1] output. DMA Control
OP5 OOutput 5: General-purpose output
OP6 OOutput 6: General-purpose output or open-drain, active-Low, Tx interrupt ISR[0] output. DMA Control
OP7 OOutput 7: General-purpose output.
IP0 IInput 0: General-purpose input or clear to send active-Low input (CTSN). Has Change of State Dector.
IP1 IInput 1: General-purpose input. Has Change of State Dector.
IP2 I Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector.
IP3 IInput 3: General-purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-
mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.
IP4 IInput 4: General-purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,
the received data is sampled on the rising edge of the clock.
IP5 IInput 5: General-purpose input
IP6 IInput 6: General-purpose input
VCC Pwr Power Supply: +3.3 V or +5 V supply input ±10 %
GND Pwr Ground

Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21 9
PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA)
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
Symbol
ÁÁÁ
Á
Á
Á
ÁÁÁ
Pin
type
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Name and function
ÁÁÁÁ
ÁÁÁÁ
I/M
ÁÁÁ
ÁÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Bus Configuration: When low configures the bus interface to the Conditions shown in this table.
ÁÁÁÁ
ÁÁÁÁ
D0–D7
ÁÁÁ
ÁÁÁ
I/O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the
CPU. D0 is the least significant bit.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
CEN
ÁÁÁ
Á
Á
Á
ÁÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on
D0–D7 as controlled by the R/WN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condition.
ÁÁÁÁ
ÁÁÁÁ
R/WN
ÁÁÁ
ÁÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Read/Write: Input Signal. When CEN is low R/WN high input indicates a read cycle; when low indicates a write cycle.
ÁÁÁÁ
ÁÁÁÁ
IACKN
ÁÁÁ
ÁÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Interrupt Acknowledge: Active low input indicating an interrupt acknowledge cycle. Usually asserted by the CPU in
response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
DACKN
ÁÁÁ
Á
Á
Á
ÁÁÁ
O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Data Transfer Acknowledge: A3-State active-low output asserted in a write, read, or interrupt acknowledge cycle to
indicate proper transfer of data between the CPU and the UART.
ÁÁÁÁ
ÁÁÁÁ
A0–A3
ÁÁÁ
ÁÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Address Inputs: Select the UART internal registers and ports for read/write operations.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
RESETN
ÁÁÁ
Á
Á
Á
ÁÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reset: A low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state,
stops the counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets
MR pointer to MR1. See Figure 4
ÁÁÁÁ
ÁÁÁÁ
INTRN
ÁÁÁ
ÁÁÁ
O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable
interrupting conditions are true. This pin requires a pullup.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
X1/CLK
ÁÁÁ
Á
Á
Á
ÁÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When
a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).
ÁÁÁÁ
ÁÁÁÁ
X2
ÁÁÁ
ÁÁÁ
O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this
pin to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.
ÁÁÁÁ
ÁÁÁÁ
RxD
ÁÁÁ
ÁÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
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Á
ÁÁ
Á
ÁÁÁÁ
TxD
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Á
Á
Á
ÁÁÁ
O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’ condition
when the transmitter is disabled, idle, or when operating in local loop back mode. ‘Mark’ is High; ‘space’ is Low.
ÁÁÁÁ
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OP0
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ÁÁÁ
O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output 0: General purpose output or request to send (RTSAN, active-Low). Can be deactivated automatically on
receive or transmit.
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OP1
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ÁÁÁ
O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output 1: General-purpose output.
ÁÁÁÁ
ÁÁÁÁ
OP2
ÁÁÁ
ÁÁÁ
O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output 2: General purpose output or transmitter 1X or 16X clock output, or receiver 1X clock output.
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OP3
ÁÁÁ
ÁÁÁ
O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output 3: General purpose output.
ÁÁÁÁ
ÁÁÁÁ
OP4
ÁÁÁ
ÁÁÁ
O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output 4: General purpose output or open-drain, active-Low, RxA interrupt ISR [1] output. DMA Control
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OP5
ÁÁÁ
ÁÁÁ
O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output 5: General-purpose output.
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OP6
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O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output 6: General purpose output or open-drain, active-Low, TxA interrupt ISR[0] output. DMA Control
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OP7
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ÁÁÁ
O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output 7: General-purpose output.
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ÁÁÁÁ
IP0
ÁÁÁ
ÁÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input 0: General purpose input or clear to send active-Low input (CTSAN). Has Change of State Dector.
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IP1
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I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input 1: General purpose input. Has Change of State Dector.
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IP2
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I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector.
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IP3
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ÁÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input 3: General purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-
mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.
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Á
ÁÁ
Á
ÁÁÁÁ
IP4
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Á
Á
Á
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I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input 4: General purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,
the received data is sampled on the rising edge of the clock.
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IP5
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ÁÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input 5: General purpose input.
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VCC
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Pwr
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power Supply: +3.3 or +5V supply input ±10%
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GND
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Pwr
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ground

Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21 10
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter Rating Unit
Tamb Operating ambient temperature range2Note 4 °C
Tstg Storage temperature range –65 to +150 °C
VCC Voltage from VCC to GND3–0.5 to +7.0 V
VSVoltage from any pin to GND3–0.5 to VCC +0.5 V
PDPackage power dissipation (PLCC44) 2.4 W
PDPackage power dissipation (PQFP44) 1.78 W
Derating factor above 25 °C (PLCC44) 19 mW/°C
Derating factor above 25 °C (PQFP44) 14 mW/°C
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature and voltage range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
VCC = 5 V ±10 %, Tamb = –40 °C to +85 °C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low voltage 0.8 V
VIH Input high voltage (except X1/CLK) 2.4 1.5 V
VIH Input high voltage (X1/CLK) 0.8VCC 2.4 V
VOL Output low voltage IOL = 2.4 mA 0.2 0.4 V
VOH Output high voltage (except OD outputs)4IOH = –400 µAVCC – 0.5 V
IIX1PD X1/CLK input current - power down VIN = 0 V to VCC 0.5 0.05 0.5 µA
IILX1 X1/CLK input low current - operating VIN = 0 V –130 0µA
IIHX1 X1/CLK input high current - operating VIN = VCC 0 130 µA
Input leakage current:
IIAll except input port pins VIN = 0 V to VCC –0.5 0.05 +0.5 µA
Input port pins5VIN = 0 V to VCC –8 0.05 +0.5 µA
IOZH Output off current high, 3-State data bus VIN = VCC 0.5 µA
IOZL Output off current low, 3-State data bus VIN = 0 V –0.5 µA
IODL Open-drain output low current in off-state VIN = 0 V –0.5 µA
IODH Open-drain output high current in off-state VIN = VCC 0.5 µA
Power supply current6
ICC Operating mode CMOS input levels 7 25 mA
Power down mode CMOS input levels ≤1 5 mA
NOTES:
1. Parameters are valid over specified temperature and voltage range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/CLK, this swing is between 0.4 V and 0.8VCC. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL= 125 pF, except open drain outputs. Test conditions for open drain outputs: CL= 125 pF,
constant current source = 2.6 mA.
5. Input port pins have active pull-up transistors that will source a typical 2 µA from VCC when the input pins are at VSS.
Input port pins at VCC source 0.0 µA.
6. All outputs are disconnected. Inputs are switching between CMOS levels of VCC – 0.2 V and VSS + 0.2 V.