
SECTION 2 - TECHNICAL DESCRIPTION
Page 2.1
pickering
PXI/PXIe Analog Output/Current Loop Simulator 41/43-765
SECTION 2 - TECHNICAL DESCRIPTION
FUNCTIONAL DESCRIPTION
The 41/43-765 is designed to meet the requirements of industrial control applications utilising current loops 4 –
20mA. It is designed in the form of a typical PXI/PXIe module, supported by a PXI/PXIe, chassis or Pickering’s LXI/
USB chassis. The module is also designed to support PXIe communication but not as hybrid - please contact the
Pickering sales ofce for details. A functional block diagram is provided in Figure 2.1.
The Analog Output/Current Loop Simulator Module is powered by +12V, +5V and +3.3V supplies via Compact PCI
connector J1.
The interface to the user test equipment is via a front panel mounted 78-pin male D-type connector, J2. A pinout of
the connector is shown in Section 5, for each population variant of the module.
The module comprises a PCB populated with up to 4 digital to analog converter (DAC) devices (U11 to U14),
depending on module version. Each DAC provides 4 analog output channels that can be programmed to act as
current sources, current sinks or low power voltage sources. These are controlled by the PCI interface (U30) and
control logic via logic isolation devices (U7 to U10).
Each channel of the module can operate as a current loop transmitter, by sourcing current, or as a current loop
receiver by sinking current. In the sourcing current scenario, the 0-24mA and 4-20mA modes are recommended as
they deliver the best resolution, with the 0-24mA mode also delivering error and/or signalling ranges between 0-4mA
and 20-24mA. In the sinking current scenario, the ±24mA mode in the negative range, can be utilised. The module
can also deliver uni- and bi-polar low current voltage modes with precise resolution control.
For fault simulation purposes, the analog channels are routed to the front panel connector via isolation relays
(RLI_11 to RLI_44) and short relays (RLS_11 to RLS_44). When the short relay is energised for a particular channel,
the status of the corresponding isolation relay is irrelevant. To see how the relays are utilised for each channel,
please refer to the Functional Diagram or Figures 4.1 to 4.4.
Each DAC is powered via its own power management circuit, this includes relays (RL_DAC1 to RL_DAC4) for the
selection of the internal power supply or external power from the front panel connector. The internal power supply
is derived from the PXI bus and is xed at +12V. External power for each DAC is supplied via regulators (U151
to U154). The external supply can vary between +16.5V and +60V (regulated by the module to +15V). By default
the internal supply is selected and is used during the module power up sequence. When the internal supply is
selected, all the grounds are tied, including all channel grounds, to the controller and PXI chassis ground. When the
external power supplies are selected, each DAC works in full isolation mode. This means all channels of a specic
DAC have a common ground, isolated from the PXI chassis, controller ground and other DACs, which needs to be
provided by the external PSU. This feature can be used to break potential ground loops when delivering power from
the transmitter/receiver site. Each DAC can be used independently in this respect. Please see the 2- and 3-wire
connection examples in Section 1 of this manual, also refer to the “Connectivity Notes” section.
Output isolation, output shorting and power selection relays are controlled by relay drivers (U6, U22 and U23).
In many simulation cases it may be desirable to change the speed of the level-to-level signal transition. Therefore,
each channel has a programmable slew rate - this feature is disabled by default. The slew rate can be programmed
in two ways: by modifying the clock rate and/or the step size. The range of the clock rate is between 3.3Hz and
258.065Hz. Each step size is a multiple of 2 with 8 settings ranging from 1 to 128. Please see Figure 4.6 for the slew
rate programming concept. The time required for the output to slew over a given range may vary mode to mode and
the step size will be a different value in mA or V. When the slew rate control feature is enabled, the output changes
occur at the programmed slew rate. This conguration results in a staircase waveform at the output. If a hardware
clear is invoked, the output slews to the zero value at the programmed slew rate. When new data is written to the
DAC, the output starts slewing to the new value at the slew rate determined by the current settings.
The module consists of a safety hardware interlock feature which disables all the outputs if the front panel connector
is not correctly wired, or will immediately disable all the outputs it the front panel connector is removed whilst the
module is operating. Please see Section 5 – “Connector Information” for more details.