Pico Communications E-15 Use and care manual

www.picocomputing.com Pico Computing
[phone] 150 Nickerson Street. Suite 311
Seattle, WA 98109
Pico
PicoPico
Pico Computing
Computing Computing
Computing
Pico E-15
Hardware Technical
Reference
Release 1.01
For Hardware Revision D

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[phone] 150 Nickerson Street. Suite 311
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Contents:
Product Overview 3
Quick Reference Datasheet 4
Standard Part Numbers 5
System Architecture 6
Electrical Specification 7
Features
Field Programmable Gate Array 8
PowerPC™ Processor 9
CPLD TurboLoader 10
Flash Memory 11
DDR2 SDRAM Memory 12
Temperature Sensor 14
I/ Interfaces
Sleep Controller 15
Tri-Mode Ethernet Interface 16
Digital Peripheral Interface 17
High Speed Analog to Digital Converters 18
High Speed Digital to Analog Converters 21
Video Digitizer 23
CardBus / Digital Bus Interface 24
JTAG Debug Interface 25
PSoC Debug Interface 26
Appendices
A – Peripheral I/O Connector Information 27
B – CardBus Connector Information 28
C – FPGA Pinout 29
D – CPLD Pinout 33
E – PSoC Pinout 40
F – Standard Part Number Listing 41
G – Errata 43
H – FPGA Performance Enhancements 44
Revision History 45
Legal Notices 46

Pico E-15 Hardware Reference www.picocomputing.com Pico Computing
[phone] 150 Nickerson Street. Suite 311
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Product verview:
The Pico family of products are revolutionary FPGA based embedded acceleration platforms.
With performance that often exceeds modern microcomputers, a shockingly small form factor,
and nominal power consumption that is less than one watt, the Pico family of products take
computing to a whole new level.
The Pico E-15 is based on the high-performance Virtex-4 FPGA chip. This device has the
performance and power consumption of a custom chip (ASIC), but is completely
reconfigurable! The E-15 features four high speed converters and direct video capture.
Advanced users will enjoy the open source development kits which allow absolute control over
the hardware. For those who desire a more high level approach to firmware, Viva provides a
graphical development model. Impulse C™ support is also included for rapid firmware
development in the C programming language. Board support packages are available for
operating systems such as Linux, µC/OS, Green Hills Integrity OS™ and VX Works.

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Pico E-15 Quick Reference Datasheet
FEATURES
♦ High-performance Virtex-4 FX-20, 40 or 60
♦ 256MB RAM
♦ 64MB Flash ROM
♦ Dual 12-Bit 125 MSPS A/D converters
♦ Dual 14-Bit 210 MSPS D/A converters
♦ Integrated composite video capture
♦ CardBus (PCI) Interface
♦ Open source
♦ Standalone operation
♦ Reconfigurable, high-speed digital bus
FPGA FEATURES
♦ Embedded PowerPC™ P405 processor
♦ Integrated DSP logic
♦ Integrated RAM
APPLICATI NS
♦ Software defined radio
♦ Video processing / compression
♦ Accelerated scientific computing
♦ Digital signal processing
♦ Impulse C™ development platform
♦ Viva development platform
♦ Embedded systems
♦ Encryption / decryption
♦ Supercomputing / cluster computing
I Connectivity
♦ 10/100/1000 Ethernet
♦ RS-232 Asynchronous Serial
♦ JTAG
♦ SVIDEO/Composite In
♦ Dual High Speed Analog to Digital
♦ Dual High Speed Digital to Analog
♦ GPIO
MECHANICAL
Temperature Range 0°C to +70°C
PC Card Type II Form-Factor
Stainless steel case
P WER
Sleep 0.001W
Nominal 1.2W
Absolute Maximum 7.0W
Supply Voltage 3.3V
*Operation below -0°C requires throttled RAM timing

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Standard Part Numbers
Standard Part Number
FX-20 E15FX20-256/64/JEGSAADDV10C
FX-40 E15FX40-256/64/JEGSAADDV10C
FX-60 E15FX60-256/64/JEGSAADDV10C
A Military version is available which includes:
 BGA underfill
 Conformal coating
 Extended temperature range
The Military version is available by special order only, and is subject to minimum quantity
requirements.

Pico E-15 Hardware Reference www.picocomputing.com Pico Computing
[phone] 150 Nickerson Street. Suite 311
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System Architecture
At the core of the Pico E-15 is a Virtex-4 FPGA. The FPGA can be dynamically configured to
perform any number of specialized tasks such as protocol processing, encryption, or complex
mathematical functions. Embedded systems benefit from the integrated PowerPC™ processor.

Pico E-15 Hardware Reference www.picocomputing.com Pico Computing
[phone] 150 Nickerson Street. Suite 311
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Pico E-15 Electrical Specification
Minimum Nominal Maximum
DC Input Voltage 3.25V 3.3V 3.35V
Power Consumption 0.001W 1.2W 7.0W
DC Input Current 0.0003A 0.36A 2.1A
Recommended Temperature Range 0°C 10°C 70°C
FPGA Over Temperature Shutdown 70-80°C
Maximum Storage Temperature Range -50°C 27°C 90°C
Relative Humidity (Non-Condensing) 0% 95%
verpower Considerations:
The Pico E-15 FX60 is designed desktop computers, and is not recommended for use in
laptops. Because of the large gate count of the FX60, it can easily exceed the PCCARD
maximum current consumption specification of 1A. The FX-60 features built in over-
temperature shutdown to protect both the card and the host system.
The Pico E-15 FX60 should be used with an external heat sink and an extender card.

Pico E-15 Hardware Reference www.picocomputing.com Pico Computing
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Field Programmable Gate Array
The core of the Pico E-15 is a high performance Virtex-4 FPGA. Included in the FPGA are the
FPGA Fabric, an optional PowerPC ™ processor, ultra high-speed DSP slices and RAM.
FPGA Fabric:
The “Fabric” of an FPGA comprises an array of logic elements that can be connected in
virtually unlimited patterns. These patterns of logic elements can be used to perform basic
mathematical functions such as addition and subtraction, or can be grouped together to
perform complex functions like Fast Fourier Transforms. Logic elements can even be
connected to create a custom soft processor.
The advantage of the FPGA is that the internal logic can be optimized for a specific
application. FPGAs are also able to execute operations in parallel, not being limited by
sequential execution like a traditional processor. FPGA operations can be executed in a
parallel, pipelined or even an asynchronous manner. The FPGA allows incredible application
speed with very low power consumption. Your imagination is really the limit.
DSP Slice:
Embedded within the FPGA are special areas that are designed to facilitate high speed “digital
signal processing.” These areas are called DSP slices. The DSP slice can be configured in a
variety of different ways. For example, one DSP slice can be configured to be one tap of an
FIR filter. DSP slices are fully pipelined and feature incredible speed. When configured for FIR
filtering the DSP slice has a guaranteed performance of 500MHz with a latency of one cycle.
An 18x18 multiply and accumulate also runs at 250MHz with a latency of two cycles. Smaller
data widths allow higher clock speeds.
FPGA Resources:
Free FPGA Cores http //www.opencores.org
Encryption Cores http //www.openciphers.org
Virtex-4 Website http //www.xilinx.com/virtex4

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[phone] 150 Nickerson Street. Suite 311
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PowerPC™ Processor
PPC405x3 Processor Introduction:
FPGAs are renowned for their ability to process parallel logic, but they typically have a hard
time emulating a high performance processor. To get the best of both worlds the Virtex-4™
features an embedded Power PC Processor. Since the processor shares the same die as the
FPGA it seamlessly interfaces with the FPGA fabric.
A new feature of the Virtex-4 FPGA is the addition of an auxiliary processor interface. The APU
is the highest speed interface between the PowerPC™ processor and the FPGA fabric. Up to
four custom instructions may be implemented in the FPGA, which are accessible from the
PowerPC™.
Board support packages are currently available for µ C/OS and Linux. Board support source
code is available open source under the GPL.

Pico E-15 Hardware Reference www.picocomputing.com Pico Computing
[phone] 150 Nickerson Street. Suite 311
Seattle, WA 98109
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CPLD TurboLoader
A CPLD (Complex Programmable Logic Device) is a smaller version of an FPGA (described
above) with permanent Flash storage built in. The Pico E-15 contains one CPLD that loads
and reconfigures the FPGA. The Pico firmware guide describes how to access the CPLD
TurboLoader.
The Flash ROM’s address bus can be controlled by either the TurboLoader or the FPGA (but
not both). During power-up or reboot, the TurboLoader is in control of the Flash ROM Address
bus. At all other times the FPGA is in control of the address bus.
CPLD Resources:
Xilinx CPLD Website http //www.xilinx.com/cpld

Pico E-15 Hardware Reference www.picocomputing.com Pico Computing
[phone] 150 Nickerson Street. Suite 311
Seattle, WA 98109
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Flash Memory
The Pico E-15 comes equipped with at least 64MB of Flash ROM. The Flash ROM is divided
into 512 sectors that can be erased independently. Most of the space on the ROM is reserved
for the user.
The Flash ROM’s address bus can be controlled by either the TurboLoader or the FPGA (but
not both). During power-up or reboot, the TurboLoader is in control of the Flash ROM Address
bus. At all other times the FPGA is in control of the address bus.
The Flash ROM has a simple, open file system which allows the user to store FPGA images,
ELF binary files, or other data. The primary image is used to boot the FPGA initially, and the
backup image is only invoked if the primary image fails to load correctly. Executable files are in
ELF format and are loaded by a loader within the secondary image. The primary image will
either load the secondary image or pause for the PC to access and manage the file system.

Pico E-15 Hardware Reference www.picocomputing.com Pico Computing
[phone] 150 Nickerson Street. Suite 311
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DDR2 SDRAM Memory
The Pico E-15 comes equipped with 256MB of DDR2 SDRAM memory. There are two 1024Mb
chips, each with a separate 16 bit data path to the host to form one 32 bit bank. From 0°C to
+85°C, the ram can run at up to 333 MHz. For operation at temperatures below 0°C, special
firmware with throttled ram timings is required. Please note that the RAM will not function
below 125 MHz.
Virtex-4 FPGA
RAM
MSBs
RAM
LSBs

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RAM Timing and Parameter Information
Parameter Value EDK Value
133 MHz
EDK Value
333 MHz
Registered No 0 0
Clock Pairs 1 1 1
Memory Banks 1 1 1
IDELAY Controllers 2 2 2
Differential DQs Yes 1 1
Open Row Management No 0 0
On Die Termination Disabled 0 0
ECC Support No 0 0
TMRD 2 Clocks 15000 6000
TWR 15 nS 15000 1500
TWTR 7.5 nS 1 3
TRAS 45 nS 45000 45000
TRC 60 nS 60000 60000
TRFC 127.5 nS 12750 12750
TRCD 15 nS 15000 15000
TRRD 10 nS 10000 10000
TRP 15 nS 15000 15000
TREFI 7.8 uS 7800000 7800000
TFAW 37.5 37500 37500
CAS Latency 5 Clocks 5 5
Data Width 32 Bits 32 32
Address Width 13 Bits 13 13
Column Width 10 Bits 10 10
Bank Address Width 3 3 3
Clock Period* 5 nS 7500 3000
*Minimum RAM Speed is 125MHz

Pico E-15 Hardware Reference www.picocomputing.com Pico Computing
[phone] 150 Nickerson Street. Suite 311
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Temperature Sensor
The Pico E-15 contains one temperature sensor that directly senses the die temperature of the
Virex-4 FPGA. The digital interface of the remote temperature sensing chip is connected to the
Cypress PSoC. If an overtemperature condition occurs, the PSoC will shutdown the FPGA
until the temperature has dropped sufficiently below the shutdown threshold.
The setpoints of the temperature shutdown circuit can be reprogrammed via the PSoC debug
cable.
Electrical Specifications Minimum Nominal Maximum
Temperature Sensing Range -55°C 125°C
Resolution 0.0625°C
Accuracy +/- 2.4°C +/- 1.0°C +/- 0.0°C

Pico E-15 Hardware Reference www.picocomputing.com Pico Computing
[phone] 150 Nickerson Street. Suite 311
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Sleep Controller
The Pico E-15 contains one Cypress PSoC which is used to generate a clock for the
bootloader and control the power state.
The E-15 can be placed in a state where it draws almost no power, then wakes up
automatically after a set amount of time.
The sleep controller can be activated by the FPGA, or the external peripheral interface
connector.
The protocol for entering sleep state is simple. Simply pulse FPGA_POWERCTL_C for as
many seconds as your wish to sleep, then lower the FPGA_POWERCTL_D signal.
The Pico E-15 will awake from sleep if any of the following conditions are true
-Power is first applied
-The sleep timer has run out
-POWERCTL_D is low and POWERCTL_C is high
The Pico E-15 will enter sleep mode if any of the following conditions are true
-An overtemperature condition is detected
-The FPGA_POWERCTL_D pin is low
-The POWERCTL_C pin is low

Pico E-15 Hardware Reference www.picocomputing.com Pico Computing
[phone] 150 Nickerson Street. Suite 311
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Tri-Mode Ethernet Interface
The Pico E-15 features the Marvell Alaska series 88E1111 tri-mode Ethernet transceiver.
Combined with the on-FPGA MAC (Middle access controller) a complete Ethernet solution is
offered. Communication between the MAC and PHY takes place over an industry standard
MII/GMII interface.
The Ethernet transceiver features 10/100/1000 full/half duplex operation. It will automatically
configure the physical interface on the fly for crossover or straight through operation. The PHY
can even automatically correct for common wiring mistakes. The PHY has a built in Time
Domain Reflectometer which can diagnose cable problems and pinpoint their distance away
from the transceiver.
The Ethernet interface on the Pico is magnetic-less allowing high speed, low power digital
interconnect directly to Ethernet backplanes. DO NOT directly connect the Ethernet interface
to a hub or switch without a magnetic isolation module.
The Marvell 88E1111 is the only user-accessible chip on the Pico E-15 that requires an NDA
for access to the datasheets. If you are interested in some of the advanced features not
supported by the native driver, contact Pico Computing for assistance in obtaining an NDA
from Marvell. Users are advised not to contact Marvell directly.
Ethernet Resources:
Marvell 88E1111 Webpage http //www.marvell.com/products/transceivers/singleport/88e1111.jsp

Pico E-15 Hardware Reference www.picocomputing.com Pico Computing
[phone] 150 Nickerson Street. Suite 311
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Digital Peripheral Interface
The Pico E-15 features 2 GPIO lines which are used for external peripheral support. The GPIO
lines are always enabled.
All GPIO signals have user selectable pull-up, pull-down, keeper or HI-Z termination. Drive
strength is also user selectable between 2 and 24mA. All GPIOs can be configured for input,
output and bi-directional mode.
GPIO 1 has a 50 ohm resistor in series with the output to allow connectivity with low voltage
devices which may clamp a 3.3V signal.
Electrical Specifications Minimum Nominal Maximum
High Voltage 2.0V 3.3V 3.45V
Low Voltage -0.2V 0V 0.8
Input Impedance (Pulldowns Disabled) HI-Z
Drive Strength (Selectable) 2 mA 24 mA
ESD Withstand Voltage (Human Body Model) 2 KV

Pico E-15 Hardware Reference www.picocomputing.com Pico Computing
[phone] 150 Nickerson Street. Suite 311
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High Speed Analog to Digital Converters
The Pico E-15 features 2 high speed analog to digital converters. The converters are optimized
for high-frequency, high-performance, low-power, low-noise operation. The converters have
integrated DC blocking capacitors, and thus, cannot be used on very low frequency signals.
The ADC should be driven by a source with an impedance of 50 ohms.
To ensure accuracy at high speeds, the low-jitter 125 MHz reference clock must be used. The
converters may be tuned to different applications. For example a lower termination impedance
may be traded for more sensitivity. A wider high frequency input range may be traded for less
high frequency noise rejection. Contact Pico Computing with your application requirements.
The data returning from the ADCs must be sampled on the rising edge of the appropriate clock
return pin. Even when the ADCs are clocked from the same source, they will be running out of
sync because of the duty cycle stabilizer (which provides greater resolution). The Pico E-15
can be special ordered with the duty cycle stabilizer perminately disabled.

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Electrical Specifications Minimum Nominal Maximum
Differential AC Input Voltage 0 Vpp 1 Vpp 1.8 Vpp
Termination Resistance 45 (VHF) 50 (AC) 115(DC)
Input Frequency Range 1 KHz* 1-50 MHz 125 MHz
Bandwidth 125 MHz 225 MHz
Dielectric Surge Withstand Voltage -14 VDC 0 VDC 14 VDC
Withstand Voltage -4 VDC 0 VDC 4 VDC
Clock Frequency 125 MHz 125 MHz
Resolution 12 Bits
Sensativity 0.087V 0.013V 0.007V
*Lower requencies are possible with degraded per ormance.
ADC Front-End Equivalent Circuit

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ADC Low Frequency Input Impedance
ADC High Frequency Input Impedance*
*Low pass filter range is customizable via special order