Plessey PM-DZ11 User manual

PM-DZII
Asynchronous Multipl~xer
Manual
Plessey
Peripheral
Systems

PM-DZII
Asynchronous Multipl~xer
Manual
Plessey
Peripheral
Systems

"
,~
PM-DZll
Asynchronous Multiplexer
Manual
April 1980 - Revision A
Copyright ~ Plessey peripheral Systems
0-0
MA 701885 REV A

Contents
SECTION 1 - GENERAL INFORMATION
1.1 INTRODUCTION .•••••••.••••••••••••••••••••••••••••••••.•
1.2 GENERAL DESCRIPTION ••••••••••••••••••••••••••••••••••••
1. 3 FEATURES •••...••••••.••••••.••••••••••••••••••••.••••••
1.4 PHYSICAL DESCRIPTION ••.•••••.•.•.•••.••••••.••••••..•••
1.5 CONFIGURATIONS ..•.•.••••••••••••••••••.••••••.••••.••••
1.5.1 EIA Models •.•.••••••••••••••••••••••••••.••.••••
1.5.2 Current Loop Models •••.••••.•••••••••.•••••.••••
1.5.3 Hardware Descriptions ••.••..•••••••••••••••.••••
1.5.4 Test Connectors ..•••••••••.•••••••••••••••••••••
1.6 FUNCTIONAL DESCRIPTION .••••.•.•••••••.•••.•••••.••.••••
1.6.1 Unibus Interface •••••••••••••••••••••••••••.••••
1.6.2 Control Logic ••••.•••.•••••••••••••••••••.••••••
1.6.3 Line Interface ••••••••••.•••••••••••••••••••••••
1. 7 SPECIFICATIONS •••••..••••••••••.•.••••••••••••.•.••••••
1. 7.1 Performance Parameters •..•••...•••.•..•...•.••••
1. 7 . 2 Output s. • • • . • . • . • . • • • . • • . • • • • • • • • . • • • • • • • • • • . • • •
1.7.3 Inputs ••.••...•.••••••••.•••••...•••••••••••••.•
1. 7.4 Power Requirements •.••••••.•.•.••••••.••..••.••.
1.7.5 Environmental Requirements ••••.•••••.•••••••.•••
1. 7.6 Distortion •••.••••.•••••••.•••.•••••••••••••••••
1-1
1-1
1-2
1-3
1-4
1-4
1-5
1-6
1-6
1-8
1-8
1-9
1-10
1-10
1-10
1-11
1-12
1-12
1-12
1-13
1.7.7 Interrupts...................................... 1-13
2.1
2.2
2.3
1.7.8 Line Speed...................................... 1-13
SECTION 2 - INSTALLATION AND OPERATION
GENERAL INFORMATION ...•••.••••••••..•••••.•••••••.•••.•
UNPACKING AND INSPECTION ..•••••••••••••••••..••..•.•..•
INSTALLATION ••••••...•..••.••••••••••••••••.•.....•••••
2.3.1 PM-DZIIA or PM-DZllC Panel Installation •.•.•••••
2.3.2 PM-DZllE or PM-DZllF Panel Installation •..••.•••
2.3.3
2.3.4
2.3.5
PM-DZllB or PM-DZ11D Filter Installation ..•.••.•
Logic Board Assembly Installation ••.•••••••..•••
Diagnostic Testing .•••••••••••.••••••••••••.•••.
SECTION 3 - PROGRAMMING
2-1
2-1
2-2
2-2
2-4
2-4
2-6
2-6
3.1 INTRODUCTION. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 3-1
3.2 ADDRESS AND VECTOR SPACE ASSIGNMENTS................... 3-1
3.3 REGISTER BIT ASSIGNMENTS............................... 3-4
3.3.1 Control and Status Register (CSR) - ~.......... 3-4
0-1
MA 701885 REV A

3.4
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
Receive Buffer Register (RBUF) - R2 •••••••.•••••
Line Parameter Register (LPR) - R2 ••••••••••••••
Transmit Control Register (TCR) - R4 ••••••••••••
Modem status Register (MSR) - R6 •.••••••..•••••••
Transmit Data Register (TOR) - R6 ••.••••...•.•..
POOGRAMMING ••••••••••••••••••••••••••••••••••••••••••••
3•4 •1 Baud Rate ...................................... .
3.4.2 Character Length, stop Bits, and Parity .••••.•.•
3.4. 3 Interrupts ..................................... .
3.4.4 Emptying the FIFO ••••••••••••••••••••••.••••••••
3.4.5 Data set Control (EIA Operation Only) ••.••...•••
SECTION 4 - FUNCTIONAL DESCRIPTION
3-6
3-7
3-9
3-9
3-9
3-10
3-10
3-10
3-10
3-11
3-11
4.1 INTRODUcrION. • • • • • • • • • • • • • • • • • • . . • • • • . •• . • . . • • . • • . . • • • • 4-1
4.2 PM-DZll LOGIC MODULE................................... 4-1
4.3 UNIBUS INTERFACE....................................... 4-1
4.3.1 Address Selection............................... 4-1
4.3.2 Register Selection.............................. 4-4
4.3.3 Data Lines...................................... 4-4
4.4 INTERRUPT CONTROL...................................... 4-4
4.4.1 vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.5 DATA CONTROL........................................... 4-6
4.5.1 PM-DZllA, B, and E Registers (EIA
versions Only).................................. 4-6
4.5.2 PM-DZllC, 0, and F Registers (CUrrent
wop Orlly)...................................... 4-7
4.5.3 FIFO............................................ 4-8
4.5.4 Baud Rate Generation............................ 4-8
4.6 DATA CONDITIONING...................................... 4-8
4.6.1 Universal Asynchronous Receiver/Transmitter
(UART) • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 4-8
4.6.2 Data Level Conditioning ••••.•••••••••.••••••••••
4.6.3 Distribution ................................... .
MA 701885
REV A 0-2
4-12
4-12
• I '

2-1 :
2-2 :
2-3:
2-4 :
2-5 :
3-1 :
3-2 :
1-1 :
1-2 :
1-3:
1-4 :
1-5 :
1-6 :
1-7:
1-8:
1-9:
2-1:
2-2:
4-1 :
4-2 :
4-3:
4-4 :
4-5 :
Tables
ITEMS SUPPLIED PER EIA CONFIGURATIONS ••••.••••••••••••
ITEMS SUPPLIED PER CURRENT LOOP CONFIGURATIONS ••••••••
ADDRESS SELECTION CHART ••••••.•••••••••••..•••••.•••••
VECTOR SELECTION CHART •.•••••••.••••.••••••.••••••••••
CABLES USED FOR CONNECTION TO LOCAL TERMINALS •••••••••
DEVICE ADDRESS/VECTOR SEQUENCES •••••••••••••••••••••••
BAUD RATE SELECTION CHARI' •••••••••••••••••••••••••••••
Figures
APPLICATIONS FOR THE PM-DZll ••••••••••••••••••••••••.•
BASIC PM-DZl1 •....•••...•..••.• ' •...•••.•.•..••.••..••.
REQUIRED HARIMA.RE ••••••.••••••••••••••••••••••••••••••
CURRENT LOOP MODEL HARIMARE •••••••••••••••••••••••••••
TU.RN'AROUND ••••••••••••••••••••••••••••••••••••••••••••
PM-H325 TEST CONNECTOR (P/N 701587-100A) ••••••••••••••
PM-H3271 TEST CONNECTOR (PIN 701792-100X2) ••••••••••••
PM-3190 TEST CONNECTOR (P/N 703315) ••••••••••.••••••••
GENERAL FUNCTIONAL BLOCK DIAGRAM ••••••••••••••••••••••
PM-DZIIA AND B OR PM-DZIIC AND D INSTALLATION •••••••••
PM-DZI1E OR PM-DZIIF INSTALLATION •••••••••••••••••••••
FUNCTIONAL PM-DZ11 BLOCK DIAGRAM ••••••••••••••••••••••
UNIBUS INTERFACE LOGIC BLOCK DIAGRAM ••••••••••••••••••
INTERRUPT LOGIC BLOCK DIAGRAM ••••• " ••••••••••••••••••••
FORMAT OF TYPICAL INPUT/OUTPUT SERIAL CHARACTER •••••••
UART TRANSMITTER, BLOCK DIAGRAM AND
2-1
2-2
2-7
2-8
2-9
3-2
3-8
1-2
1-3
1-4
1-5
1-6
1-7
1-7
1-8
1-9
2-3
2-5
4-2
4-3
4-5
4-9
SIMPLIFIED TIMING DIAGRAM............................. 4-10
4-6: UARl' RECEIVER, BLOCK DIAGRAM AND
SIMPLIFIED TIMING DIAGRAM............................. 4-11
0-3
MA 701885 REV A

Section 1
General Information
1.1 INTRODUCTION
This manual provides the information needed to install and
operate the PM-DZll multiplexed asynchronous serial line
interface manufactured by Plessey peripheral Systems, Irvine,
california.
The material in this manual is arranged into four sections as
follows:
Section 1 - GENERAL INFORMATION. This section contains a
brief description of the PM-DZll, its configurations, and a
list of specifications.
Section 2 - INSTALLATION AND OPERATION. This section explains
the requirements and procedures for equipment installation.
Interface information and switch settings are provided.
Section 3 - PROGRAMMING. A description of the PM-DZll control
registers and programming features is presented to aid user
programming.
Section 4 - FUNCTIONAL DESCRIPTION. This section provides a
functional description of the PM-DZll and includes signal
functions, block diagrams, and timing diagrams.
MAINTENANCE DRAWING PACKAGE. A separate drawing package,
MD 701885, contains the parts lists, logic diagrams, and
assembly drawings required for a complete understanding of
the PM-DZll.
1.2 GENERAL DESCRIPTION
The PM-DZll is an asynchronous interface that connects a
PDP-ll CPU to 8 or 16 asynchronous serial lines.* It is a
low cost, multiplexed program controlled interface for
connection of multiple local or remote terminals at moderate
throughput. Local operation to terminals or computers is
possible at speeds up to 9600 baud using EIA RS232C interfaces
*PDP-ll is a registered trademark of Digital Equipment
Corporation.
1-1 MA 701885 REV A

or 20mA current loop. Remote operation using the public
switched telephone network is possible with EIA models. Data
set control is provided to permit auto answer (dial-up)
operation with modems capable of full-duplex operation (e.g.,
Bell Models 103 or 113). Remote operation over private lines
for full duplex point-to-point or full duplex multipoint (as
a master control station) is also possible. The PM-DZll does
not support half-duplex operations with secondary transmit
and receive operations. Half-duplex modems, such as the Bell
202, can be used on leased lines with the latter restrictions.
Figure 1-1 shows two possible applications for the PM-DZll.
Further applications are inherent in these figures.
PM-DZll
IISYNCHRONOUS
MULTIPLEXER 201nA
PM-DZll
ASYNCfRONOUS
MULTIPLEXER BIA
FIGURE 1-1:
1. 3 FEATURES
ACTIVE TO
PASSIVE
ADAPTER
PM-DZll
SYSTEM
PM-DZll SYSTEM
APPLICATIONS FOR THE PM-DZll
Some of the features of the asynchronous interface are:
• Low cost 8 and l6-line multiplexed asynchronous interface
for connecting Unibus PDP-lIs to terminals or other
computers.
• EIA and 20mA current loop models available.
• Local operation at speeds up to 9600 baud for maximum
responsiveness of CRT terminals.
MA 701885 REV A
1-2

• Data set control on EIA models for full duplex dial-up
remote operation.
• Programmable line speeds and character formats on a per
line basis for flexibility and ease of configuration.
• FIFO buffered input transfers for reduced interrupt
overhead and improved latency; program interrupt output
transfers for low cost.
• Compact, single PC board, 8-line modularity.
• l6-line cable distribution panel conserves cabinet space.
1.4 PHYSICAL DESCRIPTION
The PM-DZII (8-line configuration) is comprised of a single
hex small peripheral controller (SPC) module, a 5.25 inch
unpowered distribution panel, and a IS-foot interconnecting
cable. A l6-line confignration uses two modules and a single
distribution panel which is connected by two ribbon cables.
The basic PM-DZII module, cables, static filter panel, and
distribution panel are shown in Figure 1-2.
STATIC FILTER
PM-BC06K-OJ (2OmA)
PM-BCOGL-OJ (EIA)
LOGIC MODULE
17
PM-Bcoes (20mA)
PM-BCOSW (EIA)
STATIC FILTER PANEL
lllllLLLLLLLLLLL
f#9..&y<f?Pfri>
DISTRIBUTION PANEL
PM-BCOGL-OS
FIGURE 1-2: BASIC PM-DZII
1-3
MA 701885 REV A

1.5 CONFIGURATIONS
The PM-DZll is available in six different configurations. EIA
models are PM-DZIIA, B, and E. Current loop models are
PM-DZIIC, D, and F.
1.5.1 EIA Models
The PM-DZIIA is an 8-line configuration with EIA RS232C
interface. It consists of a logic module, distribution panel,
and interconnecting cables. The PM-DZIIB consists of an
additional logic module, filter, and cables which expand the
PM-DZIIA to a 16-line configuration. The PM-DZIIE is a
16-line configuration and is a combination of the PM-DZ11A
and PM-DZIIB. Figure 1-3 shows the required hardware for
various configurations.
I I
LOGIC BOARD
I
LOGIC BOARD
PIN 701640-100
I I PIN
701640-100
I I
( L I I J \
1 PIN
701608-100
I I \
I
STATIC FILTER I
~
PANEL
~
STATIC FILTER
PIN
701663-100
PiN 859798-1
I STATIC FILTER I I
I 1
2 ( 1
_P~ 20~5~-~0?.. ~- - - -:)-_ ~-_- _
1 ...
I 8
lines
I 8,
l~nes
I
DISTRIBUTION PANEL
~/
PiN 701651-100
16 lines
L.
-- -- - -- -------------
- --
DATA SET
l
WCAL
TERMINAL
I
_ I
..,
_I
PM-DZllC ~ PM-DZllA .~ PM -DZllB
TO TELEPHONE LINES
FIGURE 1-3: REQUIRED HARDWARE
MA 701885 REV A
1-4

1.5.2 CUrrent Loop Models
The PM-DZIIC is an 8-line configuration with a 20mA current
loop interface. It consists of a logic module, distribution
panel, and interconnecting cables. The PM-DZIID consists of
additional logic module, filter, and cables which expand the
PM-DZIIC to a 16-line configuration. The PM-DZIIF is a
16-line configuration and is a combination of the PM-DZIIC
and PM-DZIID. Figure 1-4 illustrates the required hardware
for the 20mA model configurations.
<
UNIBUS "'-
----,--~---r--V
,---j---- ,---j----
I
I
I
L
PM-DZllC I PM-DZllD
I I
LOGIC BOARD
1
LOGIC BOARD
I
PIN 703210-100
I I PIN
703210-100
I
( L I I J \
I PIN
701461-100
l I I \
STATIC FILTER I
I
PANEL
~
I
ex
STATIC FILTER
PIN 701663-104
PIN 841918-1
I STATIC FILTER I I
I I
) ( I PIN
701781-100 '- - - -)- ~- -
r
----------.:r- --
,
I tl.ll.neS
I I 8
li'les
I
DISTRIBt~ION PANEL
"'-/
16 lines
-- --
--------------------
_I
PM-DZl1F • PM-DZ11C AND PM-D
ZllD
LOCAL
TERMINAL
FIGURE 1-4: CURRENT LOOP MODEL HARDWARE
Maximum configuration allows 16 PM-DZIIE/F modules per Unibus
for 128 lines of communication.*
·Unibus is a registered trademark of Digital Equipment
Corporation.
1-5
MA 701885 REV A

1.5.3 Hardware Descriptions
The distribution panel provides 16 communication lines using
Cinch DB25p connectors, from two modules (8 lines per module),
and is included with the PM-DZllA/C and PM-DZllE/F
configurations. The PM-DZll logic module plugs into any hex
SPC slot of the CPU or expansion chassis. The distribution
panel requires no power and can be mounted in a standard
19-inch wide cabinet. The static filter panel is used to
prevent problems caused by electrostatic discharge. A 50
conductor, f.lat, shielded cable, connects the logic module to
the static filter. A second cable connects the static filter
to the EIA distribution panel. The cables to modems and/or
local devices are not provided with the basic PM-DZll. See
Table 2-5 for recommended cables for data set and/or local
terminal interconnections.
1.5.4 Test Connectors
Two accessory test connectors are provided with each PM-DZllA
and PM-DZllE. The PM-H325 test connector plugs into an EIA
connector on the distribution panel or on the end of the
modem cable to loop back data and modem signals on a single
line. The PM-H327l connected to the module with the interface
cable staggers the data and modem lines as shown in Figure
1-5. The EIA test connectors are shown in Figures 1-6 and
1-7. Refer to Sections 2.3.4 and 2.3.5 for use of test
connectors.
A priority level insert plugs into a socket on the logic
module to establish interrupt levels on the Unibus.
TRANS
~
RECI
DTR
~
RI 1
CO 1
CO
~
RI
~
DTR 1
REC
~
TRANS 1
NOTE: Lines 2 and 3, 4 and 5, 6 and 7 are staggered the
same way.
FI GURE 1-5: TURNAROUND
MA 701885 REV A
1-6

I {.~c.?g 11 ~
•• -'-'-'-~:.:.! •• /I
PM-DZllE LINES
PM-H325* I
PM-DZllA LI~ES
PM-DZllB LINES
........ " I
I
~1h
I ~~~~
~~~~
~~~~
f I I
I I I
I I I
I I I
I I'
• I :
I I
J5~
Jl J3
J9
Jll
J13 Jl5
J2
J5 J6 J8 JlO Jl2 Jl4 Jl6
r::
*'
c ::I C = C
::I
J17
Jl8 Jl9
J20
*NOTE: PM-H325 test connector is testing line
5.
FIGURE 1-6: PM-H325 TEST CONNECTOR (piN 701587-100A)
TERMINATING PM-DZllA TEST BOARD
AND INTERCONNECT CABLE
BOIIRD
"AU
TO LOGIC BOARD (RIBBED SIDE DOWN)
TERMINATING PM-DZllE TEST BOARD
AND INTERCONNECT CABLES
TO LOGIC
BOARD "3"
FIGURE 1-7: PM-H3271 TEST CONNECTOR (PIN 701792-100X2)
1-7
MA 701885 REV A

The PM-DZllC and PM-DZllD also have a staggered turnaround
test connector (PM-3l90) which is connected to the logic board
via the PM-BC08S cable. The PM-3l90 staggers the data lines
as shown in Figure 1-5. Figure 1-8 illustrates the PM-3l90
test connector. A priority level insert plugs into a socket
on the logic board to establish interrupt levels on the Unibus.
TERMINATING PM-DZllC TEST BOARD
AND INTERCX>NNECT CABLE
FIGURE 1-8: PM-3l90 TEST CONNECTOR (PIN 703315)
1.6 FUNCTIONAL DESCRIPTION
The PM-DZll can be defined as three basic components: Unibus
interface, control logic, and line interface. These basic
structures are illustrated in a general block diagram shown
in Figure 1-9.
1.6.1 Unibus Interface
All transactions between the Unibus and the PM-DZll control
logic are related to the PDP-II Unibus interface which performs
data handling, address recognition, and interrupt control. The
following explanations apply:
• Data Handling -The Unibus sends data to and from registers
in the control logic and provides the
voltage signals which determine transmission
or reception of data to and from the Unibus.
MA 701885 REV A 1-8

• Address Recognition - Preselected Unibus address recognition
activates the proper load (write) and
read signals which are used to route
the in/out data to the desired
locations.
• Interrupt Control
- This function initiates and controls
interrupt processing between the
DZll and the CPu.
0
1---------
"I
1 1
---------
1------------------
1
UNIBUS
1 1 1 LINE
1
L'ONTROL
1 1
I
INTERFACE
INTERFACE
1
LOGIC
1 1
1 1 1 1
1 1 1
CONTRO
y 1
INTERRUPT
~
SCANNER
-t -.l.-
CLOCK TO
,-
CONTROL
1 1
CONTROL
1 1 1 1
1 1 1
1 1
1 1 1 1
1 1 1 1
1 1 1
1 1
II)
1 1 FIFO LINE
::J
'"
1
BUFFERS
it
1
~ DATA
1
DATA
1 1
TO
XCURS
.1
REGISTERS
1
UART
XCUHS
-( +
MUX
~,..
1 1 -
--
1 1
1 1 I
1 1
'--- ______ 1
1 1
1
---------------
- --
1 1
1 1
1 1
1 I
ADDRESJ
1
'7
I
ADDRESS
1
('
SELECT
1
1 1
1 _________ 1 DISTRIBUTION
PANEL
FIGURE 1-9: GENERAL FUNCTIONAL BLOCK DIAGRAM
1.6.2 Control Logic
Receiver and transmitter timing and control signals are
generated by the control logic which consists of the scanner
and the registers.
Information from the line interface and registers is
continuously analyzed by the scanner which produces data flow
to or from the appropriate line. The scanner consists of
a clock and a four-phase clocking network.
1-9
MA 701885 REV A

Four device registers are utilized to provide six l6-bit
accessible registers. The device registers store input/output
data, monitor control signal conditions, and establish
operating status. The registers are accessible in bytes
and/or words and (depending on operation) can be read or
written, which extends the use of two of the device registers
to four independent registers.
1.6.3 Line Interface
The PM-DZll is located between the Unibus parallel data path
and serial data paths (terminals or telephone lines). The
line interface provides serial to parallel and parallel to
serial data format conversion. Conversions for each line in
the PM-DZll are performed by independent universal asynchronous
receiver/transmitter (UART) integrated circuits. The line
interface also allows the line receiver or driver to convert
TTL voltage levels in the PM-DZll to correspond to external
device input lines.
1.7 SPECIFICATIONS
1.7.1 Performance Parameters
Operating Mode:
Data Format:
Character Size:
Parity:
Bit Polarities:
Data Signal:
Control Signal:
Order of Bit:
Baud Rates:
MA 701885 REV A
Full-duplex
Asynchronous, serial by bit, 1 start and
1, 1 1/2 (5-level codes only) or 2 stop
bits supplied by the hardware under
program control
5, 6, 7 or 8 bits. Program selectable.
(Does not include parity bit.)
Even, odd or none. Program selectable.
UNIBUS
Low = 1
High = Ji1
Low = 1
High = Ji1
INTERFACE
High = 1
Low = ~
High = 1
Low = Ji1
EIA OUT
Low = 1 = Mark
High = ~ = Space
Low = OFF
High = ON
Transmission/reception low-order bit
first
50, 75, 110, 134.5, 150, 300, 600, 1200,
1800, 2000, 2400, 4800, 7200, and 9600
1-10

Break:
can be generated and detected on each
line.
Throughput:
21,940 characters/second = (bits/second
x number of lines x direction)/
(bits/character)
Example: (9600 x 8 x 2}/7 = 21,940
characters/second
( NOTE)
The theoretical maximum is 21,940.
Actual throughput depends on other
factors, such as type of CPU, system
software, etc.
1.7.2 Outputs
• EIA
Each line provides voltage levels and
connector pins that conform to Electronic
Industries Association (EIA) standard
RS232C and CCITT recommendation V.24.
The leads supported by this option are:
Circuit
AA
(CCITT 101) Pin
1
Protective Ground
Circuit
AB
(CCITT 102)
Pin 7 Signal Ground
Circuit BA
(CCITT 103) Pin 2 Transmitted Data
Circuit
BB (CCITT 104) Pin
3
Received Data
Circuit
CD (CCITT 108.2) Pin
20
Data Terminal Ready
Circuit
CE (CCITT l25)
Pin 22 Ring Indicator
Circuit
CF
(CCITT 109)
Pin 8 carrier
( NOTE)
Signal ground and protective ground
are connected.
Circuit CA (CCITT 105 - Request to
Send) is connected to circuit CD
(DTR) through a jumper on the
distribution panel. This allows
control of the Request to Send line
for full-duplex modem applications
that use the RTS circuit.
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MA 701885 REV A

• 20mA Current Loop
1. 7. 3 Inputs
Each 20mA channel provides the
current for the two pairs of signal
lines (transmit and receive). The
signals and associated pins are:
Receive +
Receive -
Transmit -
Transmit +
Pin 1
Pin 2
Pin 3
Pin 4
The
20mA line is connected to local
terminals (no data set control).
The line is active and drives only
passive devices.
The PDP-II Unibus is the input for all PM-DZlls. The PM-DZllA
or Band PM-DZllC or D present one unit load to the Unibus.
The PM-DZllE and PM-DZllF present two unit loads to the Unibus.
Four AC loads per module are presented to the Unibus.
1.7.4 Power Requirements
The PM-DZIIA or B and PM-DZIlC or D require the following
powers. The PM-DZllE and PM-DZllF require twice the following
values.
VOLTAGE
+ 5.0VDC
-15.0VDC
+l5.0VDC
CURRENT
TYPICAL
2.20 amps
0.13 amps
0.10 amps
MAXIMUM
2.50 amps
0.15 amps
0.13 amps
1.7.5 Environmental Requirements
Operating Temperature:
Relative Humidity:
MA 701885 REV A
5° to 50°C (41° to 122°F). Reduce
1.8°C/lOOO meters (l.ooF/lOOO feet)
for operation at altitudes above
sea level.
10% to 95% with maximum wet bulb of
32°C (90°F) and a minimum dewpoint
of 2°C (36°F).
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