Plessey PM-DZ11 User manual

PM-DZII
Asynchronous Multipl~xer
Manual
Plessey
Peripheral
Systems

PM-DZII
Asynchronous Multipl~xer
Manual
Plessey
Peripheral
Systems

"
,~
PM-DZll
Asynchronous Multiplexer
Manual
April 1980 - Revision A
Copyright ~ Plessey peripheral Systems
0-0
MA 701885 REV A

Contents
SECTION 1 - GENERAL INFORMATION
1.1 INTRODUCTION .•••••••.••••••••••••••••••••••••••••••••.•
1.2 GENERAL DESCRIPTION ••••••••••••••••••••••••••••••••••••
1. 3 FEATURES •••...••••••.••••••.••••••••••••••••••••.••••••
1.4 PHYSICAL DESCRIPTION ••.•••••.•.•.•••.••••••.••••••..•••
1.5 CONFIGURATIONS ..•.•.••••••••••••••••••.••••••.••••.••••
1.5.1 EIA Models •.•.••••••••••••••••••••••••••.••.••••
1.5.2 Current Loop Models •••.••••.•••••••••.•••••.••••
1.5.3 Hardware Descriptions ••.••..•••••••••••••••.••••
1.5.4 Test Connectors ..•••••••••.•••••••••••••••••••••
1.6 FUNCTIONAL DESCRIPTION .••••.•.•••••••.•••.•••••.••.••••
1.6.1 Unibus Interface •••••••••••••••••••••••••••.••••
1.6.2 Control Logic ••••.•••.•••••••••••••••••••.••••••
1.6.3 Line Interface ••••••••••.•••••••••••••••••••••••
1. 7 SPECIFICATIONS •••••..••••••••••.•.••••••••••••.•.••••••
1. 7.1 Performance Parameters •..•••...•••.•..•...•.••••
1. 7 . 2 Output s. • • • . • . • . • . • • • . • • . • • • • • • • • . • • • • • • • • • • . • • •
1.7.3 Inputs ••.••...•.••••••••.•••••...•••••••••••••.•
1. 7.4 Power Requirements •.••••••.•.•.••••••.••..••.••.
1.7.5 Environmental Requirements ••••.•••••.•••••••.•••
1. 7.6 Distortion •••.••••.•••••••.•••.•••••••••••••••••
1-1
1-1
1-2
1-3
1-4
1-4
1-5
1-6
1-6
1-8
1-8
1-9
1-10
1-10
1-10
1-11
1-12
1-12
1-12
1-13
1.7.7 Interrupts...................................... 1-13
2.1
2.2
2.3
1.7.8 Line Speed...................................... 1-13
SECTION 2 - INSTALLATION AND OPERATION
GENERAL INFORMATION ...•••.••••••••..•••••.•••••••.•••.•
UNPACKING AND INSPECTION ..•••••••••••••••••..••..•.•..•
INSTALLATION ••••••...•..••.••••••••••••••••.•.....•••••
2.3.1 PM-DZIIA or PM-DZllC Panel Installation •.•.•••••
2.3.2 PM-DZllE or PM-DZllF Panel Installation •..••.•••
2.3.3
2.3.4
2.3.5
PM-DZllB or PM-DZ11D Filter Installation ..•.••.•
Logic Board Assembly Installation ••.•••••••..•••
Diagnostic Testing .•••••••••••.••••••••••••.•••.
SECTION 3 - PROGRAMMING
2-1
2-1
2-2
2-2
2-4
2-4
2-6
2-6
3.1 INTRODUCTION. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 3-1
3.2 ADDRESS AND VECTOR SPACE ASSIGNMENTS................... 3-1
3.3 REGISTER BIT ASSIGNMENTS............................... 3-4
3.3.1 Control and Status Register (CSR) - ~.......... 3-4
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MA 701885 REV A

3.4
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
Receive Buffer Register (RBUF) - R2 •••••••.•••••
Line Parameter Register (LPR) - R2 ••••••••••••••
Transmit Control Register (TCR) - R4 ••••••••••••
Modem status Register (MSR) - R6 •.••••••..•••••••
Transmit Data Register (TOR) - R6 ••.••••...•.•..
POOGRAMMING ••••••••••••••••••••••••••••••••••••••••••••
3•4 •1 Baud Rate ...................................... .
3.4.2 Character Length, stop Bits, and Parity .••••.•.•
3.4. 3 Interrupts ..................................... .
3.4.4 Emptying the FIFO ••••••••••••••••••••••.••••••••
3.4.5 Data set Control (EIA Operation Only) ••.••...•••
SECTION 4 - FUNCTIONAL DESCRIPTION
3-6
3-7
3-9
3-9
3-9
3-10
3-10
3-10
3-10
3-11
3-11
4.1 INTRODUcrION. • • • • • • • • • • • • • • • • • • . . • • • • . •• . • . . • • . • • . . • • • • 4-1
4.2 PM-DZll LOGIC MODULE................................... 4-1
4.3 UNIBUS INTERFACE....................................... 4-1
4.3.1 Address Selection............................... 4-1
4.3.2 Register Selection.............................. 4-4
4.3.3 Data Lines...................................... 4-4
4.4 INTERRUPT CONTROL...................................... 4-4
4.4.1 vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.5 DATA CONTROL........................................... 4-6
4.5.1 PM-DZllA, B, and E Registers (EIA
versions Only).................................. 4-6
4.5.2 PM-DZllC, 0, and F Registers (CUrrent
wop Orlly)...................................... 4-7
4.5.3 FIFO............................................ 4-8
4.5.4 Baud Rate Generation............................ 4-8
4.6 DATA CONDITIONING...................................... 4-8
4.6.1 Universal Asynchronous Receiver/Transmitter
(UART) • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 4-8
4.6.2 Data Level Conditioning ••••.•••••••••.••••••••••
4.6.3 Distribution ................................... .
MA 701885
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4-12
4-12
• I '

2-1 :
2-2 :
2-3:
2-4 :
2-5 :
3-1 :
3-2 :
1-1 :
1-2 :
1-3:
1-4 :
1-5 :
1-6 :
1-7:
1-8:
1-9:
2-1:
2-2:
4-1 :
4-2 :
4-3:
4-4 :
4-5 :
Tables
ITEMS SUPPLIED PER EIA CONFIGURATIONS ••••.••••••••••••
ITEMS SUPPLIED PER CURRENT LOOP CONFIGURATIONS ••••••••
ADDRESS SELECTION CHART ••••••.•••••••••••..•••••.•••••
VECTOR SELECTION CHART •.•••••••.••••.••••••.••••••••••
CABLES USED FOR CONNECTION TO LOCAL TERMINALS •••••••••
DEVICE ADDRESS/VECTOR SEQUENCES •••••••••••••••••••••••
BAUD RATE SELECTION CHARI' •••••••••••••••••••••••••••••
Figures
APPLICATIONS FOR THE PM-DZll ••••••••••••••••••••••••.•
BASIC PM-DZl1 •....•••...•..••.• ' •...•••.•.•..••.••..••.
REQUIRED HARIMA.RE ••••••.••••••••••••••••••••••••••••••
CURRENT LOOP MODEL HARIMARE •••••••••••••••••••••••••••
TU.RN'AROUND ••••••••••••••••••••••••••••••••••••••••••••
PM-H325 TEST CONNECTOR (P/N 701587-100A) ••••••••••••••
PM-H3271 TEST CONNECTOR (PIN 701792-100X2) ••••••••••••
PM-3190 TEST CONNECTOR (P/N 703315) ••••••••••.••••••••
GENERAL FUNCTIONAL BLOCK DIAGRAM ••••••••••••••••••••••
PM-DZIIA AND B OR PM-DZIIC AND D INSTALLATION •••••••••
PM-DZI1E OR PM-DZIIF INSTALLATION •••••••••••••••••••••
FUNCTIONAL PM-DZ11 BLOCK DIAGRAM ••••••••••••••••••••••
UNIBUS INTERFACE LOGIC BLOCK DIAGRAM ••••••••••••••••••
INTERRUPT LOGIC BLOCK DIAGRAM ••••• " ••••••••••••••••••••
FORMAT OF TYPICAL INPUT/OUTPUT SERIAL CHARACTER •••••••
UART TRANSMITTER, BLOCK DIAGRAM AND
2-1
2-2
2-7
2-8
2-9
3-2
3-8
1-2
1-3
1-4
1-5
1-6
1-7
1-7
1-8
1-9
2-3
2-5
4-2
4-3
4-5
4-9
SIMPLIFIED TIMING DIAGRAM............................. 4-10
4-6: UARl' RECEIVER, BLOCK DIAGRAM AND
SIMPLIFIED TIMING DIAGRAM............................. 4-11
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MA 701885 REV A

Section 1
General Information
1.1 INTRODUCTION
This manual provides the information needed to install and
operate the PM-DZll multiplexed asynchronous serial line
interface manufactured by Plessey peripheral Systems, Irvine,
california.
The material in this manual is arranged into four sections as
follows:
Section 1 - GENERAL INFORMATION. This section contains a
brief description of the PM-DZll, its configurations, and a
list of specifications.
Section 2 - INSTALLATION AND OPERATION. This section explains
the requirements and procedures for equipment installation.
Interface information and switch settings are provided.
Section 3 - PROGRAMMING. A description of the PM-DZll control
registers and programming features is presented to aid user
programming.
Section 4 - FUNCTIONAL DESCRIPTION. This section provides a
functional description of the PM-DZll and includes signal
functions, block diagrams, and timing diagrams.
MAINTENANCE DRAWING PACKAGE. A separate drawing package,
MD 701885, contains the parts lists, logic diagrams, and
assembly drawings required for a complete understanding of
the PM-DZll.
1.2 GENERAL DESCRIPTION
The PM-DZll is an asynchronous interface that connects a
PDP-ll CPU to 8 or 16 asynchronous serial lines.* It is a
low cost, multiplexed program controlled interface for
connection of multiple local or remote terminals at moderate
throughput. Local operation to terminals or computers is
possible at speeds up to 9600 baud using EIA RS232C interfaces
*PDP-ll is a registered trademark of Digital Equipment
Corporation.
1-1 MA 701885 REV A

or 20mA current loop. Remote operation using the public
switched telephone network is possible with EIA models. Data
set control is provided to permit auto answer (dial-up)
operation with modems capable of full-duplex operation (e.g.,
Bell Models 103 or 113). Remote operation over private lines
for full duplex point-to-point or full duplex multipoint (as
a master control station) is also possible. The PM-DZll does
not support half-duplex operations with secondary transmit
and receive operations. Half-duplex modems, such as the Bell
202, can be used on leased lines with the latter restrictions.
Figure 1-1 shows two possible applications for the PM-DZll.
Further applications are inherent in these figures.
PM-DZll
IISYNCHRONOUS
MULTIPLEXER 201nA
PM-DZll
ASYNCfRONOUS
MULTIPLEXER BIA
FIGURE 1-1:
1. 3 FEATURES
ACTIVE TO
PASSIVE
ADAPTER
PM-DZll
SYSTEM
PM-DZll SYSTEM
APPLICATIONS FOR THE PM-DZll
Some of the features of the asynchronous interface are:
• Low cost 8 and l6-line multiplexed asynchronous interface
for connecting Unibus PDP-lIs to terminals or other
computers.
• EIA and 20mA current loop models available.
• Local operation at speeds up to 9600 baud for maximum
responsiveness of CRT terminals.
MA 701885 REV A
1-2