PLX Technology PEX 8612-AA RDK Quick user guide

PEX 8612-AA RDK
Hardware Reference Manual
Version 1.1
May 2010
Website: www.plxtech.com
Technical Support: www.plxtech.com/support
Copyright © 2010 by PLX Technology, Inc. All Rights Reserved – Version 1.1
May 3, 2008

© 2010 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor
variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: PEX8612AA-RDK-HRM-1.1
May 3, 2008

PEX 8612-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved i
PREFACE
NOTICE
This document contains PLX Confidential and Proprietary information. The contents of this document may not be
copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to entirely
verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured
products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this
information. The information in this document is subject to change without notice. Although every effort has been
made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental, or consequential
damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes
no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which
may arise through the use of the RDK, or for any damage or loss caused by deletion of data as a result of
malfunction or repair.
ABOUT THIS MANUAL
This document describes the PLX PEX 8612-AA RDK, a Rapid Development Kit, from a hardware perspective. It
contains a description of all major functional circuit blocks on the board and also is a reference for the creation of
software for this product. This manual also includes complete schematics and bill of materials.
Note: This Hardware Reference Manual is specific to the PEX 8612 RDK. In the event of a discrepancy
between this Hardware Reference Manual and the PEX 8612 Data Book, please be sure to follow the
instructions and guidelines as stated in the PEX 8612 Data Book when designing your systems.
REVISION HISTORY
Date Version Comments
January 4,
2008 0.50 Hardware Reference Manual initial release.
January 17,
2008 0.60 Added SHP Configuration, updated BOM and Schematics
April
2008 1.0 Updated BOM and Schematics.
May
2010 1.1
Updated BOM and Schematics for the replacement On Semi CAT25080LI-G
EEPROM. Added note to follower Data Book in the case of a discrepancy
with Hardware Reference Manual in “About This Manual” section.

PEX 8612-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved ii
CONTENTS
NOTICE ......................................................................................................................................................... i
ABOUT THIS MANUAL .................................................................................................................................. i
REVISION HISTORY ...................................................................................................................................i
1.General Information.............................................................................................................................1
1.1PEX 8612 Features....................................................................................................................... 2
1.2PEX 8612-AA RDK Features...................................................................................................... 3
2.PEX 8612-AA RDK Hardware Architecture.......................................................................................4
2.1.1PEX 8612 PCI Express Gen 2 Switch .................................................................................. 4
2.2PEX 8612-AA RDK PCI Express Interfaces............................................................................... 4
2.2.1Configuration Modules and Receptacle CM1....................................................................... 5
2.2.2PCI Express Card Edge Connector P1.................................................................................. 6
2.2.3PCI Express Edge Card Connector SLOT 1......................................................................... 6
2.2.4PCI Express Edge Card Connector SLOT 2......................................................................... 6
2.2.5PCI Express Edge Card Connector SLOT 3......................................................................... 6
2.2.64X Mini-SAS Connector IP1................................................................................................ 6
2.3Reference Clock Circuitry............................................................................................................ 7
2.4Reset Circuitry.............................................................................................................................. 7
2.5Hot-Plug Circuits.......................................................................................................................... 8
2.5.1Parallel Hot-Plug Controller Circuit..................................................................................... 8
2.5.2Serial Hot-Plug Controller Circuits ...................................................................................... 9
2.6Serial EEPROM ........................................................................................................................... 9
2.7I2C Interface ............................................................................................................................... 10
2.8Power Distribution ..................................................................................................................... 10
2.9LED Indicators........................................................................................................................... 11
2.9.1Port Link Status Indication (D18 – D20)............................................................................ 12
2.9.2Fatal Error Indication (D24) ............................................................................................... 12
2.9.3PEX_INTA Interrupt Indication (D23)............................................................................... 13
2.9.4PEX 8612 Voltage Level Monitoring (D10 – D11)............................................................ 13
2.10GPIO Pins............................................................................................................................... 13
2.11Reserved Pins ......................................................................................................................... 13
3.On-Board Connectors, Switches, and Jumpers..................................................................................14
3.1DIP Switches.............................................................................................................................. 14
3.1.1Slot ID Selection (SW1) ..................................................................................................... 14
3.1.2Serial Hot-Plug Signal and Control (SW2)......................................................................... 14
3.1.3Parallel Hot-Plug Signal and Control (SW3)...................................................................... 15
3.1.4DC/DC Converter and Mode Controls (SW4).................................................................... 15
3.1.5Upstream Port Select (SW5)............................................................................................... 16
3.1.6Port Configuration and NT Upstream Port Select (SW6)................................................... 16
3.1.7Test Mode Select (SW7)..................................................................................................... 17
3.1.8I2C Address and Other Mode Select (SW8) ....................................................................... 18
3.2Push-Button Switches ................................................................................................................ 19
3.2.1Manual Reset# (S1)............................................................................................................. 19
3.2.2Serial Hot-Plug Controller Attention Button (S2).............................................................. 19
3.2.3Parallel Hot-Plug Controller Attention Button (S3) ........................................................... 19
3.3Midbus probe footprints (JP1 – JP2).......................................................................................... 19
3.42.5V Header (JP3)...................................................................................................................... 20

PEX 8612-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved iii
3.5JTAG Header (JP4).................................................................................................................... 21
3.6I2C Port (JP5 – JP6).................................................................................................................... 21
3.7ATX HD Power Connector (J1)................................................................................................. 21
3.8Reference Clock Header (J2) ..................................................................................................... 21
3.9Probe Mode Input Header (J3)................................................................................................... 22
3.10PLX Use Header (J4).............................................................................................................. 22
4.Bill of Materials/ Schematics.............................................................................................................23
FIGURES
Figure 1-1. PEX 8612-AA RDK Front View ............................................................................................. 1
Figure 2-1. PEX 8612-AA RDK Hardware Architecture........................................................................... 4
Figure 2-2. PCI Express up to 5GT/s Gen 2 Connections.......................................................................... 5
Figure 2-3. Use mini-SAS Connector for NT Function Setup.................................................................... 6
Figure 2-4. PEX 8612-AA RDK Reference Clock Circuit......................................................................... 7
Figure 2-5. PEX 8612-AA RDK Reset Circuit........................................................................................... 7
Figure 2-6. PEX 8612-AA RDK Parallel Hot-Plug Circuits...................................................................... 8
Figure 2-7. PEX 8612-AA RDK Serial Hot-Plug Circuits......................................................................... 9
Figure 2-8. PEX 8612-AA RDK Power Subsystem................................................................................. 10
Figure 3-1. Switch SW1 Default Settings................................................................................................. 14
Figure 3-2. Switch SW2 Default Settings................................................................................................. 14
Figure 3-3. Switch SW3 Default Settings................................................................................................. 15
Figure 3-4. Switch SW4 Default Settings................................................................................................. 15
Figure 3-5. Switch SW5 Default Settings................................................................................................. 16
Figure 3-6. Switch SW6 Default Settings................................................................................................. 16
Figure 3-7. Switch SW7 Default Settings................................................................................................. 17
Figure 3-8. Switch SW8 Default Settings................................................................................................. 18
Figure 3-9. Midbus 2.0 footprint Dimensions, pin numbering and specification
(Copied from Agilent’s document).................................................................................................... 19
TABLES
Table 2-1. PEX 8612-AA RDK LED Indicator descriptions ................................................................... 11
Table 2-2. Port Link Status LED Functions.............................................................................................. 12
Table 2-3. Voltage Level Monitoring LED Functions.............................................................................. 13
Table 2-4. Strap_Reserved Pin Connections ............................................................................................ 13
Table 3-1. Switch SW2 Description ......................................................................................................... 14
Table 3-2. Switch SW3 Description ......................................................................................................... 15
Table 3-3. Switch SW5 Description ......................................................................................................... 16
Table 3-4. Switch SW6 Description ......................................................................................................... 17
Table 3-5. Switch SW7 Description ......................................................................................................... 17
Table 3-6. Switch SW8 Description ......................................................................................................... 18
Table 3-7. Signal Names of x8 PCI Express Midbus probe footprint...................................................... 20
Table 3-8. Midbus probe footprints VS. Lanes of PEX 8612................................................................... 20
Table 3-9. Pin assignment of JP4.............................................................................................................. 21
Table 3-10. Pin assignment of JP5 and JP6.............................................................................................. 21
Table 3-11. Pin assignment of J1.............................................................................................................. 21
Table 3-12. Pin assignment of J2.............................................................................................................. 21

Table 3-13. Pin assignment of J3.............................................................................................................. 22
Table 3-14. Pin assignment of J4.............................................................................................................. 22

PEX 8612-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved 1
1. General Information
The PLX PEX 8612-AA RDK is a Rapid Development Kit based on the PEX 8612, a 12-lane, 3-port PCI Express
Gen 2 switch. The PEX 8612-AA RDK provides a complete hardware and software development platform that
facilitates getting designs up and running quickly, lowering risk and reducing time-to-market. This RDK allows the
upstream port of the PEX 8612 to be directly plugged into a system board’s x8 or x16 PCI Express connector, or
plugged into an x4/x1 PCI Express connector by using card edge adapters.
Figure 1-1. PEX 8612-AA RDK Front View

PEX 8612-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved 2
1.1 PEX 8612 Features
12-lane, 3-port PCI Express Gen 2 switch with integrated on-chip SerDes
120 GT/s aggregate bandwidth (5.0GT/s/Lane x 12 Lanes x 2 (full duplex))
19mm2324-ball Flip-Chip Plastic Ball Grid Array (FCBGA) package
Typical Power – 2.04 W
Cut-Thru packet latency of less than 150ns (x8 to x8)
Low power SerDes (under 90mW per lane)
Fully non-blocking switch architecture
Flexible port configuration
oPorts configurable as x8 or x4, with auto link-width negotiation to x2 and x1
Flexible device configuration
oConfigurable via serial EEPROM, I2C, hardware strapping, or by the host
Maximum packet payload size of 2,048 bytes
Designate any Port as the Upstream Port (Port 0 is recommended)
Dynamic Buffer Pool Architecture
Read Pacing (allows user to throttle Read requests from Downstream Ports to allow for more efficient
performance)
Dual Cast (enhances performance by sending date from one ingress port to two egress ports)
Dynamic speed (2.5 GT/s or 5.0 GT/s) negotiation
Dynamic link-width negotiation (automatically negotiates down to optimal link-width based on traffic
density)
Lane and polarity reversal
Non-Transparent Bridging support
oEnables Dual-Host, Dual-Fabric, Host-Failover applications
Conventional PCI-compatible Link Power Management states – L0, L0s, L1, L2/L3 Ready, and L3 (with
Vaux not supported)
Conventional PCI-compatible Device Power Management states – D0 and D3hot
Active State Power Management
Quality of Service (QoS)
oOne Virtual Channels (VC0) and Eight Traffic classes (TC)
oRound-Robin and Weighted Round-Robin Port arbitration
Reliability, Availability, Serviceability (RAS) features
oPCI Express Standard Hot-Plug Controller for two Ports, include optional usage models for
Manually operated Retention Latch, by way of MRL Sensor and Attention Button support
oElectromechanical Interlock supported with Power Enable output
oBaseline and Advanced Error Reporting capability
oPerformance Monitoring
Per-Port Payload and Header Counters
Per-traffic type (write, Read, Completion) Counters
oJTAG AC/DC boundary scan
o3-port link status indicators (PEX_PORT_GOOD[5,1,0]#)
o17 GPIO and/or Serial Hot-Plug PERST# pins
INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) ball
support
Compliant to the following specifications:
oPCI Local Bus Specification, Revision 3.0 (PCI r3.0)
oPCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2)
oPCI to PCI Bridge Architecture Specification, Revision 1.2 (PCI-to-PCI Bridge r1.2)
oPCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1)
oPCI Express Base Specification, Revision 2.0 (PCI Express Base r2.0)
oPCI Express Card Electromechanical (CEM) Specification, Revision 2.0
oPCI ExpressCard CEM r2.0)
oPCI Express Mini Card Electromechanical (CEM) Specification, Revision 1.1
(PCI ExpressCard Mini CEM r1.1)

PEX 8612-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved 3
oIEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture,
1990 (IEEE Standard 1149.1-1990)
oIEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture
oIEEE Standard 1149.1-1994, Specifications for Vendor-Specific Extensions
oIEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan Architecture
Extensions (IEEE Standard 1149.6-2003)
oThe I2C-Bus Specification, Version 2.1 (I2C Bus v2.1)
1.2 PEX 8612-AA RDK Features
PLX PEX 8612 PCI Express switch in a 324-ball Flip-Chip Plastic BGA package
Form factor based on PCI Express Card Electromechanical (CEM) Specification 2.0
Ships with default configuration of one x4 upstream and two x4 downstream ports
oAll PEX 8612 lane/port configurations supported with configuration modules
Non-Transparent Bridging support
Two x8 Gen 2 Midbus probe footprints for one upstream and two downstream port PCI Express signal
probing
On-board PCI Express RefClk buffer which supports Spread Spectrum Clocking
Parallel Hot-Plug and Serial Hot-Plug Circuits
Socketable Serial EEPROM (2.5V)
Two standard 2x2 headers provides the I2C interface to an I2C master
DIP switches for port configuration, upstream port or NT port select and I2C address settings
Manual push-button PERST# capability
Up to three port link status indicator LEDs for visual inspection of link speed and status
Voltage level monitoring circuit for 1.0V and 2.5V power to the PEX 8612

PEX 8612-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved 4
2. PEX 8612-AA RDK Hardware Architecture
Figure 2-1. PEX 8612-AA RDK Hardware Architecture
2.1.1 PEX 8612 PCI Express Gen 2 Switch
The PEX 8612 is a 12-lane, 3-port PCI Express Gen 2 (5.0 GT/s) switch. It is designed with two stations. Station 0
contains lanes 0 thru 7 and Station 1 contains lanes 24 thru 27. Station 0 can be configured as one x8 port or two
x4 ports. Each port can then auto-negotiate its link-width down to x2 or x1.
2.2 PEX 8612-AA RDK PCI Express Interfaces
The PEX 8612-AA RDK is designed around the PEX 8612, a 3-port, 12-lane Gen 2 switch, and is based on the
form factor specified in the PCI Express CEM 2.0 Specification. The PEX 8612-AA RDK offers four PCI Express
(PCIe) interfaces: a x8 PCI Express edge connector (P1), two x16 PCI Express slots (SLOT 1 and SLOT 2; SLOT
3 is not used), and a 4X Mini-SAS connector (IP1).