PLX Technology PEX 8680 Guide

PEX 8680 Quick Start
Hardware Design Guide
Version 1.1
August 2011
Website:
www.plxtech.com
Technical Support:
www.plxtech.com/support
Copyright © 2011 by PLX Technology, Inc. All Rights Reserved – Version 1.1
August 2011

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
ii © 2011 PLX Technology, Inc. All Rights Reserved.
© 2011 PLX Technology, Inc. All Rights Reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice.
Products may have minor variations to this publication, known as errata. PLX assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX
Technology, Inc.
Other brands and names are the property of their respective owners.
Document Number: PEX 8680AA-SIL-DG-P1-1.1

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved. iii
Preface
Notice
This document contains PLX Confidential and Proprietary information. The contents of this document may
not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX
Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to
entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX
manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or
adequacy of this information. The information in this document is subject to change without notice.
Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for
any errors, incidental or consequential damages in connection with the furnishing, performance, or use of
this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use
of this manual, for loss or claims by third parties, which may arise through the use of the PEX 8680, or for
any damage or loss caused by deletion of data as a result of malfunction or repair.
Revision History
Date Version Comments
August 2009 0.1 Initial release.
March 2010 1.0 Updated Figure 5 and Figure 6
August 2011 1.1 Updated STRAP_RESERVED[3:0] default definitions.

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
iv © 2011 PLX Technology, Inc. All Rights Reserved.
Contents
Preface .........................................................................................................................................................iii
Notice ........................................................................................................................................................iii
Revision History.........................................................................................................................................iii
Introduction................................................................................................................................................... 1
1PCI Express Link Interface..................................................................................................................... 1
1.1 Transmitter....................................................................................................................................... 2
1.2 Receiver........................................................................................................................................... 4
1.3 Reference Clock.............................................................................................................................. 4
1.4 Channel ........................................................................................................................................... 6
2PCB Layout and Stackup Considerations.............................................................................................. 6
2.1 PEX 8680 BGA Routing Escape and De-Coupling Capacitor Placement....................................... 6
2.2 Add-in Board Routing...................................................................................................................... 8
2.3 System Board Routing..................................................................................................................... 8
2.4 Midbus Routing................................................................................................................................ 9
2.5 PCB Stackup Considerations.......................................................................................................... 9
3Non-Transparent Function................................................................................................................... 10
4I2C Interface ......................................................................................................................................... 11
5Hot Plug Circuitry................................................................................................................................. 11
6JTAG Interface..................................................................................................................................... 13
7PCI Express Port Good Indicators....................................................................................................... 14
8Debug Functions.................................................................................................................................. 14
9PEX 8680 Configuration Strapping Balls............................................................................................. 17
10 GPIO Balls............................................................................................................................................ 18
11 Power Supplies, Sequencing, and De-Coupling.................................................................................. 18
11.1 Power Supplies.............................................................................................................................. 19
11.2 Power Sequencing ........................................................................................................................ 19
11.3 Board-Level De-Coupling.............................................................................................................. 19
12 References........................................................................................................................................... 22

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved. v
Figures
Figure 1. Sample PCI Express Link Block Diagram..................................................................................... 1
Figure 2. Single-Ended versus Differential Voltage...................................................................................... 2
Figure 3. Transport Delay Delta................................................................................................................... 5
Figure 4. PEX 8680 RefClk Circuit............................................................................................................... 5
Figure 5. Top Layer BGA Layout and Routing Escape................................................................................ 7
Figure 6. Bottom Layer BGA Layout, Escape, and De-coupling Capacitor Placement ............................... 7
Figure 7. Add-In Card Routing to PCI Express Gold Fingers....................................................................... 8
Figure 8. System Board Routing to PCI Express Slot.................................................................................. 8
Figure 9. PCI Express Midbus Routing Example......................................................................................... 9
Figure 10. Enable NT Function with NT Strapping Balls............................................................................ 10
Figure 11. Disable NT Function.................................................................................................................. 10
Figure 12. I2C Interface Block Diagram...................................................................................................... 11
Figure 13. PHPC Circuit Block Diagram..................................................................................................... 12
Figure 14. SHPC Interface to PEX 8680 Block Diagram ........................................................................... 13
Figure 15. JTAG Interface Block Diagram.................................................................................................. 14
Tables
Table 1. Receiver Equalization Settings....................................................................................................... 4
Table 2. PEX 8680 LED On/Off Patterns, by State.................................................................................... 14
Table 3. Cross-Reference of Ball Names and Related Debug Signal Names........................................... 15
Table 4. Configuration Strapping Balls....................................................................................................... 17

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
vi © 2011 PLX Technology, Inc. All Rights Reserved.
THIS PAGE INTENTIONALLY LEFT BLANK.

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved. 1
Introduction
This quick start hardware design guide is an overview of PLX Technology’s ExpressLane™ PEX 8680
PCI Express Switches and provides examples of how to connect to the various switch interfaces.
1 PCI Express Link Interface
PLX’s PEX 8680 is an 80-Lane, 20-Port PCI Express 2.0 (that is, Gen2)-compliant switch. PCI Express
2.0 supports transfer rates of 5.0 GT/s per Lane. The Physical Media Attachment (PMA) Layer for each
Lane is implemented as a SerDes transceiver, which is composed of a transmit path and receive path.
The transmit path typically contains a serializer, Phase Lock Loop (PLL), and Current Mode Logic (CML)
driver. The receive path consists of a CML Receiver buffer, Clock and Data Recovery circuit (CDR), and a
de-serializer.
As the PCI Express Base Specification, Revision 2.0, continues to mature, so does its description of the
Physical Layer Electrical sub-block. A PCI Express serial Link is described in terms of four components –
Transmitter, Receiver, Channel, and Reference Clock. The Transmitter and Receiver elements are
typically integrated into PCI Express silicon. The channel and Reference Clock are implemented at the
system level. The PCI Express interoperability matrix implies that all four elements must support 5.0 GT/s
for the Link to successfully run at 5.0 GT/s. If any one element is not 5.0 GT/s-compliant, the Link will not
be able to operate beyond 2.5 GT/s. Another important concept is that 2.5 GT/s is not a subset of
5.0 GT/s. This implies that a design targeted to meet 5.0 GT/s might not successfully run in a 2.5 GT/s
environment, if those design criteria are not met, as well.
Figure 1illustrates a block diagram of a sample PCI Express Link.
PLL1
CDR1PLL2
CDR2
RefClk
Rx1
Rx2Tx1
Tx2
Channel
Channel
Device 1 Device 2
Figure 1. Sample PCI Express Link Block Diagram

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
2 © 2011 PLX Technology, Inc. All Rights Reserved.
1.1 Transmitter
A PCI Express Transmitter is typically a differential CML driver that transmits an 8b/10b encoded
bitstream across the channel to the Receiver. The minimum differential voltage swing (VTX-DIFF-PP
Figure 2
) of
Transmitter is 800 mV at both 2.5 GT/s and 5.0 GT/s. The DC common mode voltage can be anywhere
between 0 and 3.6V; hence, AC-coupling capacitors are required to isolate the Transmitter’s
DC component from the Receiver’s fixed 0V DC common mode voltage. The AC-coupling capacitor
values must range between 75 nF and 200 nF, to ensure that the lower frequency components of the
8b/10b encoded data are not affected. illustrates what a generic PCI Express differential signal
looks like, as compared to a single-ended signal.
Note: The swing values listed in Figure 2(400 mV and 800 mV) do not reflect default PLX register
values.
PCI Express Transmitters are required to support de-emphasis. The role of de-emphasis is to reduce the
amount of energy used to transmit multiple successive bits of the same polarity (that is, non-transition
bits), compared to the amount of energy used to transmit a set of transition bits (0 1 or 1 0).
Transition bits have higher frequency components than non-transition bits and are, therefore, more
distorted by the low-pass channel. This effect is also known as Inter-Symbol Interference (ISI), which is a
source of deterministic jitter in the system.
The PCI Express Base Specification, Revision 2.0 defines two de-emphasis levels for devices running at
5.0 GT/s: 3.0 to 4.0 dB and 5.5 to 6.5 dB. The desired de-emphasis level for a given Link is advertised by
the downstream Ports of a switch during Link recovery. The upstream port of a switch and endpoints
connected to the downstream ports capture this value and Set their de-emphasis level, accordingly.
Longer Links should use 6.0 dB, whereas shorter Links can use the 3.5 dB level.
The standard de-emphasis level is selectable by way of the PEX 8680 Link Control 2 register Selectable
De-Emphasis bit (Configuration register, offset 98h[6]).
TXp
TXn
VTX-DC-CM
TXp - TXn
0V
400mV
800mV
Figure 2. Single-Ended versus Differential Voltage

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved. 3
In addition to supporting the standard de-emphasis levels, the PEX 8680 has a number of programmable
registers to control the Transmitter’s characteristics, such as drive level and de-emphasis. The
SerDes Transmitter Control registers exist in Station Ports 0, 4, 8,16, and 20 each controlling a bank of
16 SerDes (Lanes [0-15], [16-31], [32-47], [64-79], and [80-96] respectively). Registers at offsets 0xB8Ch
to 0xB94h are the SerDes Drive Level registers. Registers at offsets 0xB98h to 0xBA0h are the Post-
Cursor Emphasis Level registers. The SerDes Drive Level and Post-Cursor Emphasis Level registers
work in conjunction, to determine the transition and non-transition bits driver swing and de-emphasis ratio.
The PLX driver is implemented as a two-tap driver. When transition bits are transmitted, the SerDes
Drive Level and Post-Cursor Emphasis Level register levels are added together; for non-transition bits,
the two values are subtracted. Using Equation 1, Example 1presents a calculation of what the drive level
and de-emphasis level would be for a given set of register values. For more information on these and
other registers, please refer to the PEX8680 Data Book.
Systems with short Links and/or power-sensitive applications (such as mobile platforms) can optionally
decide to use low-swing output drive levels (400 mVP-P). In the PEX 8680, this can be accomplished by
setting the SerDes Drive Level register for a specific Lane to 01000b (400 mVP-P
Equation 1. PEX 8680 Transmitter Drive Level
), and the Post-Cursor
Emphasis Level register to 00000b (no de-emphasis).
(a) VTRANS = VDRV_LVL + V
(b) V
POST_EMP
NON-TRANS = VDRV_LVL - V
(c) V
POST_EMP
TX-DE-RATIO-3.5DB = 20 log (VPOST_EMP/ VDRV_LVL
Example 1. Setting for Lane 0 Transmitter to 3.5 dB
)
Port 0 SerDes Drive Level register, offset 0xB84h[4:0] = 01111b (750 mVpp)
Port 0 Post-Cursor Emphasis Level register, offset 0xB94h[4:0] = 01101b (162.5 mVpp)
VTRANS
V
= 750 mV + 162.5 mV = 912.5 mVpp
NON-TRANS =
V
750 mV - 162.5 mV = 587.5 mVpp
TX-DE-RATIO-3.5 DB = 20 log (587.5/912.5) = -3.82 dB

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
4 © 2011 PLX Technology, Inc. All Rights Reserved.
1.2 Receiver
The Receiver’s role is to recover the differential bitstream coming across the channel from the Transmitter,
and latch it so it can be de-serialized and forwarded to the logical sub-block. The main components of
a Receiver are the receive buffer and the CDR circuit.
The PCI Express receive buffer input threshold is 175 mV for 2.5 GT/s data rate and 120 mV for a
5.0 GT/s data rate. PCI Express Receivers are required to have a DC common mode voltage of 0V.
The receive buffer will provide bits to the CDR circuit to be sampled and forwarded to the de-serializer.
Digital-based CDRs must track the edges of the incoming bits and determine the best time to sample
each bit, which is typically the center of eye (0.5 UI). The CDR base Reference Clock(s) is provided by
the PLL. A CDR must be able to track either a fixed phase offset (common clock system) or small
continuous phase offset (non-common clock system) between the incoming data/clock and the CDR base
clock. Jitter on the base CDR clock and/or the incoming data stream can cause bit sampling errors to
occur.
Although outside of the scope of the PCI Express specification, Receivers may implement some form of
Receiver equalization to help compensate for the low-pass characteristics of the channel. In general,
Receiver equalization only needs to be used on longer channels.
The PEX 8680 provides a programmable receive equalization function. Ports 0, 4, 8, 16, and 20 each
have a set of Receiver Equalizer registers, located at offsets 0xBA4h and 0xBA8h, to control a group of
16 SerDes. Each individual SerDes has a 4-bit control word. Table 1describes the Receiver equalization
effects.
Table 1. Receiver Equalization Settings
SerDes NReceiver Equalizer[3:0] Equalization
0000b Off
0010b Low
0110b Medium
1110b High
1.3 Reference Clock
The Reference Clock is a key component to a Link that was often overlooked by system designers in first
generation PCI Express systems. The Reference Clock provides a 100-MHz base frequency for the PLL.
The PLL provides a frequency synthesis function, generating the higher speed clocks required to transmit
data at a rate of either 2.5 GT/s or 5.0 GT/s. In designs that implement digital CDRs, the PLL output also
provides the Reference Clocks to the CDR circuit; hence, jitter on the Reference Clock can affect both the
Transmitter and Receiver components.
The PLL has a low-pass, filter-jitter transfer function from its reference input to the high speed output
clocks; therefore, it is important to minimize the low-frequency jitter in the pass band of the PLL.
Low-frequency jitter below the PLL loop bandwidth passes directly to output clocks, which, in turn, drives
the Transmitter and CDR circuits. Jitter at the loop bandwidth is especially critical, given most PLLs have
some amount of gain at the cut-off frequency. High-frequency jitter on the Reference Clock input above
the loop bandwidth is typically attenuated, and is therefore of less concern.
The jitter transfer function of a CDR circuit is modeled as a high-pass filter. Low-frequency jitter, including
Spread-Spectrum Clock (SSC) modulation, is tracked by the CDR circuit, whereas higher-frequency jitter
content causes eye closure at the Receiver. The cut-off frequency of the CDR high-pass function is
usually less than the cut-off frequency of the Transmitter PLL low-pass function. The pass band between
these cut-off frequencies is where Reference Clock jitter causes the most problems.

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved. 5
In PCI Express, the cut-off frequency of the PLL is specified to be between 1.5 to 22 MHz for 2.5 GT/s
and 8 to 16 MHz for 5.0 GT/s data rates. The purpose of these bandwidth ranges is to limit the difference
in PLL bandwidth on the two sides of a Link. This is especially important for common clock systems,
where the amount of jitter appearing at the CDR is defined by the difference function between the Tx and
Rx PLLs.
Another mechanism that can increase jitter seen by a Receiver in common clocked systems is the fixed
phase difference (transport delay delta) between Transmitter data at the CDR input and a Receiver’s
recovered clock, relative to the 100-MHz Reference Clock source. This delay should not exceed 12 ns
per PCI Express specification. The delay budget includes on-chip and off-chip delays. In general terms,
all Reference Clock nets in a system should be matched within 38.1 cm (15 in.). Figure 3illustrates the
Reference Clock transport delay delta.
The PEX 8680 PEX_REFCLKn/p signal is the Reference Clock Input buffer. It has an internal DC-biasing
circuit, and hence, should be AC-coupled from the RefClk source driver. Use 0.01 to 0.1 µF capacitors
(0603 or 0402-size) to AC-couple the Reference Clock input, as illustrated in Figure 4.
PLL1
CDR1PLL2
CDR2
RefClk
Rx1
Rx2Tx1
Tx2
Channel
Channel
Device 1 Device 2
T1
T2
T3
T4
T5
Transport Delay Delta = (T1+T2+T3) – (T4+T5) < 12 ns
Figure 3. Transport Delay Delta
33 ohm
33 ohm
49.9 ohm 0.1 µF
PEX 8680
PCI Express
RefClk Driver
PEX_REFCLKp
PEX_REFCLKn
Source termination placed close to driver.
49.9 ohm
0.1 µF
Place AC-coupling capacitors
near PEX_REFCLKn/p balls
Figure 4. PEX 8680 RefClk Circuit

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
6 © 2011 PLX Technology, Inc. All Rights Reserved.
1.4 Channel
In PCI Express, the channel refers to the board level copper interconnects (including connectors) that lie
between the Transmitter and Receiver balls. The channel is represented as a transmission line, which
can be modeled by a distributed series of Resistance Inductance Conductance Capacitance (RLGC)
circuits. A transmission line behaves like a low-pass filter due to frequency-dependent dielectric and
conductor losses.
In PCI Express, the channel contributes to amplitude loss and deterministic jitter, which is why it is
important to minimize discontinuities, such as vias and stubs, to minimize channel effects.
A common issue that presents itself to PCI Express system designers is determining allowable channel
length. This is a question that does not have a simple answer. The best way to determine if a particular
channel length is allowable is to simulate the channel using the HSPICE models for the PEX8680
provided by PLX and available on the product website at www.plxtech.com/8680. The PCI Express Base
Specification, Revision 2.0 provides additional details for simulating a channel.
2 PCB Layout and Stackup Considerations
PCB layout is of critical importance for PCI Express systems. Numerous form factor specifications (PCI
Express Base Specification, Revision 2.0 and PCI Express Card Electromechanical (CEM) Specification,
Revisions 1.0a and 1.1) exist for providing important implementation guidelines for a given form factor. It
is important to understand the type of system being designed before starting layout. For example, the PCI
Express Card Electromechanical (CEM) Specification defines two platforms, referred to as system boards
and add-in cards (boards). Each platform has its own criteria, in terms of jitter and loss budget, trace
lengths and length matching, and so forth.
2.1 PEX 8680 BGA Routing Escape and De-Coupling Capacitor Placement
The PEX 8680 is in a 35x35 mm2
Each pair is split between two rows on the package; hence, the pairs start off with a 1-mm (39.4-mil)
offset And small serpentines may be necessary to match the lengths within the pair. When implemented,
make the serpentines as close to the BGA as possible to allow the differential signal to be tightly coupled
as it travels down the channel.
FCBGA package with 1-mm ball pitch. Power and ground pads have
small “dog-bone” nets from the pad to a via which will connect it with an internal power or ground plane.
The PEX 8680 places all Transmitter differential pairs on the outer two rows of balls and Receiver
differential pairs on rows four and five. This means only two signal layers are required in a PCB stackup
to escape the differential pairs from the BGA. All Transmitters can escape on the top layer, whereas the
Receiver pairs can escape on either the bottom layer or some other internal signal layer. The positive and
negative conductors of a pair should be coupled together as quickly as possible, after escaping from the
BGA.
Figure 5and Figure 6demonstrate one means of escaping the differential pairs from a typical PLX PCIe
switch using two routing layers.
The PEX 8680 is a full matrix, 1-mm pitch BGA. Hence, placing de-coupling capacitors underneath the
BGA can be tricky. It is best to use 0201-sized ceramic capacitors under the BGA matrix (bottom layer),
so that the capacitors can be placed as close to the power balls as possible. Figure 6illustrates the
typical placement of 0201 de-coupling capacitors underneath the PLX PCIe switch.

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved. 7
Figure 5. Top Layer BGA Layout and Routing Escape
Figure 6. Bottom Layer BGA Layout, Escape, and De-coupling Capacitor Placement

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
8 © 2011 PLX Technology, Inc. All Rights Reserved.
2.2 Add-in Board Routing
Although the PEX 8680 Transmitter pairs escape on the top layer (as previously mentioned), at some
point they must route to the bottom layer to connect to the gold fingers as is the case for an add-in board.
If a logic analyzer midbus footprint is placed in the routing path, the layer transition can occur at that point.
This works out well, because the midbus footprint will have a significant number of ground vias, which
provide effective ground plane stitching for the differential signal’s return path. If a midbus footprint is not
used, layer changing can occur at the AC-coupling capacitors. Dedicated ground vias can be placed near
the capacitors, close to the signal vias, to provide a return path. One ground via per pair is ideal; however,
one via per every two pair is acceptable.
Receiver differential pairs must also transition signal layers at least once. Receiver pairs start off at the
top layer, from the gold fingers, and into the inner rows of the BGA. The layer transition should occur at
the midbus footprint, if one exists, or close to the gold fingers. Either location should have plenty of
ground vias.
PCI Express add-in boards must be length-matched within 5-mil. AC-coupling capacitors should be
placed close to the gold fingers. Differential pairs for PCI Express Gen2 add-in boards should have a
differential impedance of between 68 to 105 ohms (85 ohms, nominal).
Figure 7. Add-In Card Routing to PCI Express Gold Fingers
2.3 System Board Routing
System board routing is simplified slightly. Transmitter pairs can escape on the top layer from the BGA
and route to AC-coupling capacitors, placed close to the slot. Similarly, Receiver pairs can escape on the
bottom layer and directly route to the slot. Transmitter pairs can also transition to the bottom layer after
the AC-coupling capacitors, to minimize the stub effects of a through-hole PCI Express slot.
PCI Express system boards must be length-matched within 10-mil and all AC-coupling capacitors should
be placed close to the slot. Differential pairs for PCI Express Gen2 system boards should have a
differential impedance between 68 to 105 ohms (85 ohms, nominal).
Figure 8. System Board Routing to PCI Express Slot

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved. 9
2.4 Midbus Routing
Midbus footprints can be placed into the routing path, to provide an interface to various protocol analyzers,
as well as provide a location to probe a signal using oscilloscopes. Transmitter pairs route on one side of
the footprint, while Receiver signals route through the other side.
Figure 9. PCI Express Midbus Routing Example
2.5 PCB Stackup Considerations
Determining the PCB stackup is one of the most important steps in designing and implementing a system.
The PCB stackup should be determined prior to board routing, because it will determine the trace width
and spacing requirements necessary to achieve a particular characteristic impedance and differential
impedance. After the stackup is known, the trace width can be selected. For a single-ended signal, this is
enough to determine the characteristic impedance of that trace. For differential signals, the last step is to
determine the separation between the positive and negative conductors, to achieve the needed
differential impedance.
Additionally, a PCB stackup can determine the power supply de-coupling scheme for a device. Parallel
plane capacitance exists between a PCB’s DC power and ground planes. PCB reference planes have an
insignificant amount of series inductance; therefore, their effective frequency range is much higher than
that of discrete capacitors.
PCB traces can be implemented as one of two types of transmission lines – microstrip and stripline.
Microstrip traces have only one reference plane, and therefore, represent traces on the outer layers (top
and bottom layer) of a PCB. Stripline traces have two reference planes and are implemented using inner
routing layers. Typically, stripline traces are only available for PCBs with six or more layers. Microstrip
and stripline traces each have their own properties, which must be weighed when determining which type
of trace to use.

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
10 © 2011 PLX Technology, Inc. All Rights Reserved.
3 Non-Transparent Function
The PEX 8680 supports Non-Transparent (NT) function. There are three ways to enable the NT function
and configure the NT Port for the PEX 8680.
Method 1. Use of the Strapping balls:
STRAP_NT_ENABLE#
STRAP_NT_UPSTREAM_PORTSEL[4:0]
Pull down the STRAP_NT_ENABLE# to logic zero (0) to enable the NT function. Pull up or down the
STRAP_NT_UPSTREAM_PORTSEL[4:0] to select the NT Port.
Method 2. Enable the NT function and configure the NT Port through the serial EEPROM. The NT
configuration settings will be loaded upon power-up and after reset.
Method 3. Use the PEX 8680 I2
C Port 0 to enable the NT function and configure the NT Port.
Figure 10 illustrates how to implement the NT functions through the Strapping balls. Figure 11 illustrates
how to disable the NT functions, through the PEX 8680’s NT Strapping balls.
2.5V
PEX 8680
STRAP_NT_UPSTREAM_PORTSEL0
STRAP_NT_UPSTREAM_PORTSEL1
STRAP_NT_ENABLE#
2.5V
Figure 10. Enable NT Function with NT Strapping Balls
2.5V
PEX 8680
STRAP_NT_UPSTREAM_PORTSEL0
STRAP_NT_UPSTREAM_PORTSEL1
STRAP_NT_ENABLE#
Figure 11. Disable NT Function

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved. 11
4 I2
The PEX 8680 implements dual two-wire I
C Interface 2C interface ports. I2C-Port 0 is a slave interface port and I2C-
Port 1 is a master interface port used with the SHPC (see Section 5). Through its I2C_SCL0 and
I2C_SDA0 balls (I2C-Port 0), the PEX 8680 allows an external I2C Master to read and write device
registers through an out-of-band mechanism. The simplest way to implement an I2
Figure 12 C interface to the PEX 8680 is illustrated in .
VCC
PEX 8680
I2C_SDA0
I2C_SCL0
VCC
1
2
R
R
R = 1K to 10K
Figure 12. I2
C Interface Block Diagram
5 Hot Plug Circuitry
The PEX 8680 supports four Parallel Hot Plug Controllers (PHPC) and up to nineteen Serial Hot Plug
Controllers (SHPC), to service its downstream Ports. The PHPCs are designated as Hot Plug Ports A, B,
C, and D. Each PHPC has 10 Hot Plug signal balls to control various Hot Plug-related functions:
HP_ATNLED_[n]#
HP_BUTTON_[n]#
HP_CLKEN_[n]#
HP_MRL_[n]#
HP_PERST_[n]#
HP_PRSNT_[n]#
HP_PWER_GOOD_[n]
HP_PWREN_[n]
HP_PWRFLT_[n]#
HP_PWRLED_[n]#
where “n” is A, B, C and/or D
Figure 13 provides an example of how to connect the PEX 8680’s PHPC to the external circuit, to build
a complete PHPC circuit.

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
12 © 2011 PLX Technology, Inc. All Rights Reserved.
Clkenx#
Atnledx#
Pwrledx#
Pwrenx
Perstx#
VCC
System
Power
Supply
12V, 3.3V
VCC
VCC
Buttonx#
Pwrflx#
Mrlx#
Prsntx#
VCC
VCC
Hot Plug
Controller
Pwrgdx#
Clken_a#
Atnled_a#
Pwrled_a#
Pwren_a
Perst_a#
Button_a#
Pwrflt_a#
Mrl_a#
Prsnt_a#
Pwrgood_a
PEX 8680
FETs
Clock
Buffer
Figure 13. PHPC Circuit Block Diagram
When connecting the I2C-Port 1 to multiple I/O expander ICs, the PEX 8680 has the option of having Hot
Plug capability on eight of its downstream Ports. The PEX 8680’s I2C-Port 1 is the I2C Master, which is
designed to interface to I/O expander ICs, to build SHPCs. One 16-I/O expander connects to I2C-Port 1
for a single SHPC, and one 40 I/O expander connects to the I2C-Port 1 for two SHPCs. Both 16-I/O
expander(s) and 40-I/O expander(s) cannot concurrently connect to the I2C Bus. To use 40-I/O
expander(s), a register bit within the PEX 8680 must be Set, and boot with serial EEPROM is essential.
After the PEX 8680 is powered up, the state machine inside the PEX 8680 scans the number of I/O
expander ICs connecting to the I2
Figure 14
C Bus, starting from Address 000h, in ascending order. If it cannot
locate the device with Address 000h, it stops the scan process. After it locates the I/O expander IC, it
automatically assigns a valid Port Number for this SHPC. illustrates a block diagram of the
SHPC interface to the PEX 8680. The SHPC has more signals than the PHPC. Besides the 10 Hot Plug
signals mentioned at PHPC, INTERLOCK, SLOTID[3:0], and one GPIO are added to the SHPC. Also, the
interrupt signal output, INT#, from the I/O expander, should be connected to the PEX 8680’s Interrupt
Input ball, SHPC_INT#, for the PEX 8680 to service input events at the SHPC. Because the I/O
Expander requires some time to be configured upon power-up, it is recommended that GPIO[24-42]
signals from the PEX 8680 be used for slot PERST# from the I/O Expander to provide reset to
downstream slots.

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved. 13
PEX 8680
SDA
SCL
INT#
16/40 I/O Expander
MAX7311 or
PCA9698
Interlock
Sltid[4:0]
GPIO
AD[2:0]
I
2
C
Port 1
PCI
Express
Slot
VCC
System
Power
Supply
12V, 3.3V
VCC
VCC
VCC
VCC
Hot Plug
Controller
FETs
Clock
Buffer
Clken#
Atnled#
Pwrled#
Pwren
Perst#
Button#
Pwrflt#
Mrl#
Prsnt#
Pwrgood
VCC
VCC
4
3
IO 13/29
IO 11/17
IO 0/16
IO 2/18
IO 3/19
IO 14/30
IO 5/21
IO 6
IO[10:7]/[26:22]
IO 11/27
IO 12/28
IO 15/31
VCC
VCC
GPIO
VCC
Figure 14. SHPC Interface to PEX 8680 Block Diagram
6 JTAG Interface
The PEX 8680 supports a five-ball JTAG Boundary Scan interface. The JTAG interface consists of the
following signals:
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST#
At the board level, pull JTAG_TDI, JTAG_TMS, and JTAG_TCK up to 2.5V with 1-kohm to 5-kohm
resistors. Pull JTAG_TRST# down to VSS with a 1-kohm to 5-kohm resistor. Because the PEX 8680
JTAG clock frequency can be as high as 10 MHz, a 15-ohm series terminator can be added to TCK, TDI,
and TDO, to improve signal quality. Figure 15 illustrates a generic JTAG interconnection.

PEX 8680 Quick Start Hardware Design Guide, Version 1.1
14 © 2011 PLX Technology, Inc. All Rights Reserved.
PEX 8680
TDO
TDI
TCK
TMS
TRST#
VCC
from JTAG Controller
from JTAG Controller
from JTAG Controller
to next JTAG device
from previous JTAG device
R R R
R = 1K
Figure 15. JTAG Interface Block Diagram
7 PCI Express Port Good Indicators
The PEX 8680 provides up to 20 Active-Low “Port Good” Output balls for the PCI Express Port on the
device, PEX_PORT_GOOD[23:16,11:0]#. These Output balls can be used to build the Port Status LED
circuits, to indicate the status of each PEX 8680 Port. Each Port has five states, which are related to Link
Status, Channel Speed, and the Port’s Lane width. Table 2lists the relationship of the LED On/Off
patterns to the Port status.
Table 2. PEX 8680 LED On/Off Patterns, by State
State LED Pattern
Link is down Off
Link is up, 5 Gbps, all Lanes are up On
Link is up, 5 Gbps, reduced Lanes are up Blinking, 0.5 seconds On, 0.5 seconds Off
Link is up, 2.5 Gbps, all Lanes are up Blinking, 1.5 seconds On, 0.5 seconds Off
Link is up, 2.5 Gbps, reduced Lanes are up Blinking, 0.5 seconds On, 1.5 seconds Off
8 Debug Functions
(The optional Debug function is primarily intended for prototyping activities. Its use requires assistance
from PLX Technical Support.)
Two major debug functions of the PEX 8680 are External Probe mode (EPM) and SerDes Debug mode
(SDM). The EPM function is for viewing the internal state machines and control signals of the
three station-based modules and the core-based module. The SDM function is for viewing
the 20-bit Receive Bus (elastic buffer exit) and 20-bit Transmit Bus of each Lane of the SerDes,
in the PEX 8680. Two Strapping balls are used to enable either Debug mode function. Pulling down
the STRAP_PROBE_MODE# ball enables the EPM function. Pulling down the
STRAP_SERDES_MODE_EN# ball enables the SDM function. The EPM contains 16 inputs and
39 outputs. The SDM contains 11 inputs and 44 outputs. When either Debug mode is enabled, the
parallel Hot Plug, Port Good, General-Purpose I/O, and Spare balls, as well as two other Strapping balls
are serviced by EPM and SDM inputs or outputs.
Notes: Inputs are marked in blue, outputs are marked in red.
The maximum frequency of Debug mode Output signals, such as PROCMON (N/C, at location W4), is
125 MHz, with fast rise and fall time. When routing these traces to the mictor connector for scope probing,
50-ohm, single-ended controlled-impedance traces are recommended. To service normal operation and