PLX Technology PEX 8647-AA User manual

PEX 8647-AA Quick Start
Hardware Design Guide
Version 1.2
January, 2008
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PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2
iv © 2008 PLX Technology, Inc. All Rights Reserved
© 2007 – 2008 PLX Technology, Inc. All Rights Reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice.
Products may have minor variations to this publication, known as errata. PLX assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of
PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Document Number: PEX 8647-AA-SIL-DG-P1-1.2

PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2
© 2008 PLX Technology, Inc. All Rights Reserved v
Contents
Preface .........................................................................................................................................................vi
Notice ........................................................................................................................................................vi
Revision History ........................................................................................................................................ vi
Introduction ................................................................................................................................................... 1
1Switch Interfaces.................................................................................................................................... 1
1.1 PCI Express Link Interface .............................................................................................................. 2
1.1.1 Transmitter ................................................................................................................................ 3
1.1.2 Receiver .................................................................................................................................... 5
1.1.3 Reference Clock........................................................................................................................ 6
1.1.4 Channel..................................................................................................................................... 7
1.2 JTAG Interface ................................................................................................................................ 8
1.3 I2C Interface ..................................................................................................................................... 9
1.4 PCI Express Port Good Indicators................................................................................................... 9
1.5 Strapping Balls............................................................................................................................... 10
1.6 GPIO Balls..................................................................................................................................... 11
1.7 Power Supplies, Sequencing, and De-Coupling ........................................................................... 11
1.7.1 Power Supplies ....................................................................................................................... 11
1.7.2 Power Sequencing .................................................................................................................. 12
1.7.3 Board-Level De-Coupling........................................................................................................ 13
2PCB Layout and Layer Stackup Considerations.................................................................................. 15
2.1 BGA Routing Escape and De-coupling Capacitor Placement....................................................... 15
2.2 Add-In Board Routing .................................................................................................................... 17
2.3 System Board Routing................................................................................................................... 17
2.4 Midbus Routing.............................................................................................................................. 18
2.5 PCB Layer Stackup Considerations .............................................................................................. 18
3References........................................................................................................................................... 19
Figures
Figure 1. Sample PCI Express Link Block Diagram ..................................................................................... 2
Figure 2. Single-Ended versus Differential Voltage...................................................................................... 3
Figure 3. Transport Delay Delta ................................................................................................................... 7
Figure 4. PEX 8647 RefClk Circuitry ............................................................................................................ 7
Figure 5. JTAG Interface Block Diagram...................................................................................................... 8
Figure 6. I2C Interface Block Diagram .......................................................................................................... 9
Figure 7. Power Balls and Capacitor Placement........................................................................................ 11
Figure 8. Power Plane Impedance versus Frequency ............................................................................... 13
Figure 9. Capacitor Footprint Effects on Series Inductance....................................................................... 14
Figure 10. Top Layer BGA Layout and Routing Escape ............................................................................ 16
Figure 11. Bottom Layer BGA Layout, Escape, and De-coupling Capacitor Placement ........................... 16
Figure 12. Add-In Board Routing to PCI Express Gold Fingers................................................................. 17
Figure 13. System Board Routing to PCI Express Slot .............................................................................. 17
Figure 14. PCI Express Midbus Routing Example ..................................................................................... 18
Tables
Table 1. Receiver Equalization Settings....................................................................................................... 5
Table 2. PEX 8647 LED On/Off Patterns, by State...................................................................................... 9
Table 3. Configuration Strapping Balls....................................................................................................... 10
Table 4. STRAP_RESERVED Ball External Pull-Up/Pull-Down Resistor Requirements .......................... 10

PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2
vi © 2008 PLX Technology, Inc. All Rights Reserved
Preface
Notice
This document contains PLX Confidential and Proprietary information. The contents of this document may
not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX
Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to
entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX
manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or
adequacy of this information. The information in this document is subject to change without notice.
Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for
any errors, incidental or consequential damages in connection with the furnishing, performance, or use of
this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use
of this manual, for loss or claims by third parties, which may arise through the use of the PEX 8647, or for
any damage or loss caused by deletion of data as a result of malfunction or repair.
Revision History
Date Version Comments
September 26, 2007 1.0 Initial release.
October 16, 2007 1.1
Reorganized document structure.
Updated signal names listed in Table 3, and added new
STRAP_RESERVED table (Table 4).
Applied miscellaneous corrections and enhancements.
January 9, 2008 1.2 Added STRAP_RESERVED18# and
STRAP_RESERVED19# to Table 4.

PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2
© 2008 PLX Technology, Inc. All Rights Reserved 1
Introduction
This quick start hardware design guide is an overview of PLX Technology’s ExpressLane™ PEX 8647
PCI Express Switch and provides examples of how to connect to the various switch interfaces.
1Switch Interfaces
The PEX 8647 device is a 48-Lane, 3-Port Gen 2 switch, designed for graphics systems. Its signal
interface is grouped into the following functional blocks:
PCI Express Link interface
JTAG interface
I2C interface
PCI Express Port Good indicators
Strapping balls
GPIO balls
Power supply

1.1 PCI Express Link Interface
PLX’s PEX 8647 is a 48-Lane, 3-Port PCI Express 2.0 (that is, Gen 2)-compliant switch. PCI Express 2.0
supports transfer rates of 5.0 GT/s per Lane. The Physical Media Attachment (PMA) Layer for each Lane
is implemented as a SerDes transceiver, which is composed of a transmit path and receive path. The
transmit path typically contains a serializer, Phase Lock Loop (PLL), and Current Mode Logic (CML)
driver. The receive path consists of a CML Receiver buffer, Clock and Data Recovery circuit (CDR), and a
de-serializer.
As the PCI Express Base Specification, Revision 2.0, continues to mature, so does its description of the
Physical Layer Electrical sub-block. A PCI Express serial Link is described in terms of four components –
Transmitter, Receiver, Reference Clock, and Channel. The Transmitter and Receiver elements are
typically integrated into PCI Express silicon. The Channel and Reference Clock are implemented at the
system level. The PCI Express interoperability matrix implies that all four elements must support 5.0 GT/s
for the Link to successfully run at 5.0 GT/s. If any one element is not 5.0 GT/s-compliant, the Link will not
be able to operate beyond 2.5 GT/s. Another important concept is that 2.5 GT/s is not a subset of
5.0 GT/s. This implies that a design targeted to meet 5.0 GT/s might not successfully run in a 2.5 GT/s
environment, if those design criteria are not met, as well.
Figure 1 illustrates a block diagram of a sample PCI Express Link.
PLL1
CDR1
PLL2
CDR2
RefClk
Rx1
Rx2Tx1
Tx2
Channel
Channel
Device 1 Device 2
Figure 1. Sample PCI Express Link Block Diagram
PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2
2 © 2008 PLX Technology, Inc. All Rights Reserved

1.1.1 Transmitter
A PCI Express Transmitter is typically a differential CML driver that transmits an 8b/10b encoded
bitstream across the Channel to the Receiver. The minimum differential voltage swing (VTX-DIFF-PP) of the
Transmitter is 800 mV at both 2.5 GT/s and 5.0 GT/s. The DC common mode voltage can be anywhere
between 0 and 3.6V; hence, AC-coupling capacitors are required to isolate the Transmitter’s
DC component from the Receiver’s fixed 0V DC common mode voltage. The AC-coupling capacitor
values must range between 75 and 200 nF, to ensure that the lower frequency components of the 8b/10b
encoded data are not affected. Figure 2 illustrates what a generic PCI Express differential signal looks
like, as compared to a single-ended signal.
Note: The swing values listed in Figure 2 (400 mV and 800 mV) do not reflect default PLX register values.
PCI Express Transmitters are required to support de-emphasis. The role of de-emphasis is to increase
the resultant signal energy of the highest data frequencies and to counteract the frequency-dependent
Channel losses. De-emphasis does this by reducing the amount of energy used to transmit multiple
successive bits of the same polarity (that is, non-transition bits), compared to the amount of energy used
to transmit a set of transition bits (0 -> 1 or 1 -> 0). Transition bits have higher frequency components
than non-transition bits and are, therefore, more distorted by the low-pass Channel. This effect is one
aspect of Inter-Symbol Interference (ISI), which is a source of deterministic jitter in the system.
The PCI Express Base Specification, Revision 2.0, defines two de-emphasis levels for devices running at
5.0 GT/s, 3.0 to 4.0 dB and 5.5 to 6.5 dB. The desired de-emphasis level for a given Link is advertised by
the downstream Ports of a switch during Link recovery. Endpoints and the upstream device capture this
value and set their de-emphasis levels, accordingly. Longer Links should use 6.0 dB, whereas shorter
Links can use 3.5 dB.
The standard de-emphasis level is selectable by way of the PEX 8647 Link Control 2 register Selectable
De-Emphasis bit (Configuration register, offset 98h[6]).
TXp
PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2
© 2008 PLX Technology, Inc. All Rights Reserved 3
TXn
VTX-DC-CM
TXp - TXn
400mV
800mV
0V
Figure 2. Single-Ended versus Differential Voltage

PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2
4 © 2008 PLX Technology, Inc. All Rights Reserved
In addition to supporting the standard de-emphasis levels, the PEX 8647 has a number of programmable
registers to control the Transmitter’s characteristics, such as drive level and de-emphasis. The SerDes
Transmitter Control registers each control a bank of 16 SerDes (Port 0 – Lanes [0-15]; Port 4 –
Lanes [16-31]; Port 8 – Lanes [32-47]). Registers at offsets B84h to B90h are the SerDes Drive Level
registers. Registers at offsets B94h to BA0h are the Post-Cursor Emphasis Level registers. The SerDes
Drive Level and Post-Cursor Emphasis Level registers work in conjunction, to determine the transition
and non-transition bits driver swing and de-emphasis ratio. The PLX driver is implemented as a two-tap
driver. When transition bits are transmitted, the SerDes Drive Level and Post-Cursor Emphasis Level
register levels are added together; for non-transition bits, the two values are subtracted. Using Equation 1,
Example 1 presents a calculation of what the drive level and de-emphasis level would be for a given set
of register values.
Systems with short Links and/or power-sensitive applications (such as mobile platforms) can optionally
decide to use low-swing output drive levels (40 0 mVP-P). In the PEX 8647, this can be accomplished by
setting the SerDes Drive Level register for a specific Lane to 01000b (400 mVP-P), and the Post-Cursor
Emphasis Level register to 00000b (no de-emphasis).
Equation 1. PEX 8647 Transmitter Drive Level
(a) VTRANS = VDRV_LVL + VPOST_EMP
(b) VNON-TRANS = VDRV_LVL - VPOST_EMP
(c) VTX-DE-RATIO-3.5DB = 20 log (VPOST_EMP/ VDRV_LVL)
Example 1. Setting for Lane 0 Transmitter to 3.5 dB
Port 0 SerDes Drive Level register, offset B84h[4:0] = 01111b (750 mVpp)
Port 0 Post-Cursor Emphasis Level register, offset B94h[4:0] = 01101b (162.5 mVpp)
VTRANS = 750 mV + 162.5 mV = 912.5 mVpp
VNON-TRANS = 750 mV - 162.5 mV = 587.5 mVpp
VTX-DE-RATIO-3.5 DB = 20 log (587.5/912.5) = -3.82 dB

PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2
© 2008 PLX Technology, Inc. All Rights Reserved 5
1.1.2 Receiver
The Receiver’s role is to recover the differential bitstream coming across the Channel from the
Transmitter, and latch it so it can be de-serialized and forwarded to the logical sub-block. The main
components of a Receiver are the Receive buffer and CDR circuit.
The PCI Express Receive buffer input threshold is 175 mV for a 2.5 GT/s data rate and 120 mV for
a 5.0 GT/s data rate. PCI Express Receivers are required to have a DC common mode voltage of 0V.
The Receive buffer provides bits to the CDR circuit, which samples each bit and forwards them to the
de-serializer. Digital-based CDRs must track the edges of the incoming bits and determine the best time
to sample each bit, which is typically the center of the eye (0.5 UI). The CDR’s base Reference Clock(s) is
provided by the PLL. A CDR must be able to track either a fixed phase offset (common clock system) or
small continuous phase offset (non-common clock system), between the incoming data/clock and the
CDR’s base clock. Jitter on the base CDR clock and/or the incoming data stream can cause bit sampling
errors to occur.
Although not explicitly mentioned in the PCI Express Base Specification, Revision 2.0, Receivers may
implement some form of Receiver equalization, to help compensate for the Channel's low-pass
characteristics. In general, Receiver equalization only needs to be used on longer Channels.
The PEX 8647 provides a programmable Receiver Equalization function. Ports 0, 4, and 8 each have a
set of Receiver Equalizer registers, located at offsets BA4h and BA8h, to control a group of 16 SerDes.
Each individual SerDes has a 4-bit control word. Table 1 describes the Receiver equalization effects.
Table 1. Receiver Equalization Settings
SerDes NReceiver Equalizer[3:0] Equalization
0000b Off
0010b Low
0110b Medium
1110b High

PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2
6 © 2008 PLX Technology, Inc. All Rights Reserved
1.1.3 Reference Clock
The Reference Clock is a key component to a Link that was often overlooked by system designers in first
generation PCI Express systems. The Reference Clock provides a 100-MHz base frequency for the PLL.
The PLL provides a frequency synthesis function, generating the higher-speed clocks required to transmit
data at a rate of either 2.5 GT/s or 5.0 GT/s. In designs that implement digital CDRs, the PLL output also
provides the Reference Clocks to the CDR circuit; hence, jitter on the Reference Clock can affect both the
Transmitter and Receiver components.
Note: In Gen 2 PCI Express, the allowable reference jitter is much tighter than in Gen1 systems
(3.1 ps rms); therefore, it is important to select the high-quality PCI Express clock sources.
The PLL has a low-pass, filter-jitter transfer function from its reference input to the high-speed output
clocks; therefore, it is important to minimize the low-frequency jitter in the pass band of the PLL.
Low-frequency jitter, below the PLL loop bandwidth, passes directly to output clocks, which in turn, drives
the Transmitter and CDR circuits. Jitter, at the loop bandwidth, is especially critical, given most PLLs have
some amount of gain at the cut-off frequency. High-frequency jitter, on the Reference Clock input above
the loop bandwidth, is typically attenuated, and therefore, is of less concern.
The jitter transfer function of a CDR circuit is modeled as a high-pass filter. Low-frequency jitter, including
Spread-Spectrum Clock (SSC) modulation, is tracked by the CDR circuit, whereas higher-frequency jitter
content causes eye closure at the Receiver. The cut-off frequency of the CDR high-pass function is
usually less than the cut-off frequency of the Transmitter PLL low-pass function. The pass band between
these cut-off frequencies is where Reference Clock jitter causes the most problems.
In PCI Express, the cut-off frequency of the PLL is specified to be between 1.5 to 22 MHz for 2.5 GT/s
data rates and 8 to 16 MHz for 5.0 GT/s data rates. The purpose of these bandwidth ranges is to limit the
difference in PLL bandwidth on the two sides of a Link, while still providing flexibility, in terms of PLL
design. This is especially important for common clock systems, where the amount of jitter appearing at
the CDR is defined by the difference function between the Tx and Rx PLLs.
Another mechanism that can increase the jitter seen by a Receiver in common-clocked systems is the
fixed-phase difference (transport delay delta) between Transmitter data at the CDR input and a
Receiver’s recovered clock, relative to the 100-MHz Reference Clock source. This delay should not
exceed 12 ns per the PCI Express Base Specification, Revision 2.0. The delay budget includes on-chip
and off-chip delays. In general terms, all Reference Clock nets in a system should be matched within 38.1
cm (15 in.). Figure 3 illustrates the Reference Clock transport delay delta.
The PEX 8647 PEX_REFCLKn/p signal pair is the Reference Clock Input buffer. It has an internal
DC-biasing circuit, and therefore, should be AC-coupled from the RefClk source driver. Use 0.01 to 0.1 µF
capacitors (0603- or 0402-size) to AC-couple the Reference Clock input, as illustrated in Figure 4.