PLX Technology PEX 8612-AA Guide
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
iv © 2007 PLX Technology, Inc. All Rights Reserved.
© 2007 PLX Technology, Inc. All Rights Reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice.
Products may have minor variations to this publication, known as errata. PLX assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX
Technology, Inc.
Other brands and names are the property of their respective owners.
Document Number: PEX 8612-AA-SIL-DG-P1-1.2
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. v
Contents
Preface ........................................................................................................................................................ vii
Notice ....................................................................................................................................................... vii
Revision History ....................................................................................................................................... vii
Introduction ................................................................................................................................................... 1
1Switch Interfaces.................................................................................................................................... 1
1.1 PCI Express Link Interface .............................................................................................................. 2
1.1.1 Transmitter ................................................................................................................................ 3
1.1.2 Receiver .................................................................................................................................... 5
1.1.3 Reference Clock........................................................................................................................ 6
1.1.4 Channel..................................................................................................................................... 7
1.2 NT Function ..................................................................................................................................... 8
1.3 Hot Plug Controller Interface ........................................................................................................... 9
1.4 JTAG Interface .............................................................................................................................. 10
1.5 I2C Interface ................................................................................................................................... 11
1.6 PCI Express Port Good Indicators................................................................................................. 11
1.7 Strapping Balls............................................................................................................................... 12
1.8 GPIO Balls..................................................................................................................................... 14
1.9 Power Supplies, Sequencing, and De-Coupling ........................................................................... 14
1.9.1 Power Supplies ....................................................................................................................... 14
1.9.2 Power Sequencing .................................................................................................................. 15
1.9.3 Board-Level De-Coupling........................................................................................................ 16
2PCB Layout and Layer Stackup Considerations.................................................................................. 18
2.1 BGA Routing Escape and De-Coupling Capacitor Placement...................................................... 18
2.2 Add-In Board Routing .................................................................................................................... 20
2.3 System Board Routing................................................................................................................... 21
2.4 Midbus Routing.............................................................................................................................. 21
2.5 PCB Layer Stackup Considerations .............................................................................................. 22
3References........................................................................................................................................... 23
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
vi © 2007 PLX Technology, Inc. All Rights Reserved.
Figures
Figure 1. Sample PCI Express Link Block Diagram ..................................................................................... 2
Figure 2. Single-Ended versus Differential Voltage...................................................................................... 3
Figure 3. Transport Delay Delta ................................................................................................................... 7
Figure 4. PEX 8612 RefClk Circuitry ............................................................................................................ 7
Figure 5. Enable NT Function with NT Strapping Balls ................................................................................ 8
Figure 6. Disable NT Function with NT Strapping Balls ............................................................................... 8
Figure 7. PHPC Circuit Block Diagram......................................................................................................... 9
Figure 8. JTAG Interface Block Diagram.................................................................................................... 10
Figure 9. I2C Interface Block Diagram ........................................................................................................ 11
Figure 10. Power Balls and Capacitor Placement...................................................................................... 14
Figure 11. Power Plane Impedance versus Frequency ............................................................................. 16
Figure 12. Capacitor Footprint Effects on Series Inductance.....................................................................17
Figure 13. Top Layer BGA Layout and Routing Escape ............................................................................ 19
Figure 14. Inside Layer BGA Layout and Routing Escape......................................................................... 19
Figure 15. Add-in Board Routing to PCI Express Gold Fingers ................................................................. 20
Figure 16. System Board Routing to PCI Express Slot .............................................................................. 21
Figure 17. PCI Express Midbus Routing Example ..................................................................................... 21
Tables
Table 1. Receiver Equalization Settings....................................................................................................... 5
Table 2. PEX 8612 LED On/Off Patterns, by State .................................................................................... 11
Table 3. Configuration Strapping Balls....................................................................................................... 12
Table 4. STRAP_RESERVED Ball External Pull-Up/Pull-Down Resistor Requirements .......................... 13
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. vii
Preface
Notice
This document contains PLX Confidential and Proprietary information. The contents of this document may
not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX
Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to
entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX
manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or
adequacy of this information. The information in this document is subject to change without notice.
Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for
any errors, incidental or consequential damages in connection with the furnishing, performance, or use of
this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use
of this manual, for loss or claims by third parties, which may arise through the use of the PEX 8612, or for
any damage or loss caused by deletion of data as a result of malfunction or repair.
Revision History
Date Version Comments
October 1, 2007 1.0 Initial release.
October 5, 2007 1.1 Updated signal names listed in Table 3 and Table 4.
Applied miscellaneous corrections and enhancements.
October 17, 2007 1.2
Revised Table 4 pull-up/pull-down resistor recommendations
for STRAP_RESERVED[2:0].
Applied miscellaneous corrections and enhancements.
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PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 1
Introduction
This quick start hardware design guide is an overview of PLX Technology’s ExpressLane™ PEX 8612
PCI Express Switch and provides examples of how to connect to the various switch interfaces.
1Switch Interfaces
The PEX 8612 device is a 12-Lane, 3-Port PCI Express Gen2 switch, designed for high-availability and
high-performance systems. Its signal interface is grouped into the following functional blocks:
PCI Express Link interface
NT function
Hot Plug Controller interface
JTAG interface
I2C interface
PCI Express Port Good indicators
Strapping balls
GPIO balls
Power supply
1.1 PCI Express Link Interface
PLX’s PEX 8612 is a 12-Lane, 3-Port PCI Express 2.0 (that is, Gen2)-compliant switch. PCI Express 2.0
supports transfer rates of 5.0 GT/s per Lane. The Physical Media Attachment (PMA) Layer for each Lane
is implemented as a SerDes transceiver, which is composed of a transmit path and receive path. The
transmit path typically contains a serializer, Phase Lock Loop (PLL), and Current Mode Logic (CML)
driver. The receive path consists of a CML Receiver buffer, Clock and Data Recovery circuit (CDR), and
a de-serializer.
As the PCI Express Base Specification, Revision 2.0, continues to mature, so does its description of the
Physical Layer Electrical sub-block. A PCI Express serial Link is described in terms of four components –
Transmitter, Receiver, Reference Clock, and Channel. The Transmitter and Receiver elements are
typically integrated into PCI Express silicon. The Channel and Reference Clock are implemented at the
system level. The PCI Express interoperability matrix implies that all four elements must support 5.0 GT/s
for the Link to successfully run at 5.0 GT/s. If any one element is not 5.0 GT/s-compliant, the Link will not
be able to operate beyond 2.5 GT/s. Another important concept is that 2.5 GT/s is not a subset of
5.0 GT/s. This implies that a design targeted to meet 5.0 GT/s might not successfully run in a 2.5 GT/s
environment, if those design criteria are not met, as well.
Figure 1 illustrates a block diagram of a sample PCI Express Link.
PLL1
CDR1 PLL2
CDR2
RefClk
Rx1
Rx2Tx1
Tx2
Channel
Channel
Device 1 Device 2
Figure 1. Sample PCI Express Link Block Diagram
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
2 © 2007 PLX Technology, Inc. All Rights Reserved.
1.1.1 Transmitter
A PCI Express Transmitter is typically a differential CML driver that transmits an 8b/10b-encoded
bitstream across the Channel to the Receiver. The minimum differential voltage swing (VTX-DIFF-PP) of the
Transmitter is 800 mV at both 2.5 GT/s and 5.0 GT/s. The DC common mode voltage can be anywhere
between 0 and 3.6V; hence, AC-coupling capacitors are required to isolate the Transmitter’s
DC component from the Receiver’s fixed 0V DC common mode voltage. The AC-coupling capacitor
values must range between 75 and 200 nF, to ensure that the lower frequency components of the
8b/10b-encoded data are not affected. Figure 2 illustrates what a generic PCI Express differential signal
looks like, as compared to a single-ended signal.
Note: The swing values listed in Figure 2 (400 mV and 800 mV) do not reflect default PLX register values.
PCI Express Transmitters are required to support de-emphasis. The role of de-emphasis is to increase
the resultant signal energy of the highest data frequencies and to counteract the frequency-dependent
Channel losses. De-emphasis does this by reducing the amount of energy used to transmit multiple
successive bits of the same polarity (that is, non-transition bits), compared to the amount of energy used
to transmit a set of transition bits (0 -> 1 or 1 -> 0). Transition bits have higher frequency components
than non-transition bits and are, therefore, more distorted by the low-pass Channel. This effect is one
aspect of Inter-Symbol Interference (ISI), which is a source of deterministic jitter in the system.
The PCI Express Base Specification, Revision 2.0, defines two de-emphasis levels for devices running at
5.0 GT/s – 3.0 to 4.0 dB and 5.5 to 6.5 dB. The desired de-emphasis level for a given Link is advertised
by the downstream Ports of a switch during Link recovery. Endpoints and the upstream device capture
this value and set their de-emphasis levels, accordingly. Longer Links should use 6.0 dB, whereas shorter
Links can use 3.5 dB.
The standard de-emphasis level is selectable by way of the PEX 8612 Link Control 2 register Selectable
De-Emphasis bit (Configuration register, offset 98h[6]).
TXp
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 3
TXn
VTX-DC-CM
TXp - TXn
400mV
800mV
0V
Figure 2. Single-Ended versus Differential Voltage
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
4 © 2007 PLX Technology, Inc. All Rights Reserved.
In addition to supporting the standard de-emphasis levels, the PEX 8612 has a number of programmable
registers to control the Transmitter’s characteristics, such as drive level and de-emphasis. The SerDes
Transmitter Control registers exist in Station Ports 0 and 4*, each controlling a bank of SerDes (Port 0 –
Lanes [0-7]; Port 4 – Lanes [24-27]). Registers at offsets B84h to B90h are the SerDes Drive Level
registers. Registers at offsets B94h to BA0h are the Post-Cursor Emphasis Level registers. The SerDes
Drive Level and Post-Cursor Emphasis Level registers work in conjunction, to determine the transition
and non-transition bits driver swing and de-emphasis ratio. The PLX driver is implemented as a two-tap
driver. When transition bits are transmitted, the SerDes Drive Level and Post-Cursor Emphasis Level
register levels are added together; for non-transition bits, the two values are subtracted. Using Equation 1,
Example 1 presents a calculation of what the drive level and de-emphasis level would be for a given set
of register values.
Systems with short Links and/or power-sensitive applications (such as mobile platforms) can optionally
decide to use low-swing output drive levels (400 mVP-P). In the PEX 8612, this can be accomplished by
setting the SerDes Drive Level register for a specific Lane to 01000b (400 mVP-P), and the Post-Cursor
Emphasis Level register to 00000b (no de-emphasis).
Equation 1. PEX 8612 Transmitter Drive Level
(a) VTRANS = VDRV_LVL + VPOST_EMP
(b) VNON-TRANS = VDRV_LVL - VPOST_EMP
(c) VTX-DE-RATIO-3.5DB = 20 log (VPOST_EMP/ VDRV_LVL)
Example 1. Setting for Lane 0 Transmitter to 3.5 dB
Port 0 SerDes Drive Level register, offset B84h[4:0] = 01111b (750 mVpp)
Port 0 Post-Cursor Emphasis Level register, offset B94h[4:0] = 01101b (162.5 mVpp)
VTRANS = 750 mV + 162.5 mV = 912.5 mVpp
VNON-TRANS = 750 mV - 162.5 mV = 587.5 mVpp
VTX-DE-RATIO-3.5 DB = 20 log (587.5/912.5) = -3.82 dB
Note: *Port 4 on PEX 8612 is an internal Port (that is, the Port is not used externally to the PEX 8612)
that holds the Station-dependent registers for Station 1. Because the Transmitter Control registers are
Station-dependent, Port 4 must be used to program these registers for Station 1.
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 5
1.1.2 Receiver
The Receiver’s role is to recover the differential bitstream coming across the Channel from the
Transmitter, and latch it so it can be de-serialized and forwarded to the logical sub-block. The main
components of a Receiver are the Receive buffer and CDR circuit.
The PCI Express Receive buffer input threshold is 175 mV for a 2.5 GT/s data rate and 120 mV for
a 5.0 GT/s data rate. PCI Express Receivers are required to have a DC common mode voltage of 0V.
The Receive buffer provides bits to the CDR circuit, which samples each bit and forwards them to the
de-serializer. Digital-based CDRs must track the edges of the incoming bits and determine the best time
to sample each bit, which is typically the center of the eye (0.5 UI). The CDR’s base Reference Clock(s) is
provided by the PLL. A CDR must be able to track either a fixed-phase offset (common clock system) or
small continuous phase offset (non-common clock system), between the incoming data/clock and the
CDR’s base clock. Jitter on the base CDR clock and/or the incoming data stream can cause bit sampling
errors to occur.
Although not explicitly mentioned in the PCI Express Base Specification, Revision 2.0, Receivers may
implement some form of Receiver equalization, to help compensate for the Channel’s low-pass
characteristics. In general, Receiver equalization only needs to be used on longer Channels.
The PEX 8612 provides a programmable Receiver Equalization function. Ports 0 and 4* each have a set
of Receiver Equalizer registers, located at offsets BA4h and BA8h, to control a group of eight (Port 0) or
four (Port 4) SerDes. Each individual SerDes has a 4-bit control word. Table 1 describes the Receiver
equalization effects.
Table 1. Receiver Equalization Settings
SerDes NReceiver Equalizer[3:0] Equalization
0000b Off
0010b Low
0110b Medium
1110b High
Note: *Port 4 on PEX 8612 is an internal Port (that is, the Port is not used externally to the PEX 8612)
that holds the Station-dependent registers for Station 1. Because the Transmitter Control registers are
Station-dependent, Port 4 must be used to program these registers for Station 1.
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
6 © 2007 PLX Technology, Inc. All Rights Reserved.
1.1.3 Reference Clock
The Reference Clock is a key component to a Link that was often overlooked by system designers in first
generation PCI Express systems. The Reference Clock provides a 100-MHz base frequency for the PLL.
The PLL provides a frequency synthesis function, generating the higher-speed clocks required to transmit
data at a rate of either 2.5 GT/s or 5.0 GT/s. In designs that implement digital CDRs, the PLL output also
provides the Reference Clocks to the CDR circuit; hence, jitter on the Reference Clock can affect both the
Transmitter and Receiver components.
Note: In Gen2 PCI Express, the allowable reference jitter is much tighter than in Gen1 systems
(3.1 ps rms); therefore, it is important to select the high-quality PCI Express clock sources.
The PLL has a low-pass, filter-jitter transfer function from its reference input to the high-speed output
clocks; therefore, it is important to minimize the low-frequency jitter in the pass band of the PLL.
Low-frequency jitter, below the PLL loop bandwidth, passes directly to output clocks, which in turn, drives
the Transmitter and CDR circuits. Jitter, at the loop bandwidth, is especially critical; given most PLLs have
some amount of gain at the cut-off frequency. High-frequency jitter, on the Reference Clock input above
the loop bandwidth, is typically attenuated, and therefore, is of less concern.
The jitter transfer function of a CDR circuit is modeled as a high-pass filter. Low-frequency jitter, including
Spread-Spectrum Clock (SSC) modulation, is tracked by the CDR circuit, whereas higher-frequency jitter
content causes eye closure at the Receiver. The cut-off frequency of the CDR high-pass function is
usually less than the cut-off frequency of the Transmitter PLL low-pass function. The pass band between
these cut-off frequencies is where Reference Clock jitter causes the most problems.
In PCI Express, the cut-off frequency of the PLL is specified to be between 1.5 to 22 MHz for 2.5 GT/s
data rates and 8 to 16 MHz for 5.0 GT/s data rates. The purpose of these bandwidth ranges is to limit the
difference in PLL bandwidth on the two sides of a Link, while still providing flexibility, in terms of PLL
design. This is especially important for common clock systems, where the amount of jitter appearing at
the CDR is defined by the difference function between the Tx and Rx PLLs.
Another mechanism that can increase the jitter seen by a Receiver in common-clocked systems is the
fixed-phase difference (transport delay delta) between Transmitter data at the CDR input and a
Receiver’s recovered clock, relative to the 100-MHz Reference Clock source. This delay should not
exceed 12 ns, per the PCI Express Base Specification, Revision 2.0. The delay budget includes on-chip
and off-chip delays. In general terms, all Reference Clock nets in a system should be matched
within 38.1 cm (15 in.) (per the PCI Express Card Electromechanical (CEM) Specification, Revision 2.0).
Figure 3 illustrates the Reference Clock transport delay delta.
The PEX 8612 PEX_REFCLKp/n signal pair is the Reference Clock Input buffer. It has an internal
DC-biasing circuit, and therefore, should be AC-coupled from the RefClk source driver. Use 0.01 to 0.1 µF
capacitors (0603- or 0402-size) to AC-couple the Reference Clock input, as illustrated in Figure 4.
PLL1
CDR1 PLL2
CDR2
RefClk
Rx1
Rx2Tx1
Tx2
Channel
Channel
Device 1 Device 2
T1
T2
T3
T4
T5
Transport Delay Delta = (T1+T2+T3) – (T4+T5) < 12 ns
Figure 3. Transport Delay Delta
33 ohms
0.1 µF
PEX 8612
PCI Express
RefClk Driver
PEX_REFCLKp
PEX_REFCLKn
Source termination placed close to driver
Place AC-coupling capacitors
near PEX_REFCLKn/p balls
33 ohms
49.9 ohms 49.9 ohms
0.1 µF
Figure 4. PEX 8612 RefClk Circuitry
1.1.4 Channel
In PCI Express, the Channel refers to the board-level copper interconnects (including connectors) that lie
between the Transmitter and Receiver balls. The Channel is represented as a transmission line, which
can be modeled by a distributed series of Resistance Inductance Conductance Capacitance (RLGC)
circuits. A transmission line behaves like a low-pass filter, due to frequency dependent dielectric and
conductor losses.
In PCI Express, the Channel contributes to amplitude loss and deterministic jitter. It is important to
minimize discontinuities, such as vias and stubs, to minimize Channel effects.
A common issue that presents itself to PCI Express system designers is determining allowable Channel
length. This is a question that does not have a simple answer. The best way to determine whether a
particular Channel length is allowable is to simulate the Channel, using PLX-provided HSPICE models.
The PCI Express Base Specification, Revision 2.0, provides additional details for simulating a Channel.
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 7
1.2 NT Function
The PEX 8612 supports the Non-Transparent function (NT mode). Only Port 0 or 1 of Station 0 can be
configured as the NT Port. There are three ways to enable the NT function and configure the NT Port for
the PEX 8612.
Method 1. Use of the three NT Strapping balls:
STRAP_NT_ENABLE#
STRAP_NT_UPSTREAM_PORTSEL[1:0]
Pull down the STRAP_NT_ENABLE# to logic zero (0) to enable the NT function. Pull
STRAP_NT_UPSTREAM_PORTSEL[1:0] up or down, to select Port 0 or 1 as the NT Port at Station 0.
Method 2. Enable the NT function and configure the NT Port through the serial EEPROM.
Method 3. Use the PEX 8612 I2C Port 0 to enable the NT function and configure the NT Port. Figure 5
illustrates how to implement the NT functions, through the NT Strapping balls. Figure 6 illustrates how to
disable the NT functions, through the PEX 8612’s NT Strapping balls.
Figure 5. Enable NT Function with NT Strapping Balls
2.5V
STRAP_NT_UPSTREAM_PORTSEL0
STRAP_NT_UPSTREAM_PORTSEL1
STRAP_NT_ENABLE#
Figure 6. Disable NT Function with NT Strapping Balls
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
8 © 2007 PLX Technology, Inc. All Rights Reserved.
1.3 Hot Plug Controller Interface
The PEX 8612 supports two Parallel Hot Plug Controllers (PHPCs), to service its downstream Ports. The
PHPCs are called Hot Plug Ports A and B. They are internally connected to Transparent downstream Hot
Plug-capable Port 1 (if it is used) and Port 5, respectively. As long as the related Port is used, the PHPC
functions normally. Otherwise, the PHPC is disabled. Each PHPC has 10 Hot Plug signal balls, for
controlling various Hot Plug-related functions:
HP_ATNLED_[n]#
HP_BUTTON_[n]#
HP_CLKEN_[n]#
HP_MRL_[n]#
HP_PERST_[n]#
HP_PRSNT_[n]#
HP_PWR_GOOD_[n]
HP_PWREN_[n]
HP_PWRFLT_[n]#
HP_PWRLED_[n]#
where “n” is A and/or B
Figure 7 shows an example of how to connect the PEX 8612’s PHPC to the external circuit, to build
a complete PHPC circuit.
Figure 7. PHPC Circuit Block Diagram
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 9
1.4 JTAG Interface
The PEX 8612 supports a five-ball JTAG Boundary Scan interface. The JTAG interface consists of the
following signals:
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST#
At the board level, pull JTAG_TCK, JTAG_TDI, and JTAG_TMS up to 2.5V with 1- to 5-kohm resistors.
Pull JTAG_TRST# down to VSS with a 1- to 5-kohm resistor. Because the PEX 8612 JTAG clock
frequency can be as high as 25 MHz, a 15-ohm series terminator can be added to TCK, TDI, and TDO, to
improve signal quality. Figure 8 illustrates a generic JTAG interconnection.
Figure 8. JTAG Interface Block Diagram
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
10 © 2007 PLX Technology, Inc. All Rights Reserved.
1.5 I2C Interface
The PEX 8612 also implements a two-wire I2C Slave interface (I2C Port 0). Through its I2C_SCL0 and
I2C_SDA0 balls, the PEX 8612 allows an external I2C Master to read and write device registers through
an out-of-band mechanism. The simplest way to implement an I2C interface to the PEX 8612 is illustrated
in Figure 9.
Figure 9. I2C Interface Block Diagram
1.6 PCI Express Port Good Indicators
The PEX 8612 provides up to three Active-Low “Port Good” Output balls, PEX_PORT_GOOD[5, 1, 0]#,
for the PCI Express Ports. These Output balls can be used to build the Port status LED circuits, to
indicate the status of each PEX 8612 Port. Each Port has five states, which are related to Link status,
Channel speed, and the Port’s Lane width. Table 2 lists the relationship of the LED On/Off patterns to the
Port status.
Table 2. PEX 8612 LED On/Off Patterns, by State
State LED Pattern
Link is down Off
Link is up, 5 GT/s, all Lanes are up On
Link is up, 5 GT/s, reduced Lanes are up Blinking, 0.5 seconds On, 0.5 seconds Off
Link is up, 2.5 GT/s, all Lanes are up Blinking, 1.5 seconds On, 0.5 seconds Off
Link is up, 2.5 GT/s, reduced Lanes are up Blinking, 0.5 seconds On, 1.5 seconds Off
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 11
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
12 © 2007 PLX Technology, Inc. All Rights Reserved.
1.7 Strapping Balls
The PEX 8612 has a total of 29 Strapping balls. Eleven service different configuration functions and
12 are STRAP_RESERVED balls. For the PEX 8612, none of the Strapping balls have internal pull-up nor
pull-down resistors. If the Port configuration is fixed, use external pull-up or pull-down resistors to
hardwire these Strapping balls to the values corresponding to the Port configuration values. If a particular
function is not used, the related Configuration Strapping balls must be pulled up or down to known,
disabled logic states. (Refer to the PEX 8612 Data Book for details.) The STRAP_RESERVED balls have
their own pull-up and pull-down resistor requirements. Table 3 lists the names and functions of the
PEX 8612 Configuration Strapping balls. Table 4 lists the STRAP_RESERVED ball pull-up/pull-down
resistor requirements.
Table 3. Configuration Strapping Balls
Ball/Signal Name Function
STRAP_NT_ENABLE# Enable NT function.
STRAP_NT_UPSTRM_PORTSEL0
STRAP_NT_UPSTRM_PORTSEL1
NT Port select.
STRAP_STN0_PORTCFG1 Port configuration per Station.
STRAP_TESTMODE0
STRAP_TESTMODE1
STRAP_TESTMODE2
STRAP_TESTMODE3
Test mode function select.
STRAP_UPSTRM_PORTSEL0
STRAP_UPSTRM_PORTSEL1
STRAP_UPSTRM_PORTSEL2
Upstream Port select.
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 13
Table 4. STRAP_RESERVED Ball External Pull-Up/Pull-Down Resistor Requirements
Ball/Signal Name Pull-Up/Pull-Down
STRAP_RESERVED0 Must be tied Low
STRAP_RESERVED1 Must be pulled High
STRAP_RESERVED2 Must be pulled High
STRAP_RESERVED3 Must be tied High
STRAP_RESERVED4 Must be tied directly to Ground (VSS)
STRAP_RESERVED6 Must be tied High
STRAP_RESERVED7 Must be tied High
STRAP_RESERVED8 Must be tied directly to Ground (VSS)
STRAP_RESERVED9 Must be tied directly to Ground (VSS)
STRAP_RESERVED13 Must be tied directly to Ground (VSS)
STRAP_RESERVED16 Must be tied directly to Ground (VSS)
STRAP_RESERVED17# Must be tied High
1.8 GPIO Balls
The PEX 8612 has 20 GPIO balls – 17 are dedicated GPIO balls, and three share GPIO function and
PEX_PORT_GOOD[5, 1, 0]# functions in standard operation. Depending upon the settings of the Test
mode balls, STRAP_TESTMODE[3:0], the GPIO balls can be set as input, output, and/or bidirectional.
1.9 Power Supplies, Sequencing, and De-Coupling
The PEX 8612’s maximum power consumption is approximately 5W. Special cooling requirements may
exist, depending upon the system environment. (Refer to the PEX 8612 Data Book for details.)
1.9.1 Power Supplies
The PEX 8612 has the following Power ball groups:
VDD10 – Digital core logic supply
VDD10A – SerDes analog supply
VDD25 – Hot Plug, serial EEPROM, I2C, JTAG, Port Status indicators, I/O buffers
VDD25A – PEX_REFCLK PLL supply
At the board level, VDD10 and VDD10A can share a common 1.0V ±5% power plane, and VDD25 and
VDD25A can share a common 2.5V power plane. The current demands for these supplies can be high,
depending upon the device (approximately 80 mA per Lane plus 32 mA); therefore, ensure that the power
plane is sufficiently sized, to support the specified operating current. For best performance, the 1.0V ±5%
plane should have an adjacent ground plane that provides an interplane capacitor to supply
high-frequency transient currents. Provide a sufficient number of discrete capacitors for mid- and
low-frequency de-coupling. The recommendation is that 0201-sized capacitors be used in close proximity
to these power balls, as illustrated in Figure 10.
Figure 10. Power Balls and Capacitor Placement
PEX 8612-AA Quick Start Hardware Design Guide, Version 1.2
14 © 2007 PLX Technology, Inc. All Rights Reserved.
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