Power integrations Scale-2 1SC0450E2B0 Instructions for use

SCALE™-2 1SC0450E2B0
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SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
Single-Channel Cost-Effective Driver Core for IGBTs up to 4500V and 6500V
Abstract
The 1SC0450E2B0 single-channel SCALE™-2 driver core combines unrivalled compactness with broad
applicability and cost-effectiveness. It is designed for industrial and traction applications requiring high
reliability. The 1SC0450E2B0 drives all usual high-voltage IGBT modules up to 4500V and 6500V. Up to four
parallel-connected IGBT modules can be driven to cover higher power ratings. Multi-level topologies
involving 3300V or 4500V IGBTs with higher isolation requirements can also be easily supported by the
1SC0450E2B0.
The 1SC0450E2B0 supports maximal design flexibility as no fiber-optic links are assembled on the driver
board. Gate drive input and output signals are provided over dedicated electrical interface connectors.
The 1SC0450E2B0 is the most compact driver core in its voltage and power range, featuring a footprint of
only 60mm x 90mm and a maximum insertion height of 27.5mm. It allows even the most restricted insertion
spaces to be efficiently used.
Fig. 1 1SC0450E2B0 driver core

SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
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Contents
Driver Overview ............................................................................................................................. 4
Mechanical Dimensions.................................................................................................................. 5
Pin Designation .............................................................................................................................. 7
Recommended Interface Circuitry for the Primary-Side Connector.............................................. 8
Description of Primary-Side Interface ........................................................................................... 8
General...............................................................................................................................8
VCC terminal ....................................................................................................................... 8
VDC terminal.......................................................................................................................8
GND ...................................................................................................................................9
SO (status output)...............................................................................................................9
Recommended Interface Circuitry for the Secondary Side Connectors ........................................ 9
Pins 6 to 16.........................................................................................................................9
Pins 17 to 32..................................................................................................................... 10
Description of Secondary-Side Interfaces ................................................................................... 10
General............................................................................................................................. 10
DC/DC output (VISO), emitter (VE) and COM terminals......................................................... 11
Reference terminal (REF) ................................................................................................... 11
Collector sense (VCE)......................................................................................................... 11
Input for adjusting the turn-off delay in fault condition (CSHD) ............................................. 14
Active Clamping (ACL)........................................................................................................ 15
Gate turn-on (GH) and turn-off (GL) terminals ..................................................................... 15
Gate Boosting Power Supply (VGB) ..................................................................................... 16
Gate Boosting Signal (GBS) ................................................................................................ 16
Gate Drive Input (IN)......................................................................................................... 16
Status Feedback /Fault input (OUT) .................................................................................... 16
How Do 1SC0450E2B0 SCALE-2 Drivers Work in Detail? ............................................................ 19
Power supply and electrical isolation ................................................................................... 19
Power-supply monitoring.................................................................................................... 19
Parallel connection of IGBT modules ................................................................................... 19
3-level or multilevel topologies............................................................................................ 19
Gate Boosting.................................................................................................................... 20
Bibliography ................................................................................................................................. 22
The Information Source: SCALE-2 Driver Data Sheets ................................................................ 23
Quite Special: Customized SCALE-2 Drivers ................................................................................ 23
Technical Support ........................................................................................................................ 23
Quality.......................................................................................................................................... 23
Legal Disclaimer ........................................................................................................................... 23

SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
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Ordering Information................................................................................................................... 24
Information about Other Products .............................................................................................. 24
Power Integrations Sales Offices.................................................................................................25

SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
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Driver Overview
The 1SC0450E2B0 is a driver core equipped with the latest SCALE-2 chipset from Power Integrations /1/.
The SCALE-2 chipset comprises a set of application-specific integrated circuits (ASICs) that cover the main
functions needed to design intelligent gate drivers. The SCALE-2 driver chipset is a further development of
the proven SCALE™-1 technology /2/.
The 1SC0450E2B0 targets medium- and high-power IGBT applications up to 6500V. The driver supports
switching frequencies up to 10kHz with best-in-class efficiency. The 1SC0450E2B0 comprises a complete
single-channel IGBT driver core, fully equipped with an isolated DC/DC converter, electrical interface for the
external use of fiber-optic transceivers, short-circuit protection, Advanced Active Clamping and supply-
voltage monitoring. Additional features such as gate boosting are also implemented and provide further
driving benefits.
Fig. 2 Block diagram of the 1SC0450E2B0 driver core

SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
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Mechanical Dimensions
Fig. 3 Interactive 3D drawing of the 1SC0450E2B0

SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
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Fig. 4 Mechanical drawing of the 1SC0450E2B0
The primary-side and secondary-side pin grid is 2.54mm (100mil) with a pin cross-section of
0.64mm x 0.64mm. Total outline dimensions of the board are 60mm x 90mm. The total height of the driver
is maximum 27.5mm measured from the bottom of the pin bodies to the top of the populated PCB.
Note that the mechanical fixing points are placed in the clearance and creepage paths. Insulated fixation
material (screws, distance bolts) must therefore be used in order not to reduce these. The fixing points
support M3 screw size.
Recommended diameter of solder pads: Ø 2mm (79mil)
Recommended diameter of drill holes: Ø 1mm (39mil)

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Preliminary Description & Application Manual
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Pin Designation
Pin No. and Name
Function
Primary Side
1
SO
Status output primary side; normally pulled up to VCC over a 10kΩresistor, pulled
down to low in case of a fault
2
GND
Ground
3
VCC
Supply voltage; 15V supply for primary side
4
VDC
DC/DC converter supply
5
GND
Ground
Secondary Side
6
VGB
Gate-boosting power supply
7
VISO
DC/DC output
8
COM
Secondary-side ground
9
CSHD
Set turn-off delay after fault detection; capacitor to COM
10
GH
Gate high; pulls gate high through turn-on resistor
11
GBS
Gate-boosting signal
12
VE
IGBT emitter
13
GL
Gate low; pulls gate low through turn-off resistor
14
ACL
Active clamping feedback; leave open if not used
15
REF
Set VCE detection threshold through resistor to VE
16
VCE
VCE sense; connect to IGBT collector through impedance network
17
COM
Secondary-side ground
18
VISO
DC/DC output
19
COM
Secondary-side ground
20
COM
Secondary-side ground
21
COM
Secondary-side ground
22
IN
Gate driving input; Inverted non-isolated signal input
23
COM
Secondary-side ground
24
COM
Secondary-side ground
25
COM
Secondary-side ground
26
OUT
Status output and external fault input
27
COM
Secondary-side ground
28
COM
Secondary-side ground
29
COM
Secondary-side ground
30
OUT
Status output and external fault input
31
OUT
Status output and external fault input
32
COM
Secondary-side ground

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Preliminary Description & Application Manual
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Recommended Interface Circuitry for the Primary-Side Connector
Fig. 5 Recommended user interface of the 1SC0450E2B0 (primary side)
Description of Primary-Side Interface
General
The primary-side interface of the 1SC0450E2B0 driver is very simple and easy to use.
The driver primary side is equipped with a 5-pin interface connector with the following terminals:
2x power-supply terminals VCC and VDC
2x ground terminals GND
1x status output SO (indicating a fault during primary-side under-voltage)
All inputs and outputs are ESD-protected.
VCC terminal
The driver has one VCC terminal on the interface connector to supply the primary-side electronics with 15V.
VDC terminal
The driver has one VDC terminal on the interface connector to supply the DC/DC converter for the secondary
side.
VDC should be supplied with 15V. It is recommended to connect the VCC and VDC terminals to a common
15V power supply. In that case, the driver limits the inrush current at startup and no external current
limitation of the voltage source for VDC is needed.

SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
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GND
Both ground pins must be connected together with low parasitic inductance. A common ground plane is
strongly recommended. Furthermore it is recommended to shield all primary-side circuitry with the ground
plane. The connecting distance between the ground pins must be kept to a minimum.
SO (status output)
When no primary-side under-voltage condition is detected, an internal pull-up resistor of 10kΩ keeps the
output level at the voltage level of VCC. When a primary-side supply under-voltage is detected, the status
output SO goes to low (connected to GND). The SO output is automatically reset (returning to the voltage
level of VCC) when the under-voltage on the primary side disappears.
The maximum SO current in a fault condition must not exceed the value specified in the driver data sheet
/3/.
Recommended Interface Circuitry for the Secondary Side Connectors
Pins 6 to 16
Fig. 6 Recommended user interface of the 1SC0450E2B0 (secondary-side pins 6 to 16) without gate
boosting (refer to chapter “Gate Boosting” and Fig. 11 for gate-boosting circuitry)

SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
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Pins 17 to 32
Fig. 7 Recommended command interface circuitry with Avago fiber-optic links HFBR-x522ETZ
Description of Secondary-Side Interfaces
General
The driver’s secondary side is equipped with an 11-pin and two 8-pin interface connectors.
The 11-pin interface connector features the following terminals:
1x DC/DC output terminal VISO
1x emitter terminal VE
1x secondary-side ground COM
1x collector sense terminal VCE
1x reference terminal REF for short-circuit protection
1x input terminal CSHD to set the turn-off delay after fault
1x active clamping terminal ACL
1x turn-on gate terminal GH
1x turn-off gate terminal GL
1x gate-boosting power supply VGB
1x gate-boosting signal GBS
The two 8-pin interface connectors combine the command interface and feature the following terminals:
1x DC/DC output terminal VISO
11x secondary-side ground COM
1x PWM input (inverted)
3x status feedback input/output (inverted)
All inputs and outputs are ESD-protected.

SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
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DC/DC output (VISO), emitter (VE) and COM terminals
The driver is equipped with blocking capacitors on the secondary side of the DC/DC converter (for values
refer to the data sheet /3/). IGBTs with a gate charge of up to 4.7µC can be driven without additional
external capacitors (C1and C2in Fig. 6 are not assembled). Eq. 1 and Eq. 2 give the recommended
capacitance value of C1and C2for gate charges above this value:
C1[μF]≥(QG[μC]-4.7)∙4
C1in Fig. 6; 4µF blocking capacitance
per 1µC gate charge between VISO
and VE
Eq. 1
C2=C1
2
C2in in Fig. 6; blocking capacitance
between VE and COM, half of the C1
value
Eq. 2
Example: IGBT modules with a gate charge of up to 42µC can be driven with external capacitances of
149.2µF between the VISO and VE terminals and 74.6µF between the VE and COM terminals (C1
and C2of Fig. 6).
If the capacitance C1(or C2) exceeds 200µF (or 100µF), please contact the Power Integrations support
service.
The blocking capacitors must be connected as close as possible to the driver’s terminal pins with minimum
inductance. Ceramic capacitors with a dielectric strength ≥25V are recommended.
No static load must be applied between VISO and VE, or between VE and COM. A static load can be applied
between VISO and COM if necessary.
Reference terminal (REF)
The reference terminal REF allows the threshold to be set for short-circuit protection with a resistor placed
between REF and VE (Rth of Fig. 6). An internal resistor of 68kΩ sets the default threshold value to 10.2V. It
can be reduced with the use of an external resistor Rth according to the following Eq. 3:
Rth󰇟kΩ󰇠=68∙Vth[V]
10.2-Vth[V]
with Vth<10.2V
Eq. 3
It is recommended to keep the reference voltage at its maximum default value of 10.2V (without using an
external resistor Rth).
Collector sense (VCE)
The collector sense must be connected to the IGBT collector with the circuit shown in Fig. 6 in order to
detect a short circuit condition.
General information and recommendations:
The overall value Rtot of the resistors Rvcei is calculated with equation Eq. 4:
Rtot=Rvcei=
n
i=1
Rvce1+...+Rvcen
Eq. 4
It is recommended to dimension the overall value Rtot of the resistors in order for a current IVce of
about 0.6…0.8mA to flow through them at the maximum DC-link voltage (Eq. 5). This current must
not exceed 0.8mA. It is recommended to use series-connected resistors; the minimum creepage and
clearance distances required for the application must be considered and the maximum voltage,

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power and temperature rating of the resistors used must not be exceeded. Dimensioning
recommendations are given below.
IVceVDC-link󰇛max󰇜
Rtot
=0.6.0.8mA
Eq. 5
All resistors Rvcei (i ≥1) must have the same value.
Rdiv allows the static threshold detection level VCEth to be increased if required (resistive voltage
divider with Rtot). Rdiv can be calculated with Eq. 6 in order to determine the static detection level
VCEth.
Rdiv[kΩ]=Rtot[kΩ]∙Vth󰇟V󰇠+VGL[V]
VCEth󰇟V󰇠-Vth[V]
(VCEth > Vth)
Eq. 6
|VGL| is the absolute value of the gate-emitter turn-off voltage at the driver output. It depends on
the driver load and can be found in the driver data sheet /3/. Vth is the reference value set at the
reference terminal REF as described in the “Reference terminal (REF)” section.
The recommended range for the overall capacitance value Ctot is given in Eq. 7:
Ctot=1
1
Cvcek
p
k=1
=1…4pF
Eq. 7
All capacitances Cvcek with k≥2 must have the same value.
The capacitance Cvce1 must be chosen such that the Eq. 8 is satisfied:
Cvce1
Ctot
=󰇛0.7…0.9󰇜∙Rtot
Rvce1+Rvce2
Eq. 8
The maximum voltage rating of the resistors and capacitors used must not be exceeded. Peak
values and average values must be considered. Dimensioning recommendations are given below.
The diodes D9and D10 must have a very low leakage current and a blocking voltage of >40V (e.g.
BAS416). Schottky diodes must be explicitly avoided.
Raand Caare used to set the response time.
Recommended values for 6500V IGBTs with DC-link voltages up to 4500V
Rvce1=Rvce2=…=Rvce30=200kΩ(500mW, 400Vpeak, 1%)
Rdiv=620kΩ(0603, 1%)
Cvce1=15pF (C0G, 1000V, 5%)
Cvce2=Cvce3=…=Cvce15=22pF (C0G, 630V, 5%)
Ca=22pF (C0G, 50V, 5%)
Rth=not assembled
Ra=refer to Table 1 below (0603, 1%)
This setup uses 30 resistors Rvcei and 15 capacitors Cvcek and leads to a static desaturation detection
threshold of about 201V.

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VDC-Link
Ra=68kΩ
Ra=91kΩ
Ra=120kΩ
4500V
5.3µs
6.9µs
9.0µs
3000V
5.3µs
7.0µs
9.1µs
2250V
5.5µs
7.0µs
9.1µs
1500V
7.2µs
8.0µs
9.4µs
1125V
9.9µs
10.3µs
11.1µs
900V
14.1µs
14.1µs
14.2µs
Table 1 Typical response time as a function of the resistance Raand the DC-link voltage VDC-Link
Table 1 gives indicative values only. The response time depends on the specific layout and the IGBT module
used. It is therefore recommended to measure the short-circuit duration in the final design.
Note that slow IGBT modules may report a wrong VCE desaturation fault at turn-on. It is therefore
recommended to test the setup under worst case conditions (maximum DC-link voltage, maximum collector
current and highest IGBT junction temperature). Please also refer to AN-1101 /4/ for more information.
Recommended values for 4500V IGBTs with DC-link voltages up to 3200V
Rvce1=Rvce2=…=Rvce20=220kΩ(500mW, 400Vpeak, 1%)
Rdiv=620kΩ(0603, 1%)
Cvce1=15pF (C0G, 1000V, 5%)
Cvce2=Cvce3=…=Cvce10=22pF (C0G, 630V, 5%)
Ca=22pF (C0G, 50V, 5%)
Rth=not assembled
Ra=refer to Table 2 below (0603, 1%)
This setup uses 20 resistors Rvcei and 10 capacitors Cvcek and leads to a static desaturation detection
threshold of about 150V.
VDC-Link
Ra=68kΩ
Ra=91kΩ
Ra=120kΩ
3200V
5.1µs
6.8µs
8.8µs
2000V
5.2µs
6.8µs
8.9µs
1500V
6.1µs
7.0µs
8.9µs
1000V
8.8µs
9.3µs
10.3µs
800V
12.7µs
13.1µs
12.9µs
Table 2 Typical response time as a function of the resistance Raand the DC-link voltage VDC-Link
Table 2 gives indicative values only. The response time depends on the specific layout and the IGBT module
used. It is therefore recommended to measure the short-circuit duration in the final design.
Note that slow IGBT modules may report a wrong VCE desaturation fault at turn-on. It is therefore
recommended to test the setup under worst case conditions (maximum DC-link voltage, maximum collector
current and highest IGBT junction temperature). Please also refer to AN-1101 /4/ for more information.

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Recommended values for 3300V IGBTs with DC-link voltages up to 2200V
Rvce1=Rvce2=…=Rvce14=220kΩ(500mW, 400Vpeak, 1%)
Rdiv=1.5MΩ(0603, 1%)
Cvce1=15pF (C0G, 1000V, 5%)
Cvce2=Cvce3=…=Cvce7=22pF (C0G, 630V, 5%)
Ca=22pF (C0G, 50V, 5%)
Rth=not assembled
Ra=refer to Table 3 below (0603, 1%)
This setup uses 14 resistors Rvcei and 7 capacitors Cvcek per channel and leads to a static desaturation
detection threshold of about 50V.
VDC-Link
Ra=68kΩ
Ra=91kΩ
Ra=120kΩ
2200V
5.3µs
7.0µs
9.0µs
1500V
5.3µs
7.0µs
9.0µs
1100V
5.4µs
7.0µs
9.1µs
700V
7.6µs
8.1µs
9.3µs
600V
17.0µs
14.4µs
13.7µs
Table 3 Typical response time as a function of the resistance Raand the DC-link voltage VDC-Link
Table 3 gives indicative values only. The response time depends on the specific layout and the IGBT module
used. It is therefore recommended to measure the short-circuit duration in the final design.
Note that slow IGBT modules may report a wrong VCE desaturation fault at turn-on. It is therefore
recommended to test the setup under worst case conditions (maximum DC-link voltage, maximum collector
current and highest IGBT junction temperature). Please also refer to AN-1101 /4/ for more information.
Input for adjusting the turn-off delay in fault condition (CSHD)
The terminal CSHD allows the delay in turning off the IGBT after a fault detection on the driver’s secondary
side (short-circuit, undervoltage, external fault input) to be determined with a capacitor Ccshd (C0G/50V) with
a maximum value of 10nF connected to COM. Table 4 shows the resulting delay as a function of the circuit
used at pin CSHD.
Circuit at pin CSHD
Typical turn-off delay Tcshd
Left open:
Tcshd=0.2μs
Eq. 9
Capacitor between CSHD and COM:
Tcshd[μs]= Ccshd[pF]
50 (Ccshd≤10nF)
Eq. 10
Table 4 Turn-off delay as a function of CSHD wiring
As soon as the fault turn-off delay time Tcshd has elapsed, the driver’s channel is automatically turned off.
The driver’s channel can also be turned off from the driver’s input IN within the turn-off delay time Tcshd
determined by the CSHD pin after a secondary-side fault detection.
Note that it will not be possible to turn the IGBT on during about 100ns per 100pF capacitance applied to
CSHD after a fault condition, starting from the turn-off event of the IGBT (minimum off-time required).

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Active Clamping (ACL)
Active clamping is a technique designed to partially turn on the power semiconductor as soon as the
collector-emitter voltage exceeds a predefined threshold. The power semiconductor is then kept in linear
operation.
Basic active clamping topologies implement a single feedback path from the IGBT’s collector through
transient voltage suppressor devices (TVS) to the IGBT gate. The 1SC0450E2B0 supports Advanced Active
Clamping from Power Integrations, where the feedback is also provided to the driver’s secondary side at pin
ACL (Fig. 6): as soon as the voltage at pin ACL exceeds about 1.3V, the turn-off MOSFET is progressively
switched off in order to improve the effectiveness of the active clamping and to reduce the losses in the
TVS. The turn-off MOSFET is turned completely off when the voltage at pin ACL approaches 20V (measured
to COM).
It is recommended to use the circuit shown in Fig. 6. The following parameters must be adapted to the
application:
For TVS D1, D2it is recommended to use:
-3300V IGBTs with DC-link voltages up to 2200V: Seven unidirectional 300V TVS and one
bidirectional 350V TVS. Good clamping results can be obtained with seven unidirectional TVS
P6SMB300A and one bidirectional TVS P6SMB350CA from Diotec.
-4500V IGBTs with DC-link voltages up to 3200V: Eight unidirectional 400V TVS and one
bidirectional 350V TVS. Good clamping results can be obtained with eight unidirectional TVS
P6SMB400A and one bidirectional TVS P6SMB350CA from Diotec.
-6500V IGBTs with DC-link voltages up to 4350V: Ten unidirectional 440V TVS and one
bidirectional 440V TVS. Good clamping results can be obtained with ten unidirectional TVS
P6SMB440A and one bidirectional TVS P6SMB440CA from Diotec.
At least one bidirectional TVS (D1) (≥300V for 3300V IGBTs, ≥350V for 4500V IGBTs, ≥440V for
6500V IGBTs) must be used in order to avoid negative current flowing through the TVS chain during
turn-on of the anti-parallel diode of the IGBT module due to its forward recovery behavior. Such a
current could, depending on the application, lead to under-voltage of the driver secondary-side
voltage VISO to VE (15V).
Note that it is possible to modify the number of TVS in a chain. The active clamping efficiency can
be improved by increasing the number of TVS used in a chain if the total breakdown voltage remains
at the same value. Note also that the active clamping efficiency is highly dependent on the type of
TVS used (e.g. manufacturer).
D3and D4: It is recommended to use Schottky diodes with blocking voltages >35V (>1A depending on
the application).
Please note that the diodes D3and D4must not be omitted if Advanced Active Clamping is used.
If active clamping is not used, the diode D4can be omitted. The pin ACLx must then be left open.
Gate turn-on (GH) and turn-off (GL) terminals
These terminals allow the turn-on (GH) and turn-off (GL) gate resistors to be connected to the gate of the
power semiconductor. The GH and GL pins are available as separated terminals in order to set the turn-on
and turn-off resistors independently without the use of an additional diode. Please refer to the driver data
sheet /3/ for the limit values of the gate resistors used.
A resistor between GL and COM of 6.8kΩ(other values are also possible) may be used in order to provide a
low-impedance path from the IGBT gate to the emitter even if the driver is not supplied with power. No
static load (e.g. resistors) must be placed between GL and the emitter terminal VE.

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Note, however, that it is not advisable to operate the power semiconductors within a half-bridge with a
driver in the event of a low supply voltage. Otherwise, a steep increase of VCE may cause partial turn-on of
these IGBTs.
Gate Boosting Power Supply (VGB)
The driver supports an increased IGBT turn-on voltage source VGB to perform gate boosting. The voltage is
generated by internal circuitry. No static load must be applied to VGB. Refer to the driver data sheet /3/ for
more information.
Gate Boosting Signal (GBS)
The gate-boosting signal GBS is an auxiliary signal that has the same time waveform –but different voltage
values –as the GH signal. Please refer to the driver data sheet for the exact voltage values /3/ and to the
”Gate Boosting” section for more information.
Note that no static load must be applied to GBS. Refer to the driver data sheet /3/ for more information.
Gate Drive Input (IN)
The gate drive input signal IN is inverted to the gate output. A transition to a low-level state at IN generates
a driver turn-on command while a transition to a high-level state generates a driver turn-off command. Also
refer to Table 5 and Fig. 8.
It is recommended to use the input circuitry of Fig. 7. The drive signal is then not inverted to the gate
output according to Table 5.
If other drive circuits are used, the following information must be considered:
The absolute maximum ratings of the driver data sheet /3/ must be respected.
The logic level thresholds of the input IN are given in the driver data sheet /3/.
The input IN features an internal pull-up current source of about 500µA which sets its potential to a
high-level state and assures an IGBT off-state condition if the pin is floating. Refer to the driver data
sheet /3/ for values.
Pin IN belongs to the secondary-side electrical circuit and follows the emitter potential of the driven
IGBT. It must be isolated against primary-side circuits, e. g. with fiber-optic links.
Drive Signal
T/R(1) Light
Input IN
Gate Output
Low
Off
High
Off-state
High
On
Low
On-state
Table 5 Signal input truth table correlated with the schematics of Fig. 7
Status Feedback /Fault input (OUT)
The OUT terminal is mainly used as a status feedback output. However, it also works as an input. When
OUT is externally shorted to COM for a minimum period of time (timing and threshold values according to
the driver data sheet /3/), the driver detects an external fault. The IGBT is then turned off after a delay
(
1
)T/R: Transmitter and receiver pair of a fiber-optic link

SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
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TCSHD (refer to the chapter “Input for adjusting the turn-off delay in fault condition (CSHD)”). Note that
failure to respect the minimum hold time may lead to incorrect driver behavior.
The recommended circuitry for using the OUT terminal as an external fault input is shown in Fig. 7
(transistor connected to “External fault input”). The external effective capacitance (components and board
parasitic capacitances referred to VISO, VE and COM) must not exceed the value given in the driver data
sheet /3/ to avoid unexpected driver fault triggering in normal operation.
In normal operation, each edge of the control signal IN is acknowledged by the driver with a short pulse
(OUT is switched to low for a short period of time; refer to driver data sheet /3/ for details). As this can be
observed by the host controller, this method allows simple and continuous monitoring of all drivers and
fiber-optic links of the system (Fig. 8).
Fig. 8 Driver behavior and status feedback in normal operation (Refer to Fig. 7 for the recommended
command interface)
The driver can detect three different secondary-side faults:
VCE-desaturation detection in case of a short-circuit; refer to chapter “Collector sense (VCE)”
Secondary-side supply under-voltage; refer to chapter “Power-supply monitoring”
External fault (as described above)
The signal truth table of Table 6 shows the behavior of the OUT signal in normal operation as well as in a
fault condition. Only the pulse length of OUT differs between normal operation (acknowledge) and the
different fault conditions.

SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
www.power.com/igbt-driver Page 18
Status
OUT
T/R(2) Light
Status Feedback
Idle
High
On
Low
Acknowledge
or fault pulse
Low
Off
High
Table 6 Signal truth table correlated with the schematics of Fig. 7
Fig. 9 shows the response of the driver in the event of an IGBT short-circuit condition. The fault status is
transferred to the status feedback terminal after the response time. The light is then driven “off” during the
delay to clear the fault state (8μs+Tcshd). The driver turns the IGBT off after the response time + delay time
Tcshd. The IGBT can be turned on again by applying a negative edge to the input IN after the fault status has
disappeared.
Fig. 9 Driver behavior and status feedback in the IGBT short-circuit condition
In case of a secondary-side supply under-voltage fault, the fault status remains active as long as this under-
voltage remains. The driver response in the event of a supply under-voltage on VISO-VE is shown in Fig. 10.
Fig. 10 Status feedback in the event of a secondary-side supply under-voltage
(
2
)T/R: Transmitter and receiver pair of a fiber-optic link

SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
www.power.com/igbt-driver Page 19
During power-up, the status feedback will also show a fault condition until the supply under-voltage
protection disappears.
If the OUT terminal is not used, it is recommended to connect the OUT pin to VISO via a pull-up resistor in
the range of 1.5kΩ to 10kΩ.
How Do 1SC0450E2B0 SCALE-2 Drivers Work in Detail?
Power supply and electrical isolation
The driver is equipped with a DC/DC converter to provide an electrically insulated power supply to the gate
driver circuitry. The transformer features basic insulation according to IEC 61800-5-1 as well as IEC 60664-1
between the primary and secondary sides.
Note that the driver requires a stabilized supply voltage.
Power-supply monitoring
The driver’s primary and secondary sides are equipped with a local under-voltage monitoring circuit.
In the event of a primary-side supply under-voltage, the under-voltage is signalized by the electrical status
output SO. A primary-side under-voltage will not automatically cause a gate turn-off command. This
condition has to be detected by the control logic which has to switch off and block the gate drive signal.
In case of a secondary-side supply under-voltage, the corresponding power semiconductor is driven with a
negative gate voltage after the delay in IGBT turn-off (refer to “Input for adjusting the turn-off delay in fault
condition (CSHD)”) to keep it in the off-state (the channel is blocked) and a fault condition is monitored on
the status output OUT until the supply voltage exceeds the reference level for enabling.
Parallel connection of IGBT modules
It is recommended to drive parallel-connected IGBT modules using a single 1SC0450E2B0 driver core.
Appropriate gate circuitry has to be used. Please contact the Power Integrations support service for more
information.
3-level or multilevel topologies
In applications with multi-level topologies, the turn-off sequence of the individual power semiconductors
usually needs to be controlled by the host controller in case of a detected fault condition (e.g. short circuit,
over-current), especially if no Advanced Active Clamping or Dynamic Advanced Active Clamping is
implemented.
In that case, the turn-off delay in the fault condition of the different drivers can be adjusted to match the
corresponding timing specifications. It is in particular possible to determine a specific turn-off delay for the
inner IGBTs of a 3-level NPC topology as described in the section: “Input for adjusting the turn-off delay in
fault condition (CSHD)”. The driver’s response time can also be adapted accordingly if required.
Note however that Advanced Active Clamping offers simple and safe protection that allows excessive
collector-emitter overvoltages to be avoided in case of wrong commutation sequences in the short-circuit
condition of 3-level converter topologies (refer to /6/ and /7/ for more information).

SCALE™-2 1SC0450E2B0
Preliminary Description & Application Manual
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Gate Boosting
The 1SC0450E2B0 driver supports gate boosting. This feature allows the commutation speed of the
collector-emitter voltage to be accelerated at turn-on after the critical phase of the diode reverse recovery
behavior to reduce the IGBT turn-on losses.
A dedicated external circuit as shown in Fig. 11 is required. Detailed gate-boosting recommendations are not
currently available.
Gate-boosting circuit principle
The “Gate Boosting Logic”according to Fig. 11 has to trigger the boosting function at the appropriate time
during the IGBT turn on transition as illustrated in Fig. 12:
The delay time between GBS and the required boosting time needs to be determined by the “Gate
Boosting Logic” circuit.
The pulse length of the boosting pulse also needs to be determined by the “Gate Boosting Logic”
circuit. It must be limited to a few microseconds.
A turn-on pulse of the gate-boosting power switch Q1will be generated. This will lead to an increased turn-
on gate current that will be injected into the IGBT gate over Rgb.
The boosting charge capability can be increased by adding an external capacitor Cgb. The minimum value Cgb
of the external capacitor can be calculated according to Eq. 11.
Cgb󰇟nF󰇠=Qgb󰇟nC󰇠
VGH[V]+VGL[V]-22
Cgb≥0
Eq. 11
where Qgb stands for the required boosting gate charge and has to be determined according to the IGBT
module gate charge requirements. VGH and VGL are the absolute values of the turn-on and turn-off voltage at
the driver output respectively. Their value can be found in the driver data sheet /3/. Note that Eq. 11
assumes a full discharge of Cgb during a gate-boosting event (worst case).
The gate-boosting capability is further limited by the minimum time span between two consecutive gate
turn-on commands as well as by the gate-boosting power. The minimum required time Tmin between two
consecutive gate turn-on commands is given by Eq. 12. The gate-boosting efficiency is reduced if Eq. 12 is
not respected.
Tmin󰇟μs󰇠=11∙ 󰇧1+ 22+Cgb󰇟nF󰇠
22 󰇨+Tgb[μs]
Eq. 12
Tgb stands for the gate-boosting pulse length (Fig. 12). It is recommended to limit it to 1…5μs.
The maximum gate-boosting power must be within the absolute maximum ratings of the driver data sheet
/3/. Eq. 13 gives a worst case approximation of the real gate-boosting power Pgb. It is sufficient to design
the gate boosting such that Pgb is lower than the corresponding absolute maximum rating of the driver data
sheet /3/.
Pgb󰇟W󰇠=10-6∙Cgb󰇟nF󰇠+22+6.5∙Tgb󰇟μs󰇠∙󰇛VGH󰇟V󰇠VGL󰇟V󰇠󰇜∙f[kHz]
Eq. 13