Quest Engineering SUPER ELF User manual

SUPER
ELF
AN 1802 BASED
MICRO COMPUTER
BY
QUEST
COPYRIGHT 1977 BY QUEST ELECTRONICS

If you have any questions
or problems with your SUPER ELF
Write to:
SUPER ELF
QUEST ELECTRONICS
P.O. Box 4430
Santa Clara, California 95054

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CONTENTS PAGE
I INTRODUCTION
1. Manual contents 5
2. External Connections 5
II OPERATION
1. Hardware Assignments 6
2. Controls Description 6
3. Indicators and Displays Description 7
4. Operation without the ROM Monitor 8
5. Operation with the ROM Monitor 9
6. Using Single Step/Slow Step 10
III LOGIC DESIGN DESCRIPTION
1. Hexadecimal Keypad 11
2. Control Circuit: G R S W 13
3. Control Circuit: M P I L 15
4. Display Control 17
5. ROM/RAM Select 17
6. RAM/ROM Memory 19
7. State/Mode Display 19
8. Output/Data Display 23
9. Address Buffers/Latch 23
10. Address Display 25
11. Power Supply 25
12. Memory Saver 25
13. Video Generator 29
14. I/O Port Select 29
15. Q Circuit 29
16. Clock Generator 30
IV EXPANSION BUS
1. Capabilities 31
2. Constraints 31
V TROUBLESHOOTING
1. CPU Mode Control 34
2. Hexadecimal Keypad 34
3. Video Display 35
4. Data/Output Display 35

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5. Address Display 35
6. ROM/RAM Select 35
7. Load Mode 35
APPENDIX A PARTS LIST AND ASSEMBLY INSTRUCTIONS
1. Parts List - Basic 43
2. Parts List - Optional Low Address Display 46
3. Parts List - Optional High Address Display 47
4. Parts List - Optional Memory Saver 47
5. Parts List - Optional Accessories 48
6. Assembly Instructions - Basic 48
7. Assembly Instructions - Low Address Display 52
8. Assembly Instructions - High Address Display 52
9. Assembly Instructions - Memory Saver 52
10. Initial Checkout 53
APPENDIX B. DATA SHEETS
1. CDP1802 Microprocessor 57
2. CDP1861 Video Display Controller 78
FIGURES
1. Hexadecimal Keyboard 12
2. Control Circuit: G R S W 14
3. Control Circuit: M P I L 16
4. Display Control / ROM/RAM Select 18
5. RAM/ROM Memory 20
6. State/Mode Display 21
7. Output/Data Display 22
8. Address Buffers/latch 24
9. Address Display 26
10. Power supply / Memory Saver 27
11. Video Generator / I/O Port Select / Q Circuit / Clock 28
12. Expansion Bus Connections 33
13. Component Layout V 1.0 36
14. Component Layout V 2.0 37
15. Board Wiring Pattern V 1.0 Front 38
16. Board Wiring Pattern V 1.0 Back 39
17. Board Wiring Pattern V 2.0 Front 40
18. Board Wiring Pattern V 2.0 Back 41
19. Power and Ground Connections 42
CHANGE NOTICES 89

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I. INTRODUCTION
1. MANUAL CONTENTS
This manual consists of 5 major sections and two appendices. These 5
sections cover a) a description of the external connections required, b)
detailed descriptions of the operational features and how to use them, c)
logic diagrams/schematics and descriptions of how the logic works, d) the
expansion buses and how to use them, and e) hints on troubleshooting in
case of difficulty. Appendix A Contains parts lists and assembly instructions
for the basic SUPER ELF and available options. Appendix B contains
complete data sheets on both the 1802 CPU and the 1861 video graphics
generator.
2. EXTERNAL CONNECTIONS
All external connections are located in the upper left hand corner of
the printed circuit board. These connections are summarized here and
discussed in more detail in both Section III Logic Design and Appendix A
Parts List and Assembly Instructions. Starting at the upper left-hand corner
and going to the right, the BAT pair of connections are used for the 2.4V
standby Ni-Cad battery included in the memory saver option. Next are the
SW1 connections used to connect the battery to the RAMS (also used in the
memory saver option). Next are the SW2 connections used to disable the
Rams (also used in the memory saver option). Next are the AC connections
which are used to supply power to the board from the supplied plug-in
transformer. Going back to the upper left-hand corner and going down the
left edge is the SPKR connections. This is the amplified output of the Q line.
Normally a speaker is connected here for audio effects. However, these
connections can also be used as a serial output port or a relay driver. Next
are the VID connections which are an amplified composite (sync and video)
video signal of approximately 2 volts peak to peak. This output may drive a
video monitor directly or it may be used to drive an RF modulator to allow
connections to any TV set's antenna terminals. Some RF modulators
available for this use work much better than others. One that has been tested
and approved is the VAMP INC. Model RFVM-1 which is available through
QUEST.

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II OPERATION
1. Hardware ASSIGNMENTS
The SUPER ELF has been designed using the following hardware
assignments.
A. Video Display ON Op Code 62.
B. Video Display OFF Op Code 62.
C. HEX Keyboard Input OP Code 6C.
D. HEX Display Output Op Code 64.
E. Video Display Status Line EF1.
F. Input Switch Status Line EF4.
2. CONTROLS DESCRIPTION
The following is a description of the 24 key keyboard controls.
R RESET - Puts the CPU in the RESET mode. These additional
functions are reset if they were set.
1. Single Step
2. Memory Protect
3. ROM Select
L LOAD - Puts the CPU in the LOAD mode from the RESET mode.
I INPUT - Inputs data from the HEX keypad to the data bus in the
LOAD mode. In the RUN mode the EF4 status Line is LOW while
the key is depressed.
P MEMORY PROTECT - Prevents writing into memory. Useful in
the LOAD mode to verify the load. Cannot be used in the RUN
mode with the basic unexpanded board.
M MONITOR - Selects the on-board monitor. Replaces the first 20
HEX locations in memory with the monitor ROM. Location 20
HEX is used by the monitor, so user programs must not start
before location 21 HEX when using the monitor.
S SINGLE STEP - Allows single stepping through the program one
machine cycle at a time. The stopping point is the negative edge of
the TPA pulse of each machine cycle. This function is used with
the RUN switch. When in the SINGLE STEP mode, the
DATA/OUTPUT displays display the DATA bus.

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G RUN or GO puts the CPU in the RUN mode from either the WAIT
or RESET modes. If single step has been selected. Only one
machine cycle will be executed at a time with each momentary key
depression. Holding the RUN button down will result in slowly
stepping through the program one machine cycle at a time.
W WAIT puts the CPU in the WAIT state if previously in the RUN
state. Puts the CPU in the LOAD state from the RESET state.
Resets memory protect.
0 through F - HEX keypad stores the last TWO key depressions for
logout to the 8-bit data bus. The last key depressed is the least
significant 4 bits of the 8-bit data word.
3. INDICATORS AND DISPLAYS DESCRIPTION
The SUPER ELF has nine LEDS and two HEX displays (4 additional
HEX displays are optional.
A. The LEDS show:
ID FUNCTION
Q Status of Q line
L CPU in LOAD mode
R CPU in RESET mode
G CPU in RUN mode
W CPU in WAIT mode
0 CPU in state 0
1 CPU in state 1
2 CPU in state 2
3 CPU in state 3
NOTE: LED logic is active high.
B. The two HEX displays are normally an output port. However, in
the SINGLE STEP mode, the displays show the contents of the data bus.
C. The 4 optional HEX displays show the contents of the address bus.

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4. OPERATION WITHOUT THE ROM MONITOR
A. Loading programs is done in the LOAD mode. If you have purchased
the address display option, the address just loaded will be displayed
along with the address contents. All loading must start at location 00
HEX.
(1) To load a program
a. Push RESET R key.
b. Push LOAD L key.
c. Push the 2 HEX keypad keys corresponding to the
contents or address 00 HEX.
d. Push the INPUT I switch.
e. The contents of address 00 HEX will be displayed by
the data displays.
f. Push the 2 HEX keypad keys corresponding to the
contents of the next address.
g. Push the INPUT I switch.
h. The contents of tat address will be displayed.
l. Repeat steps f and g until the entire program is
loaded.
(2) To make corrections.
a. Push RESET R key.
b. Push LOAD L key.
c. Push Memory Protect P key.
d. Push the INPUT I key until the preceding location is
reached.
e. Load the HEX keypad with the corrected data word.
f. Push the WAIT W key to enable memory writing.
g. Push the INPUT I key to load the correction data
word.
(3) To run programs.
a. Push the RESET R key.
b. Push the RUN G key. The program will start
executing at address 00 HEX.

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5. OPERATION WITH THE ROM MONITOR
The SUPER ELF monitor allows us to do three things.
A. Loading a program starting at any location.
B. Examine any location in memory (including the monitor itself).
C. Starting a program at any location.
NOTE: This monitor only works with PAGE ZERO (the first 256 words
of memory).
A. To use the monitor to load a program.
(1) Push RESET R key.
(2) Push HEX keys 0 and 2 in that order.
(3) Push the MONITOR M select key.
(4) Push the RUN G key and the data display will indicate 02.
(5) Push the two HEX keypad keys corresponding to the
starting address.
(6) Push the INPUT I key and the Q light will come on
indicating that memory writing is enabled.
(7) Push the two HEX keypad keys corresponding to the data
going into the memory.
(8) Push the INPUT I key and the data displays will display
the memory data just entered.
(9) Repeat steps 7 and 8 for the remainder of the program.
(10) Push the Reset R key when completed.
B. To use the monitor to read out memory contents.
(1) Push the RESET R key.
(2) Push HEX keypad keys 0 and 1 in that order.
(3) Push HEX Monitor M select key.
(4) Push the RUN G key and the data display will indicate 01.
(5) Push the two HEX keypad keys corresponding to the
starting address.
(6) Push the INPUT I key.
(7) Push the INPUT I key again and the data display will
indicate the contents of the specified memory location.

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(8) Continue to push the INPUT I key to step through the
memory contents one at a time.
(9) Push the RESET R key when completed.
NOTE: The contents of the monitor may be read out by using memory
location 00 in step 5.
C. To use the monitor to start execution of a program at any
location.
(1) Push the RESET R key.
(2) Push the HEX keypad key 0 twice.
(3) Push the Monitor M select key.
(4) Push the RUN G key and the data display will indicate 00.
(5) Push the two HEX keypad keys corresponding to the
starting address.
(6) Push the INPUT I key and the program will start
executing.
6. USING SINGLE STEP/SLOW STEP
The SUPER ELF has the ability to step through programs one
machine cycle at a time. Execution is halted at the negative edge of the TPA
signal in each machine cycle. At this point the CPU is in the process of
executing the current instruction cycle. The instruction set timing diagrams
in APPENDIX B should be consulted to determine the hardware state
corresponding' to the instruction being executed.
The single step/slow step mode may be entered from the RESET state
or the WAIT state by pushing the Single Step S key. Pro- gram execution
may then be started or resumed by pushing the RUN G key. A single push of
the RUN G key will advance the program one machine cycle. Holding the
RUN G key down will advance the program at a rate or approximately 1 to 2
machine cycles per second. Re- leasing the RUN G key will stop execution.
Pushing the WAIT W key disables the single step mode and then pushing
the RUN\ G key resumes normal speed operation.

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III LOGIC DESIGN DESCRIPTION
1. HEXADECIMAL KEYBOARD (Figure 1)
The 16 push buttons of the HEX keypad are encoded into one HEX
character using a CMOS 20 key encoder, 74C923. The keys are arranged in
a 4x4 matrix. The encoder uses scanning to determine which key is
depressed. The scanning frequency is determined by C7 and is nominally
600 cps. The switch debounce is internally eliminated, with the debounce
period set by C9 to nominally 25ms. When a key is depressed the data
available (DA) line goes high after the debounce period. If a second key is
depressed before the first key is released, releasing the first key will force
the DA line low and then, after the debounce period, DA will go high for the
second key. This is called two-key rollover. The DA line will stay high as
long as the key is depressed. The output data word is retained until the
NEXT key depression causes another DA pulse. The data word does not
change from old to new until AFTER the leading edge of the DA pulse. This
feature allows storing the old data word using the DA pulse to latch a special
zero input delay latch. This latch, a 74C175, uses the next DA pulse to store
the previous data word. This approach allows the generation of an 8-bit data
word using the last two HEX keys depressed. The last key depressed is the
least significant HEX character of the 2 HEX character word. To the user,
sequential HEX key depressions are shifted to the left with the last two
retained as the input word. The resulting 8-bit word is gated on to the bi-
directional data bus by special CMOS devices called bilateral switches. Two
4016 I/C's are used each containing 4 switches. Each switch behaves as a
very high resistance when off and as a 300 ohm resistor when on. The
ON/OFF control is isolated from the "contacts". The switches are wired as
one 8-pole single throw switch. The keyboard input signal, KBIN, gates the
data word onto the data bus. This results from the execution of the I/O port
input command 6C or pushing the input key during the load mode.

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Hexadecimal Keyboard
Figure 1

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2. CONTROL CIRCUITS G R S W (Figure 2)
The 'G' button is the RUN control. The letter R was used for RESET
and G was chosen as an indication of GO or RUN, Depressing the button
causes the state of the Schmidt trigger NAND gate (U21) to change. The
output goes low and is converted to a high using U5 as an inverter. The D
flip flop (U12) is set by this high causing the not Q output to go low. This
low signal is NORed with the load flip flop output (Figure 3) to pull the
clear line down and cause the CPU to enter the run state (from the reset
state). The above U5 high output resets the wait flip flop U16 (if it was set)
and allows entering the run state from the wait state.
The 'W' button is the wait control. Depressing the button causes the
state of the Schmidt trigger NAND gate (U21) to change. The output goes
high and sets the D flip flop (U16). The Q output of U|16 is ORed with the
single step logic and NANDed with the load FF (U9) to control the wait line.
With a high output of U16 the wait line (U6 P2) is pulled low causing the
CPU to enter the wait state from the run state. The 'W' button also resets the
memory protect (Figure 3) flip flop. The 'W' button can be used to rest
memory protect during loading as an aid in correcting loading errors.
The 'S' button is the single step/slow step control.
Depressing the button sets the D flip flop (U16), and the not Q output goes
low. This is the single step stop request signal.
The two flip flops in U8 are set and reset by the TPA and TPB timing pulses.
The not Q output is low between TPA and TPB. This low is enabled by the
single step flip flop output, and steps the CPU by causing it to enter the wait
state. When in the wait state, timing pulses TPA and TPB are suppressed and
thus TPB cannot reset U8's output. Pushing the 'G' button causes U8 to
receive the equivalent of a TPB pulse and the CPU returns to the run state.
The next machine cycle will output a TPA pulse and if the single step mode
is selected, the CPU will again enter the wait state.
In this manner it is possible to step thru a program one machine cycle at a
time. The stopping point is just after the negative edge of TPA which is in
the middle of execution of an instruction.

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Control Circuit G R S W
Figure 2

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The timing diagrams in the appendix should be consulted to determine
specifically where the instruction execution has stopped. Note that there are
at least two and sometimes three machine cycles per instruction. The 'G'
button Schmidt trigger has a gated oscillator built into it which provides the
slow step feature. When the button is pushed and held, the oscillator is
enabled and starts outputting pulses (equivalent to TPB) at approximately
two per second, the same feature could be accomplished simply by
repetitively pushing the button. The initial delay for the first pulse is caused
by the time it takes to charge C6 up to the Schmidt trigger operating point.
The 'R' button is the reset button. Depressing the button causes the
state of the Schmidt trigger to change putting a high on the reset line. All
other functions are reset by this control.
3. CONTROL CIRCUITS M P I L (Figure 3)
The 'M' button is the ROM monitor select control. Depressing the
button causes the D flip flop (U12) to be set. The not Q output goes low and
this signal is used to select the ROM when the first 32 locations are
addressed. (see figure 4)
The 'P' button is the memory protect control. Depressing the button
causes the D flip flop (U10) to be set. The Q output is ORed with the CPU
MWR signal. When in the Protect mode, the MWR signal is blocked and
memory write is inhibited.
The 'L' button is the load mode select control. Depressing the button
causes the D flip flop (U10) to be set. The Q output is NORed with the clear
and wait CPU controls forcing them low and putting the CPU in the wait
state. The 'I' button is the input control. Depressing the button causes the
state of the Schmidt trigger (U21) to change to low.
This pulls the EF4 CPU sense line low. This signal can be used by a
program to detect that input data is available. Also the D flip flop (U7) is
clocked causing the DMAIN signal to go low. This signal is used by the
CPU in the 'built in' load mode to load data into memory.

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Control Circuit M P I L
Figure 3

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4. DISPLAY CONTROL (Figure 4)
This circuit logically decides when to enable the input latches of the
display drivers. TPB and MRD along with either load of N2 are ANDed
together to detect the execution of an output instruction and enable the
displays. One additional logic element has been added to switch the displays
from an output display to a data bus display. When the single step mode is
selected this signal is gated with the display select signal forcing the displays
onto the data bus a11 the time.
The same figure also shows the logic for enabling the input data word.
In this case either LOAD or N2 and MRD cause the input to be selected.
5. ROM/RAM SELECT (Figure 4)
The ROM is selected only during memory read cycles of the first 32
locations in memory when in the ROM mode. Address lines A5, A6, and A7
are all zero for the first 32 locations These signals are ANDed with the ROM
select signal and the result is ANDed with MRD to enable the ROM during
memory reads of the first 32 locations.
If the ROM is not selected than the RAM must be selected. This signal is
used with either MW or MRD to enable the RAM for a memory read or
write. The dotted lines show the V1.0 wiring. In this version, the ROM is
selected during either a write or read operation.
Therefore any attempt to write into the first 32 locations will cause a
momentary data bus conflict. This is not harmful in this application but the
design was changed to eliminate this conflict in the V2.0 boards. The
inverter used is spare on the V1.0 boards and so this change could be made
if desired by trace cutting and jumpers.

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ROM/RAM Select Display Control
Figure 4

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6. RAM/ROM MEMORY (Figure 5)
The RAM consists of two 2101 MOS memories organized as 256
words of 4 bits. Their address lines are in parallel to result in a memory
organized as 256x8. The ROM is a TTL fusible link PROM organized as
32x8. Its output data lines are Tri-State so that they are not connected to the
data bus unless the ROM is selected (Figure 4). The RAM control is more
complex. In addition to the RAM select signal (Figure 4) The output is
enabled by MRD and read / write control is by MW. There is an additional
RAM select signal which is active high and normally held up by R18. In the
memory saver option this line is lowered to disable the RAM prior to power
down to prevent random write pulses during up or down.
Note that the address and data lines are not connected in accordance with the
manufacturers convention for A0, A1---A7, D0----D7. This is done for
convenience of circuit board layout and causes no problem in operation.
7. STATE/MODE DISPLAY (Figure 6)
The STATE and MODE displays are similar and decode the two input
lines into the corresponding LED driver.
MODE CLEAR WAIT
LOAD LOW LOW
RESET LOW HIGH
RUN HIGH HIGH
WAIT HIGH LOW
STATE SC1 SC0
S0 (Fetch) LOW LOW
S1 (Execute) LOW HIGH
S2 (DMA) HIGH LOW
S3 (INT) HIGH HIGH
The two input lines are inverted and the normal and inverted signals
are input to the AND gates. Only one and gate is true at a time. This output
is inverted in the corresponding 4049 driver and provides a current limited
sink or approximately

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RAM/ROM Memory
Figure 5