Rabbit 2000 User manual

Rabbit 2000/3000Microprocessor
Instruction Reference Manual
019–0098 F • 040114
This manual (or an even more up-to-date revision) is available for free download
at the Rabbit website: www.rabbitsemiconductor.com

ii Rabbit 2000/3000 Microprocessor

Instruction Reference Manual iii
Table of Contents
1. AlphabeticalListingofInstructions.......................................1
2. InstructionsListedbyGroup ...........................................3
3. DocumentConventions ...............................................7
4. ProcessorRegisters.................................................11
5. OpCodeDescriptions................................................13
6. OpcodeMap......................................................153
7. QuickReferenceTable..............................................161
NoticetoUsers ......................................................169

iv Rabbit 2000 Microprocessor

Instruction Reference Manual 1
1. Alphabetical Listing of Instructions
A
ADC A,n ..............................14
ADC A,r ..............................15
ADC A,(HL) .........................13
ADC A,(IX+d) ......................13
ADC A,(IY+d) ......................13
ADC HL,ss ...........................16
ADD A,n ..............................18
ADD A,r ..............................19
ADD A,(HL) .........................17
ADD A,(IX+d) ......................17
ADD A,(IY+d) ......................17
ADD HL,ss ...........................20
ADD IX,xx ...........................21
ADD IY,yy ...........................21
ADD SP,d ............................22
ALTD ..................................23
AND HL,DE .........................25
AND IX,DE ..........................25
AND IY,DE ..........................25
AND n .................................26
AND r .................................27
AND (HL) ............................24
AND (IX+d) .........................24
AND (IY+d) .........................24
B
BIT b,r .................................29
BIT b,(HL) ...........................28
BIT b,(IX+d) .........................28
BIT b,(IY+d) .........................28
BOOL HL ............................30
BOOL IX .............................31
BOOL IY .............................31
C
CALL mn .............................32
CCF ....................................33
CP n ....................................35
CP r .....................................36
CP (HL) ...............................34
CP (IX+d) ............................34
CP (IY+d) ............................34
CPL .....................................37
D
DEC IX ................................39
DEC IY ................................39
DEC r ..................................40
DEC ss .................................41
DEC (HL) ............................38
DEC (IX+d) ..........................38
DEC (IY+d) ..........................38
DJNZ e ................................42
E
EX AF,AF' ...........................45
EX DE',HL ...........................46
EX DE,HL ............................46
EX (SP),HL ..........................43
EX (SP),IX ...........................44
EX (SP),IY ...........................44
EXX ....................................47
I
IDET ...................................48
INC IX .................................50
INC IY .................................50
INC r ...................................51
INC ss .................................52
INC (HL) .............................49
INC (IX+d) ...........................49
INC (IY+d) ...........................49
IOE .....................................53
IOI ......................................53
IPRES ..................................55
IPSET 0 ...............................54
IPSET 1 ...............................54
IPSET 2 ...............................54
IPSET 3 ...............................54
J
JP f,mn ................................57
JP mn ..................................56
JP (HL) ................................56
JP (IX) .................................56
JP (IY) .................................56
JR cc,e .................................58
JR e .....................................59
L
LCALL x,mn ........................60
LD A,EIR .............................68
LD A,IIR ..............................68
LD A,XPC ............................69
LD A,(BC) ...........................67
LD A,(DE) ...........................67
LD A,(mn) ............................67
LD dd',BC ............................71
LD dd',DE ............................71
LD dd,mn .............................72
LD dd,(mn) ...........................70
LD EIR,A .............................73
LD HL,IX .............................76
LD HL,IY .............................76
LD HL,(HL+d) ......................74
LD HL,(IX+d) .......................74
LD HL,(IY+d) .......................74
LD HL,(mn) ..........................74
LD HL,(SP+n) .......................75
LD IIR,A ..............................73
LD IX,HL .............................79
LD IX,mn .............................79
LD IX,(mn) ..........................77
LD IX,(SP+n) .......................78
LD IY,HL .............................79
LD IY,mn .............................79
LD IY,(mn) ..........................80
LD IY,(SP+n) .......................81
LD r,g ..................................84
LD r,n ..................................83
LD r,(HL) .............................82
LD r,(IX+d) ..........................82
LD r,(IY+d) ..........................82
LD SP,HL ............................85
LD SP,IX .............................85
LD SP,IY .............................85
LD XPC,A ............................86
LD (BC),A ...........................61
LD (DE),A ...........................61
LD (HL),n ............................61
LD (HL),r .............................61
LD (HL+d),HL ......................62
LD (IX+d),HL .......................63
LD (IX+d),n ..........................63
LD (IX+d),r ..........................63
LD (IY+d),HL .......................64

2Rabbit 2000/3000 Microprocessor
LD (IY+d),n ..........................64
LD (IY+d),r ..........................64
LD (mn),A ............................65
LD (mn),HL ..........................65
LD (mn),IX ...........................65
LD (mn),IY ...........................65
LD (mn),ss ...........................65
LD (SP+n),HL .......................66
LD (SP+n),IX ........................66
LD (SP+n),IY ........................66
LDD ....................................87
LDDR ..................................87
LDDSR ................................88
LDI .....................................87
LDIR ...................................87
LDISR .................................88
LDP HL,(HL) ........................91
LDP HL,(IX) .........................91
LDP HL,(IY) .........................91
LDP HL,(mn) ........................92
LDP IX,(mn) .........................92
LDP IY,(mn) .........................92
LDP (HL),HL ........................89
LDP (IX),HL .........................89
LDP (IY),HL .........................89
LDP (mn),HL ........................90
LDP (mn),IX .........................90
LDP (mn),IY .........................90
LJP x,mn ..............................93
LRET ..................................94
LSDDR ................................95
LSDR ..................................95
LSIDR .................................95
LSIR ...................................95
M
MUL ...................................96
N
NEG ....................................97
NOP ....................................98
O
OR HL,DE .........................100
OR IX,DE ..........................101
OR IY,DE ..........................101
OR n ..................................102
OR r ..................................102
OR (HL) ...............................99
OR (IX+d) ............................99
OR (IY+d) ............................99
P
POP IP ...............................103
POP IX ..............................103
POP IY ..............................103
POP SU .............................104
POP zz ...............................105
PUSH IP ............................106
PUSH IX ............................106
PUSH IY ............................106
PUSH SU ...........................107
PUSH zz ............................108
R
RA ....................................126
RDMODE ..........................109
RES b,r ..............................111
RES b,(HL) .........................110
RES b,(IX+d) ......................110
RES b,(IY+d) ......................110
RET ..................................112
RET f ................................113
RETI .................................114
RL DE ...............................116
RL r ..................................117
RL (HL) .............................115
RL (IX+d) ..........................115
RL (IY+d) ..........................115
RLA ..................................118
RLC r ................................120
RLC (HL) ...........................119
RLC (IX+d) ........................119
RLC (IY+d) ........................119
RLCA ................................121
RR DE ...............................123
RR HL ...............................123
RR IX ................................124
RR IY ................................124
RR r ..................................125
RR (HL) .............................122
RR (IX+d) ..........................122
RR (IY+d) ..........................122
RRC r ................................128
RRC (HL) ..........................127
RRC (IX+d) ........................127
RRC (IY+d) ........................127
RRCA ................................129
RST v ................................130
S
SBC A,n .............................132
SBC A,r .............................132
SBC A,(HL) ........................131
SBC HL,ss ..........................133
SBC (IX+d) ........................131
SBC (IY+d) ........................131
SCF ...................................134
SET b,r ..............................136
SET b,(HL) .........................135
SET b,(IX+d) ......................135
SET b,(IY+d) ......................135
SETUSR ............................137
SLA r ................................139
SLA (HL) ...........................138
SLA (IX+d) ........................138
SLA (IY+d) ........................138
SRA r ................................141
SRA (HL) ...........................140
SRA (IX+d) ........................140
SRA (IY+d) ........................140
SRL r .................................143
SRL (HL) ...........................142
SRL (IX+d) ........................142
SRL (IY+d) ........................142
SUB n ................................145
SUB r ................................146
SUB (HL) ...........................144
SUB (IX+d) ........................144
SUB (IY+d) ........................144
SURES ..............................147
SYSCALL ..........................148
U
UMA .................................149
UMS .................................149
X
XOR n ...............................151
XOR r ................................152
XOR (HL) ..........................150
XOR (IX+d) .......................150
XOR (IY+d) .......................150

Instruction Reference Manual 3
2. Instructions Listed by Group
A. Load Immediate Data
LD dd,mn ...............................72
LD IX,mn ................................79
LD IY,mn ................................79
LD r,n ...................................83
B. Load and Store to an Immediate Address
LD (mn),A ...............................65
LD (mn),HL ..............................65
LD (mn),IX ..............................65
LD (mn),IY ..............................65
LD (mn),ss ..............................65
LD A,(mn) ...............................67
LD dd,(mn) ..............................70
LD HL,(mn) ..............................74
LD IX,(mn) ..............................77
LD IY,(mn) ..............................80
C. 8-bit Indexed Load and Store
LD (BC),A ...............................61
LD (DE),A ...............................61
LD (HL),n ...............................61
LD (HL),r ................................61
LD (IX+d),n ..............................63
LD (IX+d),r ..............................63
LD (IY+d),n ..............................64
LD (IY+d),r ..............................64
LD A,(BC) ...............................67
LD A,(DE) ...............................67
LD r,(HL) ................................82
LD r,(IX+d) ..............................82
LD r,(IY+d) ..............................82
D. 16-bit Indexed Load and Store
LD (HL+d),HL ............................62
LD (IX+d),HL ............................63
LD (IY+d),HL ............................64
LD (SP+n),HL ............................66
LD (SP+n),IX ............................66
LD (SP+n),IY ............................66
LD HL,(HL+d) ............................74
LD HL,(IX+d) ............................74
LD HL,(IY+d) ............................74
LD HL,(SP+n) ............................75
LD IX,(SP+n) .............................78
LD IY,(SP+n) .............................81
E. 16-bit Load and Store to 20-bit Address
LDP (HL),HL .............................89
LDP (IX),HL ..............................89
LDP (IY),HL ..............................89
LDP (mn),HL .............................90
LDP (mn),IX .............................90
LDP (mn),IY .............................90
LDP HL,(HL) .............................91
LDP HL,(IX) ..............................91
LDP HL,(IY) ..............................91
LDP HL,(mn) .............................92
LDP IX,(mn) .............................92
LDP IY,(mn) .............................92
F. Register to Register Moves
LD A,EIR ................................68
LD A,IIR .................................68
LD A,XPC ...............................69
LD dd’,BC ...............................71
LD dd’,DE ...............................71
LD EIR,A ................................73
LD HL,IX ................................76
LD HL,IY ................................76
LD IIR,A .................................73
LD IX,HL ................................79
LD IY,HL ................................79
LD r,g ...................................84
LD SP,HL ................................85
LD SP,IX ................................85
LD SP,IY ................................85
LD XPC,A ...............................86
G. Exchange
EX (SP),HL ..............................43
EX (SP),IX ...............................44
EX (SP),IY ...............................44
EX AF,AF’ ...............................45
EX DE,HL ...............................46
EX DE’,HL ...............................46

4 Rabbit 2000/3000 Microprocessor
EXX ....................................47
H. Stack Manipulation
ADD SP,d ...............................22
POP IP .................................103
POP IX .................................103
POP IY .................................103
POP zz ................................105
PUSH IP ...............................106
PUSH IX ...............................106
PUSH IY ...............................106
PUSH zz ...............................108
I. 16-bit Arithmetic, Logical, and Rotate
ADC HL,ss ..............................16
ADD HL,ss ..............................20
ADD IX,xx ...............................21
ADD IY,yy ...............................21
ADD SP,d ...............................22
AND HL,DE ..............................25
BOOL HL ................................30
BOOL IX ................................31
BOOL IY ................................31
DEC IX ..................................39
DEC IY ..................................39
DEC ss .................................41
INC IX ..................................50
INC IY ..................................50
INC ss ..................................52
MUL ....................................96
NEG ....................................97
OR HL,DE ..............................100
OR IX,DE ..............................101
OR IY,DE ..............................101
RL DE .................................116
RR DE .................................123
RR HL .................................123
RR IX ..................................124
RR IY ..................................124
SBC HL,ss .............................133
I.16-bit Arithmetic, Logical, and Rotate
AND HL,DE ..............................25
AND IX,DE ..............................25
AND IY,DE ..............................25
J. 8-bit Arithmetic and Logical
ADC A,(HL) ........................13
ADC A,(IX+d) .......................13
ADC A,(IY+d) .......................13
ADC A,n ................................ 14
ADC A,r ................................ 15
ADD A,(HL) ............................. 17
ADD A,(IX+d) ........................... 17
ADD A,(IY+d) ........................... 17
ADD A,n ................................ 18
ADD A,r ................................ 19
AND (HL) ............................... 24
AND (IX+d) ............................. 24
AND (IY+d) ............................. 24
AND r .................................. 27
CP (HL) ................................ 34
CP (IX+d) ............................... 34
CP (IY+d) ............................... 34
CP n ................................... 35
CP r .................................... 36
NEG ................................... 97
OR (HL) ................................ 99
OR (IX+d) ............................... 99
OR (IY+d) ............................... 99
OR n .................................. 102
OR r .................................. 102
SBC (IX+d) ............................ 131
SBC (IY+d) ............................ 131
SBC A,(HL) ............................ 131
SBC A,n ............................... 132
SBC A,r ............................... 132
SUB (HL) .............................. 144
SUB (IX+d) ............................ 144
SUB (IY+d) ............................ 144
SUB n ................................. 145
SUB r ................................. 146
XOR (HL) .............................. 150
XOR (IX+d) ............................ 150
XOR (IY+d) ............................ 150
XOR n ................................. 151
XOR r ................................. 152
K. 8-bit Bit Set, Reset, and Test
BIT b,(HL) .............................. 28
BIT b,(IX+d) ............................. 28
BIT b,(IY+d) ............................. 28

Instruction Reference Manual 5
BIT b,r ..................................29
RES b,(HL) .............................110
RES b,(IX+d) ...........................110
RES b,(IY+d) ...........................110
RES b,r ................................111
SET b,(HL) .............................135
SET b,(IX+d) ...........................135
SET b,(IY+d) ...........................135
SET b,r ................................136
L. 8-bit Increment and Decrement
DEC (HL) ...............................38
DEC (IX+d) ..............................38
DEC (IY+d) ..............................38
DEC r ...................................40
INC (HL) ................................49
INC (IX+d) ...............................49
INC (IY+d) ...............................49
INC r ...................................51
M. 8-bit Fast Accumulator
CPL ....................................37
RLA ...................................118
RLCA ..................................121
RRA ...................................126
RRCA .................................129
N. 8-bit Shift and Rotate
RL (HL) ................................115
RL (IX+d) ..............................115
RL (IY+d) ..............................115
RLC (HL) ...............................119
RLC (IX+d) .............................119
RLC (IY+d) .............................119
RLC r ..................................120
RR (HL) ................................122
RR (IX+d) ..............................122
RR (IY+d) ..............................122
RR r ...................................125
RRC (HL) ..............................127
RRC (IX+d) .............................127
RRC (IY+d) .............................127
RRC r ..................................128
SLA (HL) ...............................138
SLA (IX+d) .............................138
SLA (IY+d) .............................138
SLA r ..................................139
SRA (HL) ...............................140
SRA (IX+d) .............................140
SRA (IY+d) .............................140
SRA r ..................................141
SRL (HL) ...............................142
SRL (IX+d) .............................142
SRL (IY+d) .............................142
SRL r ..................................143
O. Instruction Prefixes
ALTD ...................................23
IOE .....................................53
IOI ......................................53
P. Block Moves
LDD ....................................87
LDDR ...................................87
LDDSR ..................................88
LDI .....................................87
LDIR ....................................87
LDISR ...................................88
LSDDR ..................................95
LSDR ...................................95
LSIDR ...................................95
LSIR ....................................95
Q. Control, Jump, and Call
CALL mn ................................32
DJNZ e ..................................42
JP (HL) ..................................56
JP (IX) ..................................56
JP (IY) ..................................56
JP f,mn ..................................57
JP mn ...................................56
JR cc,e ..................................58
JR e ....................................59
LCALL x,mn .............................60
LJP x,mn ................................93
LRET ...................................94
RET ...................................112
RET f ..................................113
RETI ...................................114
RST v ..................................130

6 Rabbit 2000/3000 Microprocessor
R. Miscellaneous
CCF ....................................33
IPSET 0 .................................54
IPSET 1 .................................54
IPSET 2 .................................54
IPSET 3 .................................54
NOP ....................................98
SCF ...................................134
S. Special Arithmetic
UMA ...................................149
UMS ...................................149
T. Privileged Instructions
BIT b,(HL) ...............................28
IPRES ..................................55
IPSET 0 .................................54
IPSET 1 .................................54
IPSET 2 .................................54
IPSET 3 .................................54
LD A,XPC ...............................69
LD SP,HL ...............................85
LD SP,IX ................................85
LD SP,IY ................................85
LD XPC,A ...............................86
POP IP .................................103
RETI ...................................114
U. Rabbit 3000A Instructions
IDET ....................................48
LDDSR .................................88
LDISR ..................................88
LSDDR .................................95
LSDR ...................................95
LSIDR ..................................95
LSIR ....................................95
POP SU ................................104
PUSH SU ..............................107
RDMODE ..............................109
SETUSR ...............................137
SURES ................................147
SYSCALL ..............................148
UMA ...................................149
UMS ...................................149
W. System/User Mode
IDET ................................... 48
POP SU ............................... 104
PUSH SU .............................. 107
RDMODE .............................. 109
SETUSR ............................... 137
SURES ................................ 147
SYSCALL .............................. 148

Instruction Reference Manual 7
3. Document Conventions
Instruction Table Key
•Opcode: A hexidecimal representation of the value that the mnemonic instruction represents.
•Instruction: The mnemonic syntax of the instruction.
•Clocks: The number of clock cycles it takes to complete this instruction. The numbers in parenthesis
are a breakdown of the total clocks. The number of clocks instructions take follows a general patern.
There are several Rabbit instructions that do not adhere to this pattern. Some instructions take more
clocks and some have been enhanced to take fewer clocks.
Table 1: Typical Clocks Breakdown
•Operation: A symbolic representation of the operation performed.
Process Clocks
Each byte of the opcode. 2
Each data byte read. 2
Write to memory or external IO. 3
Write to internal IO. 2
Internal operation or computation. 1

8 Rabbit 2000/3000 Microprocessor
ALTD, I/O and Flags Table Keys
Table 2: ALTD (“A” Column) Symbol Key
Table 3: IOI and IOE (“I” Column) Symbol Key
Table 4: Flag Register Key
Flag Description
F R SP
•ALTD selects alternate flags
•ALTD selects alternate destination register
•ALTD operation is a special case
Flag Description
SD
•IOI and IOE affect destination
•IOI and IOE affect source
S Z L/V CDescription
•Sign flag affected
-Sign flag not affected
•Zero flag affected
-Zero flag not affected
LLV flag contains logical check result
VLV flag set on arithmetic overflow result
0LV flag is cleared
•LV flag is affected
•Carry flag is affected
-Carry flag is not affected
0Carry flag is cleared
1Carry flag is set

Instruction Reference Manual 9
Document Symbols Key
Table 5: Symbols
Rabbit Z180 Meaning
b b Bit select (000 = bit 0, 001 = bit 1, 010 = bit 2, 011 = bit
3, 100 = bit 4, 101 = bit 5, 110 = bit 6, 111 = bit 7)
cc cc Condition code select (00 = NZ, 01 = Z, 10 = NC, 11 = C)
d d 8-bit signed displacement. Expressed in two’s complement.
dd ww word register select-destination (00 = BC, 01 = DE, 10 =
HL, 11 = SP)
dd' word register select-alternate(00 = BC', 01 = DE', 10 =
HL')
e j 8-bit (signed) displacement added to PC
f f condition code select (000 = NZ, 001 = Z, 010 = NC, 011 = C,
100 = LZ/NV, 101 = LO/V, 110 = P, 111 = M)
m m the most significant bits(MSB) of a 16-bit constant
mn mn 16-bit constant
n n 8-bit constant or the least significant bits(LSB) of a 16-
bit constant
r, g g, g' byte register select (000 = B, 001 = C, 010 = D, 011 = E,
100 = H, 101 = L, 111 = A)
ss ww word register select-source ( 00 = BC, 01 = DE, 10 = HL, 11
= SP)
v v Restart address select ( 010 = 0020h, 011 = 0030h, 100 =
0040h, 101 = 0050h, 111 = 0070h)
xnbr an 8-bit constant to load into the XPC
xx xx word register select ( 00 = BC, 01 = DE, 10 = IX, 11 = SP)
yy yy word register select (00 = BC, 01 = DE, 10 = IY, 11 = SP)
zz zz word register select (00 = BC, 01 = DE, 10 = HL, 11 = AF)

10 Rabbit 2000/3000 Microprocessor
Condition Codes
Table 6: Condition Code Description
Condition Flag=Value Description
NZ Z=0 Not Zero
ZZ=1 Zero
NC C=0 No Carry (C=0)
CC=1 Carry (C=1)
PS=0 Positive
MS=1 Minus
LZ L/V=0 For logic operations, Logic Zero
(all of the four most significant
bits of the result are zero)
NV L/V=0 For arithmentic operations,
No Overflow
LO L/V=1 For logic operations, Logic One
(one or more of the four most signif-
icant bits of the result are one)
VL/V=1 For arithmentic operations,
Overflow

Instruction Reference Manual 11
4. Processor Registers
SZ LV C
Sign Zero
Logical/
Overflow Carry
IX
IY
SP
PC
Index Register
Index Register
Stack Pointer
Program Counter
General Pur ose
External
Interru t
Internal
Interru t
Interru t
Priority
Extension of
Program Counter
EIR
IIR
IP
XPC
Accumulator Flags
H
D
B
A F
L
E
C
16-bit Accumulator
Accumulator Flags
D'
B'
A' F'
E'
C'
H' L'
16-bit Accumulator
Alternate Registers

12 Rabbit 2000/3000 Microprocessor

Instruction Reference Manual 13
5. OpCode Descriptions
Description
ThedatainAissummedwiththeCflagandwiththedatainmemorywhoselocationis:
• heldinHL, or
• the sum of the data in IX and a displacement value d,or
• the sum of the data in IY and a displacement value d.
The result is then stored in A.
ADC A,(HL)
ADC A,(IX+d)
ADC A,(IY+d)
Opcode Instruction Clocks Operation
8E ADC A,(HL) 5 (2,1,2) A=A+(HL)+CF
DD 8E dADC A,(IX+d)9 (2,2,2,1,2) A=A+(IX+d)+CF
FD 8E dADC A,(IY+d)9 (2,2,2,1,2) A=A+(IY+d)+CF
Flags ALTD I/O
S Z L/V C F R SP S D
• • V • • • •

14 Rabbit 2000/3000 Microprocessor
Description
The 8-bit constant nissummedwiththeCflagandwiththedatainA.ThesumisthenstoredinA.
ADC A,n
Opcode Instruction Clocks Operation
CE nADC A,n4 (2,2) A=A+n+CF
Flags ALTD I/O
S Z L/V C F R SP S D
• • V • • •

Instruction Reference Manual 15
Description
ThedatainAissummedwiththeCflagandwiththedatain r(any of the registers A, B, C, D, E, H, or L).
TheresultisstoredinA.
ADC A,r
Opcode Instruction Clocks Operation
—— ADC A,r2A=A+r+CF
8F ADC A,A 2A=A+A+CF
88 ADC A,B 2A=A+B+CF
89 ADC A,C 2A=A+C+CF
8A ADC A,D 2A=A+D+CF
8B ADC A,E 2A=A+E+CF
8C ADC A,H 2A=A+H+CF
8D ADC A,L 2A=A+L+CF
Flags ALTD I/O
S Z L/V C F R SP S D
• • V • • •

16 Rabbit 2000/3000 Microprocessor
Description
ThedatainHLissummedwiththeCflagandwiththedatainss (anyofBC,DE,HL,orSP).Theresultis
stored in HL.
ADC HL,ss
Opcode Instruction Clocks Operation
—— ADC HL,ss 4 (2,2) HL = HL + ss +CF
ED 4A ADC HL,BC 4 (2,2) HL = HL + BC + CF
ED 5A ADC HL,DE 4 (2,2) HL = HL + DE + CF
ED 6A ADC HL,HL 4 (2,2) HL = HL + HL + CF
ED 7A ADC HL,SP 4 (2,2) HL = HL + SP + CF
Flags ALTD I/O
S Z L/V C F R SP S D
• • V • • •