Phytec phyCORE-MPC5676/57 Series User manual

A product of a PHYTEC Technology Holding company
phyCORE®-MPC5676/57xx
Hardware Manual
Document No.: L-807e.A2
SOM Prod. No.: KSP-0180-1 /
KSP-0180-1C1/
KSP-0180-1C2
SOM PCB. No.: 2367.1
CB Prod. No.: KSP-0180-B0
CB PCB. No.: 2373.1
Edition: August 2020

phyCORE
®- MPC5676/57xx [KSP-0180-0]
PHYTEC Messtechnik GmbH 2020 L-807e.A2
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further reserves the right to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
Copyright 2020 PHYTEC Messtechnik GmbH, D-55129 Mainz.
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Preliminary Edition August 2020

Contents
PHYTEC Messtechnik GmbH 2020 L-807e.A2 i
List of Figures..................................................................................................iii
List of Tables ................................................................................................... iv
Conventions, Abbreviations and Acronyms .............................................................. v
Preface ........................................................................................................ viii
1Introduction............................................................................................ 11
1.1 Features of the phyCORE-MPC5676/57x ............................................................11
1.1.1 Internal Features of the MPC5676R.......................................................12
1.2 Memory Configuration of the phyCORE-MPC5676/57xx .......................................12
1.3 Other Board-Level Features............................................................................12
1.4 Block Diagram.............................................................................................13
1.5 phyCORE-MPC5676/57xx Component Placement ................................................14
1.6 Minimum Requirements to operate the phyCORE-MPC5676/57xx ...........................16
1.6.1 phyCORE-MPC5676/57xx without FPGA .................................................16
1.6.2 phyCORE-MPC5676/57xx with FPGA ......................................................16
2Pin Description......................................................................................... 17
3Jumpers ................................................................................................. 34
4Power Requirements.................................................................................. 44
4.1 Voltage Supervisor and Reset .........................................................................45
5System Configuration and Booting................................................................ 46
6System Memory ........................................................................................ 47
6.1 External Standard Flash Memory (U100,U101)...................................................47
6.2 Synchronous Burst SRAM(U102,U103) .............................................................48
6.3 SPI EEPROM (U6) .........................................................................................49
6.3.1 EEPROM Write Protection Control (J30) .................................................49
6.4 SPI Flash Memory (U19) ................................................................................49
7FPGA System Logic Device U18 ..................................................................... 50
7.1 Addressing the FPGA from MPC .......................................................................50
7.2 Configuration of the FPGA..............................................................................50
7.3 FPGA connector X3 .......................................................................................50
8Serial Interfaces....................................................................................... 51
8.1 Universal Asynchronous Interface ...................................................................51
8.2 CAN Interface..............................................................................................52
8.3 SPI Interface...............................................................................................52
9LAN9221I Ethernet Controller...................................................................... 53
9.1 Ethernet Transformer....................................................................................53
9.2 Addressing the Ethernet Controller..................................................................54
9.2.1 Software Reset of the Ethernet Controller ..............................................54
9.3 MAC Address ...............................................................................................54
10 Real-Time Clock M41T93 (U7) ...................................................................... 55
11 JTAG/OnCE/Nexus Debufg Interface .............................................................. 56
12 Technical Specifications ............................................................................. 57
13 Hints for Integrating and Handling the phyCORE-MPC5676/57xx ......................... 60
13.1 Integrating the phyCORE-MPC5676/57xx..........................................................60
13.2 Handling the phyCORE-MPC5676/57xx.............................................................60
14 The phyCORE- MPC5676R on the phyCORE Carrier Board ..................................... 61

phyCORE
®- MPC5676/57xx [KSP-0180-0]
ii PHYTEC Messtechnik GmbH 2020 L-807e.A2
14.1 Concept of the phyCORE Carrier Board ............................................................. 61
14.2 Overview of the phyCORE Carrier Board Peripherals ............................................ 62
14.2.1 Connectors and Pin Header ................................................................ 63
14.2.2 Switches ........................................................................................ 64
14.2.3 LEDs.............................................................................................. 64
14.2.4 Analog Input Potentiometer............................................................... 65
14.2.5 Jumpers......................................................................................... 65
14.3 Functional Components on the phyCORE Carrier Board........................................ 68
14.3.1 phyCORE- MPC5676R SOM Connectivity (X1, X2, X3) ............................... 68
14.3.2 Power (X8, X9) ................................................................................ 69
14.3.2.1 Wall Adapter Input (X8)........................................................ 70
14.3.3 First Serial Interface at Socket P2A ..................................................... 71
14.3.4 Second Serial Interface at Socket P2B .................................................. 71
14.3.5 First CAN Interface at Plug P1A ........................................................... 72
14.3.6 Second CAN Interface at Plug P1B........................................................ 72
14.3.7 Ethernet Connectivity (X28) ............................................................... 73
14.3.8 User programmable LEDs................................................................... 73
14.3.9 Boot Mode Selection (BOOTCFG1)........................................................ 74
14.3.10 System Reset Button (RESET1)............................................................ 75
14.3.11 FPGA_JTAG Connector....................................................................... 76
14.3.12 JTAG/Once/Nexus Debug Interface...................................................... 76
14.3.13 Reduced JTAG/OnCE/NEXUS Pin Header Connector X ............................... 76
14.3.14 Full JTAG/OnCE/NEXUS Pin Header Connector X10 .................................. 77
14.3.15 phyCORE-MPC5676/57xx Expansion Connector...................................... 78
14.3.16 Schematic of Carrier Board KSP-0180-Bx .............................................. 79
15 Revision History ........................................................................................84
Index ............................................................................................................85

Contents
PHYTEC Messtechnik GmbH 2020 L-807e.A2 iii
List of Figures
Figure 1: Block Diagram of the phyCORE-MPC5676/57xx.................................................13
Figure 2: phyCORE-MPC5676/57xx Component Placement (top view) ................................14
Figure 3: phyCORE-MPC5676/57xx Component Placement (top view) ................................15
Figure 4: Pinout of the phyCORE-Connector (top view) ...................................................18
Figure 5: Typical Jumper Pad Numbering Scheme ..........................................................34
Figure 6: Jumper Locations (top view) ........................................................................35
Figure 8: Physical Dimensions (top view).....................................................................57
Figure 9: phyCORE Carrier Board Overview of Connectors, LEDs and Buttons (top view) .........62
Figure 10: Typical Jumper Numbering Scheme................................................................65
Figure 11: phyCORE Carrier Board Jumper Locations (top view) .........................................66
Figure 12: phyCORE- MPC5676R SOM Connectivity to the Carrier Board................................68
Figure 13: Powering Scheme.......................................................................................69
Figure 14: Power Connector corresponding to Wall Adapter Input X12.................................70
Figure 15: Pin Assignment of P2A as First RS-232 (Front View)...........................................71
Figure 16: Pin Assignment of P2B as Second RS-232 (Front View).......................................71
Figure 17: Pin Assignment of the DB-9 Plug P1A (CAN Transceiver on carrier Board, Front View)72
Figure 18: Pin Assignment of the DB-9 Plug P1B (CAN Transceiver on carrier Board, Front View).72
Figure 19: Expansion Connector location on the Development Board KSP-0150-B0................78
Figure 20: page 2/5 of KSP-0150-B0 schematic ..............................................................80
Figure 21: page 3/5 of KSP-0150-B0 schematic ..............................................................81
Figure 22: page 4/5 of KSP-0150-B0 schematic ..............................................................82
Figure 23: page 5/5 of KSP-0150-B0 schematic ..............................................................83

phyCORE
®- MPC5676/57xx [KSP-0180-0]
iv PHYTEC Messtechnik GmbH 2020 L-807e.A2
List of Tables
Table 1: Signal Types used in this Manual ................................................................... vi
Table 2: Abbreviations and Acronyms used in this Manual..............................................vii
Table 3: Pinout of the phyCORE-Connector X1, Row A ................................................... 19
Table 4: Pinout of the phyCORE-Connector X1, Row B ................................................... 21
Table 5: Pinout of the phyCORE-Connector X2, Row A ................................................... 24
Table 6: Pinout of the phyCORE-Connector X2, Row B ................................................... 26
Table 7: Pinout of the FPGA Connector X3, Row A ........................................................ 29
Table 8: Pinout of the FPGA Connector X3, Row B ........................................................ 31
Table 9: Jumper Settings ....................................................................................... 37
Table 10: Boot Modes of the phyCORE-MPC5676/57xx ................................................... 46
Table 11: Choice of Standard Flash Memory Devices and Manufacturers ............................. 47
Table 12: Memory Options for the Synchronous Burst SRAM ............................................ 48
Table 13: EEPROM write protection states via J30 and GPIO463........................................ 49
Table 14: Location of the UART Signals ....................................................................... 51
Table 15: Location of the UART Signals ....................................................................... 52
Table 16: Location of the Ethernet Signals .................................................................. 54
Table 17: 14-Pin JTAG/OnCE Connector (X8) and Corresponding Pins on the phyCORE-
Connector (X2) ......................................................................................... 56
Table 18: phyCORE Carrier Board Connectors and Pin Headers ......................................... 63
Table 19: phyCORE Carrier Board Push Buttons Descriptions............................................ 64
Table 20: phyCORE Carrier Board LEDs Descriptions ....................................................... 64
Table 21: phyCORE Carrier Board Jumper Descriptions ................................................... 67
Table 22: User Programmable LEDs on the Carrier Board................................................. 73
Table 23: phyCORE Carrier Board DIP Switch S3 Descriptions ........................................... 74
Table 24: Pin Assignment of the JTAG_FPGA connector X6 .............................................. 76
Table 25: Pin Assignment of the Reduced JTAG/OnCE/Nexus Pin Header X7........................ 76
Table 26: Pin Assignment of the Full JTAG/OnCE/Nexus Pin Header X10............................. 77

Conventions, Abbreviations and Acronyms
PHYTEC Messtechnik GmbH 2020 L-807e.A2 v
Conventions, Abbreviations and Acronyms
This hardware manual describes the KSP-0180-0 System on Module, in the following
referred to as phyCORE®-MPC5676/57xx. The manual specifies the
phyCORE®-MPC5676/57x's design and function. Precise specifications for the Freescale
Semiconductor MPC5676R microcontrollers can be found in the enclosed microcontroller
Data Sheet/User's Manual.
Note: We refrain from providing detailed part specific information within this manual,
which can be subject to continuous changes, due to part maintenance for our products.
Please read the paragraph "Product Change Management and information in this
manual on parts populated on the SOM" within the Preface.
Conventions
The conventions used in this manual are as follows:
Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), or
that have a dash on top of the signal name (e.g.: RD) are designated as active low
signals. That is, their active state is when they are driven low, or are driving low.
A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or
high-level signal.
The MSB and LSB of the data and address busses shown in the circuit diagram are
based on the conventions of Freescale. Accordingly, D31 and A31 represent the LSB,
while D0 and A0 represent the MSB.
These conventions are also valid for the parallel I/O signals.
Tables which describe jumper settings show the default position in bold, blue text.
Text in blue italic indicates a hyperlink within, or external to the document. Click these
links to quickly jump to the applicable URL, part, chapter, table, or figure.
References made to the phyCORE-Connector always refer to the high density Samtec
connector on the undersides of the phyCORE-MPC5676/57xx System on Module.

phyCORE
®- MPC5676/57xx [KSP-0180-0]
vi PHYTEC Messtechnik GmbH 2020 L-807e.A2
Types of Signals
Different types of signals are brought out at the phyCORE-Connector. The following table
lists the abbreviations used to specify the type of a signal.
Signal Type
Description
Abbr.
Power
Supply voltage input
PWR_I
Ref-Voltage
Reference voltage output
REF_O
Input
Digital input
I
Output
Digital output
O
IO
Bidirectional input/output
I/O
IPU
Digital input with pull-up, must only be connected to GND.
(jumper or open-collector output)
IPU
OC-Bidir PU
Open collector input/output with pull up
OC-BI
OC-Output
Open collector output without pull up, requires an external
pull up
OC
5V Input PD
5 V tolerant input with pull down
5V_PD
ETHERNET
Input
Differential line pairs 100 Ohm Ethernet level input
ETH_I
ETHERNET
Output
Differential line pairs 100 Ohm Ethernet level output
ETH_O
Table 1: Signal Types used in this Manual

Conventions, Abbreviations and Acronyms
PHYTEC Messtechnik GmbH 2020 L-807e.A2 vii
Abbreviations and Acronyms
Many acronyms and abbreviations are used throughout this manual. Use the table below to
navigate unfamiliar terms used in this document.
Abbreviation
Definition
CB
Carrier Board; used in reference to the phyCORE Development Kit Carrier
Board.
DFF
D flip-flop.
EMB
External memory bus.
EMI
Electromagnetic Interference.
GPI
General purpose input.
GPIO
General purpose input and output.
GPO
General purpose output.
IRAM
Internal RAM; the internal static RAM on the Freescale Semiconductor
MPC5676R microcontroller.
J
Solder jumper; these types of jumpers require solder equipment to
remove and place.
JP
Solderless jumper; these types of jumpers can be removed and placed by
hand with no special tools.
PCB
Printed circuit board.
PDI
PHYTEC Display Interface; defined to connect PHYTEC display adapter
boards, or custom adapters
PEB
PHYTEC Extension Board
POR
Power-on reset
RTC
Real-time clock.
SMT
Surface mount technology.
SOM
System on Module; used in reference to the KSP-0180-x
/phyCORE
®
-MPC5676/57xx module
Sx
User button Sx (e.g. S1, S2, etc.) used in reference to the available user
buttons, or DIP-Switches on the carrier board.
Sx_y
Switch y of DIP-Switch Sx; used in reference to the DIP-Switch on the
carrier board.
Table 2: Abbreviations and Acronyms used in this Manual

phyCORE
®- MPC5676/57xx [KSP-0180-0]
viii PHYTEC Messtechnik GmbH 2020 L-807e.A2
Preface
As a member of PHYTEC's phyCORE®product family the phyCORE-MPC5676/57xx is one of a
series of PHYTEC System on Modules (SOMs) that can be populated with different
controllers and, hence, offers various functions and configurations. PHYTEC supports a
variety of 8-/16- and 32-bit controllers in two ways:
(1) as the basis for Rapid Development Kits which serve as a reference and evaluation
platform
(2) as insert-ready, fully functional phyCORE®OEM modules, which can be embedded
directly into the user’s peripheral hardware design.
Implementation of an OEM-able SOM subassembly as the "core" of your embedded design
allows you to focus on hardware peripherals and firmware without expending resources to
"re-invent" microcontroller circuitry. Furthermore, much of the value of the phyCORE®
module lies in its layout and test.
Production-ready Board Support Packages (BSPs) and Design Services for our hardware
will further reduce your development time and risk and allow you to focus on your product
expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce
development costs, and avoid substantial design issues and risks. With this new,
innovative full-system solution, you will be able to bring your new ideas to market in the
most timely and cost-efficient manner.
For more information go to:
http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html
or
www.phytec.eu/europe/oem-integration/evaluation-start-up.html
Ordering Information
The part numbering of the phyCORE has the following structure:
KSP-0180-x (x=Version)

Preface
PHYTEC Messtechnik GmbH 2020 L-807e.A2 ix
Product Specific Information and Technical Support
In order to receive product specific information on changes and updates in the best way
also in the future, we recommend to register at
http://www.phytec.de/de/support/registrierung.html or
http://www.phytec.eu/europe/support/registration.html
For technical support and additional information concerning your product, please visit the
support section of our web site which provides product specific information, such as errata
sheets, application notes, FAQs, etc.
https://www.phytec.de/produkt/system-on-modules/phycore-mpc567x-download/#faq
or
https://www.phytec.eu/product-eu/system-on-modules/phycore-mpc567x-
download/#faq
Declaration of Electro Magnetic Conformity of the PHYTEC
phyCORE®-MPC5676/57xx
PHYTEC System on Module (henceforth products) are designed for installation in electrical
appliances or as dedicated Evaluation Boards (i.e. for use as a test and prototype platform
for hardware/software development) in laboratory environments.
Caution!
PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence,
may only be unpacked, handled or operated in environments in which sufficient
precautionary measures have been taken in respect to ESD-dangers. It is also necessary
that only appropriately trained personnel (such as electricians, technicians and engineers)
handle and/or operate these products. Moreover, PHYTEC products should not be operated
without protection circuitry if connections to the product's pin header rows are longer
than 3 m.
PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic
Conformity only in accordance to the descriptions and rules of usage indicated in this
hardware manual (particularly in respect to the pin header row connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as user modifications and
extensions of PHYTEC products, is subject to renewed establishment of conformity to, and
certification of, Electro Magnetic Directives. Users should ensure conformance following
any modifications to the products as well as implementation of the products into target
systems.

phyCORE
®- MPC5676/57xx [KSP-0180-0]
xPHYTEC Messtechnik GmbH 2020 L-807e.A2
Product Change Management and information in this manual on parts populated on
the SOM / SBC
When buying a PHYTEC SOM / SBC, you will, in addition to our HW and SW offerings, receive
a free obsolescence maintenance service for the HW we provide.
Our PCM (Product Change Management) Team of developers, is continuously processing,
all incoming PCN's (Product Change Notifications) from vendors and distributors
concerning parts which are being used in our products.
Possible impacts to the functionality of our products, due to changes of functionality or
obsolesce of a certain part, are being evaluated in order to take the right masseurs in
purchasing or within our HW/SW design.
Our general philosophy here is: We never discontinue a product as long as there is
demand for it.
Therefore we have established a set of methods to fulfill our philosophy:
Avoiding strategies
•Avoid changes by evaluating longevity of parts during design in phase.
•Ensure availability of equivalent second source parts.
•Stay in close contact with part vendors to be aware of roadmap strategies.
Change management in rare event of an obsolete and non replaceable part
•Ensure long term availability by stocking parts through last time buy management
according to product forecasts.
•Offer long term frame contract to customers.
Change management in case of functional changes
•Avoid impacts on product functionality by choosing equivalent replacement parts.
•Avoid impacts on product functionality by compensating changes through HW redesign
or backward compatible SW maintenance.
•Provide early change notifications concerning functional relevant changes of our
products.
Therefore, we refrain from providing detailed part specific information within this
manual, which can be subject to continuous changes, due to part maintenance for
our products.
In order to receive reliable, up to date and detailed information concerning parts
used for our product, please contact our support team through the contact
information given within this manual.

Pin Description
PHYTEC Messtechnik GmbH 2020 L-807e.A2 11
1Introduction
The phyCORE-MPC5676/57xx belongs to PHYTEC’s phyCORE System on Module family. The
phyCORE SOMs represent the continuous development of PHYTEC System on Module
technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards
integrate all core elements of a microcontroller system on a subminiature board and are
designed in a manner that ensures their easy expansion and embedding in peripheral
hardware developments.
As independent research indicates that approximately 70 % of all EMI (Electro Magnetic
Interference) problems stem from insufficient supply voltage grounding of electronic
components in high frequency environments approximately 20 % of all pin header
connectors on the phyCORE bus are dedicated to Ground. This improves EMI and EMC
characteristics and makes it easier to design complex applications meeting EMI and EMC
guidelines using phyCORE boards even in high noise environments.
phyCORE boards achieve their small size through modern SMD technology and multi-layer
design. In accordance with the complexity of the module, 0402-packaged SMD
components and laser-drilled microvias are used on the boards, providing phyCORE users
with access to this cutting edge miniaturization technology for integration into their own
design.
The phyCORE-MPC5676/57xx is a subminiature (58 mm x 82 mm) insert-ready System on
Module populated with the Freescale Semiconductor MPC5676R microcontroller. Its
universal design enables its insertion in a wide range of embedded applications.
Precise specifications for the controller populating the board can be found in the
applicable controller reference manual or datasheet. The descriptions in this manual are
based on the Freescale Semiconductor MPC5676R. No description of compatible
microcontroller derivative functions is included, as such functions are not relevant for the
basic functioning of the phyCORE-MPC5676/57xx.
1.1 Features of the phyCORE-MPC5676/57x
The phyCORE-MPC5676/57xx offers the following features:
•Subminiature System on Module (58 mm x 82 mm) achieved through modern SMD
technology
•Populated with the Freescale Semiconductor MPC5676R/MPC5674F/MPC57xx
microcontroller (BGA516 packaging)
•Controller signals and ports extend to two high-density (0.5 mm) Samtec connectors
aligning two sides of the board enabling the phyCORE-MPC5676/57xx to be plugged
like a "big chip" into target application
•FPGA ports extend to a third high-density (0.5 mm) Samtec connector placed on short
side of the Module

phyCORE
®- MPC5676/57xx [KSP-0180-0]
12 PHYTEC Messtechnik GmbH 2020 L-807e.A2
1.1.1 Internal Features of the MPC5676R
•32-bit Dual Power Architecture® 200z7 cores, up to 2 x 180MHz clock frequency
•6 MB int. Flash memory
•32ch eMIOS
•3x +32 eTPU
•64 channel 12-bit quad ADC
•4 x FlexCAN
•3-ch.eSCI
•5-ch.DSPI
•2-ch. FlexRay
•12 decimation filters
•384KB SRAM
•EBI ( External Bus Interface )
1.2 Memory Configuration of the phyCORE-MPC5676/57xx
•SRAM: 2 MByte to 8 MByte Synchronous Flow-Through Burst-RAM,
32-bit access
•Flash: 2 MByte to 8 MByte asynchronous standard Flash,
32-bit acces
•32k kB SPI EEPROM
•16Mbyte Dual/Quad SPI NOR-Flash (FPGA configuration memory)
1.3 Other Board-Level Features
•All controller and FPGA required supplies are generated on board
•Voltage Supervisor IC
•UART: two RS-232 transceivers for channel A and B (RxD/TxD), also usable as TTL
•Ethernet: 10/100 Mbit/s LAN9221I , 16-bit EBI access from CPU
•Bootconfig pins for boot source selection (int. Flash (standard), ext. Flash)
•Support of standard 14 pin debug interface through JTAG connector
•Xilinx Artix7 FPGA (XC7A35T…XCA100T)
•FPGA configuration memory programmable via JTAG
•SPI-RTC battery-buffered
•Watchdog
•Industrial temperature range (-40 °C to +85 °C)
•Free I/Os from CPU and 101 I/Os FPGA (Bank14/15/34) available on phyCORE-
connector

Pin Description
PHYTEC Messtechnik GmbH 2020 L-807e.A2 13
1.4 Block Diagram
Figure 1: Block Diagram of the phyCORE-MPC5676/57xx

phyCORE
®- MPC5676/57xx [KSP-0180-0]
14 PHYTEC Messtechnik GmbH 2020 L-807e.A2
1.5 phyCORE-MPC5676/57xx Component Placement
Figure 2: phyCORE-MPC5676/57xx Component Placement (top view)
C68
C22
C35
L5
U7b
L1
U9
C140
C127
J30
C106
R18
X8
C51
C111
R32
R34
C60
C4
R84
C18
C65
C20
C37
C175 C33
L3
U1
C124
J6
R39
C100
C78
R11
R95
C138
C171
Q2
C59
J10
C112
C105
C153
U20
R67
J12
U7
J19
L9
C53
R8
R4
Q1
B4
U102
C172
C173
J37
R15
R35
C107
C169
J32
C49
C170
C123
R57 R9
J11
C75
L2
R20
U17
R83
R62 J4
R86
C164
R58
C50
C161
J17
J14
R38
J22
C52
U2
C3
C57
C119
R28
C55
J35
C21
C73
C56
L13
C104
R13
C67
R7
R29
R46
C125
C108
B3
R42
J25
C7
C128
R60
R30 R90
J24
R53
XT1
C116
R59
R97
C79
C176
U3
C54
R89
C38
R54
R94
J26
C2
C6 C5
C24
C167
RN4
J15
J23
R45
B2
C103
J18
U18
R52
C139
J36
J38
R36
C126
J34
J2
L12
J16
RN1
R31
C23 C9
R43
R19
R26
C69
U10
B1
C58
C166
R6
U6
C113
L6
R14
C31
R48
R10
R41
J3
C8
R3
C48
R103
J20
J5
R47
R87
C163
R98
R23
R61
R12
R55
U101
R96
C101
C36
C109
C61
C110
C63
C102
R50 J21
C150
XT2
U13
C118
R85
R27
C19
C76
R56
C66
U21
R65
C32
C77
R66

Pin Description
PHYTEC Messtechnik GmbH 2020 L-807e.A2 15
Figure 3: phyCORE-MPC5676/57xx Component Placement (top view)
X2
X3
X1
C96
C147
C41
L7
C82
L4
RN6
R33
C168
C12
R16
R72
J1
R81
R70
R91
C99
C13
C160
C43
C151
C135
R80
J9
R74
R73
R40
C142
C97
C94
C64
C146
R93
C145
R79
C29
C129
RN3
U4
R1 C141
C174
C17
J27
C80
C152
R77
C44
R76 C92
R100
R17
L10
R44
C25
C86
R68
J31
C165
C1
C134
C117
C72
C156
RN7
R21
L11
R37
C40
C95
R51
U103
C39
C91
C87
C85
C70
C71
C10
C26
R63
C30 C14
C159
C114
C136
C15
R92
J28
TP1
C122
C120
C158
C16
J33
R22
U5
J8
R2
C89
R99
R78
J7
C143
C34
R71
C27
J39
J29
C157
C28
C144
U14
R88
C155
C149
C130
J13
C42
R101
C45
C88
R75
R5
R82
R24
C62
C121
C83
C74
C132
U100
C84
R25
R69
C162
C154
U11
C148
C137
RN5
U12
C115
C98
U19
C46
C90
C11
C93
R102
C47
L8 TP2
R49
RN2
R64
C81

phyCORE
®- MPC5676/57xx [KSP-0180-0]
16 PHYTEC Messtechnik GmbH 2020 L-807e.A2
1.6 Minimum Requirements to operate the phyCORE-MPC5676/57xx
Basic operation of the phyCORE-MPC5676/57xx only requires supply of a +3.3 V and a +5 V
input voltage as shown below:
1.6.1 phyCORE-MPC5676/57xx without FPGA
Supply voltage VCC_3V3: +3,3 V +/-5% - calculated max. 4,6@VCC_3V3 (1400mA) for the
module FPGA excluded and no external connection
Typical: 1.3 W @ 3.3V (condition: CPU with SW during production test)
Supply voltage VCC_5V: +5 V 5% - application dependent; powers the MPC5676/57x ADC
Note:
On the MPC5777C, the VCC_5V also supplies VDDEH1 of the CPU and, therefore, the
eTPU_A, eSCI_B, and the I/O supply voltage configuration (medium I/O pads).
1.6.2 phyCORE-MPC5676/57xx with FPGA
Supply voltage VCC_3V3: +3.3 V 5% - application dependent – since the power
requirement for the FPGA is application dependent, the requirement is the sum of the
following points (users should use the power calculation tool from XILINK):
•0,33@3,3 W (100mA) (only FPGA quiescent current)
•Max. additional 3 W @ VCC_3V3 from onboard regulator U20 1 V (C A) for FPGA
“vccint” + “VCCBRAM” supply
•Max. additional 6 W @ VCC_3V3 from onboard regulator U21 1V8 (3A) for PFGA
“vccadc” + “VCCAUX” supply
•Additional power X @ VCC_3V3 for the VCCO_0 + VCCO_14 + VCCO_15 + VCCO_34,
VCCO_35
•There is also three possibilities to supply 1 V or 1V8 for the FPGA directly from the
FPGA connector X3 if needed (this will also disable/unpopulate the U20/U21
regulator)
Please refer to
Section 2 for information on additional GND Pins located at the phyCORE-
Connector X1.
Caution!
We recommend connecting all available +3.3 V and +5V input pins to the power supply
system on a custom carrier board housing the phyCORE-MPC5676/57xx and at least the
matching number of GND pins neighboring the +3.3 V pins and +5V.
In addition, proper implementation of the phyCORE-MPC5676/57xx module into a target
application also requires connecting all GND pins neighboring signals that are being used
in the application circuitry.
Please refer to section 4 for more information.

Pin Description
PHYTEC Messtechnik GmbH 2020 L-807e.A2 17
2Pin Description
Please note that all module connections are not to exceed their expressed maximum
voltage or current. Maximum signal input values are indicated in the corresponding
controller manuals/data sheets. As damage from improper connections varies according to
use and application, it is the user's responsibility to take appropriate safety measures to
ensure that the module connections are protected from overloading through connected
peripherals.
As
Figure 4 indicates, all controller signals selected extend to surface mount technology
(SMT) connectors (0.5 mm) lining two sides of the module (referred to as
phyCORE-Connector). This allows the phyCORE-MPC5676/57xx to be plugged into any
target application like a "big chip".
The numbering scheme for the phyCORE-Connector is based on a two dimensional matrix in
which column positions are identified by a letter and row position by a number.
The numbering scheme for the phyCORE-Connector is based on a two dimensional matrix in
which column positions are identified by a letter and row position by a number with
prefixed Connector Reference (X1, X2, and X3). Pin X1A1, for example, is located in the
upper left hand corner of the matrix looking down through the top of the SOM (refer to
Figure 4
).
The numbered matrix can be aligned with the phyCORE-MPC5676/57xx (viewed from
above; phyCORE-Connector pointing down) or with the socket of the corresponding
phyCORE Carrier Board/user target circuitry. The numbering scheme is always in relation to
the PCB as viewed from above, even if all connector contacts extend to the bottom of the
module.
The numbering scheme is thus consistent for both the module’s phyCORE-Connector as well
as the mating connector on the phyCORE Carrier Board or target hardware, thereby
considerably reducing the risk of pin identification errors.
The following figure illustrates the numbered matrix system. It shows a
phyCORE-MPC5676/57xx with all three SMT phyCORE-Connectors on its underside (defined
as dotted lines) mounted on a carrier board. In order to facilitate understanding of the pin
assignment scheme, the diagram presents a cross-view of the phyCORE-MPC5676/57x
module showing the phyCORE-Connector mounted on the underside of the module’s PCB.
Table 3 to Table 8 provide an overview of the pinout of the different phyCORE-Connectors
X1,X2,X3 with signal names and descriptions specific to the phyCORE-MPC5676/57xx. It
also provides the appropriate voltage domain, signal type (ST) and a functional grouping
of the signals. The signal type includes also information about the signal. A description of
the signal types can be found in
Table 1 .

phyCORE
®- MPC5676/57xx [KSP-0180-0]
18 PHYTEC Messtechnik GmbH 2020 L-807e.A2
Figure 4: Pinout of the phyCORE-Connector (top view)
The Freescale Semiconductor MPC5676R is a multi-voltage operated microcontroller and as
such special attention should be paid to the interface voltage levels to avoid unintentional
damage to the microcontroller and other on-board components. Please refer to the
Freescale Semiconductor MPC5676R Reference Manual for details on the functions and
features of controller signals and port pins.
Caution:
Most of the controller pins have multiple multiplexed functions. Because most of these
pins are connected directly to the phyCORE-Connector the functions are also available
there. Signal names and descriptions in Table 3 to Table 8 however, are in regard to the
specification of the phyCORE-MPC5676/57xx and the functions defined therein. Please
refer to the MPC5676R Reference Manual , or the schematic to get to know about alternative
functions. In order to utilize a specific pin's alternative function the corresponding
registers must be configured within the appropriate driver of the BSP. To support all
features of the phyCORE-MPC5676/57xx Carrier Board a few changes have been made in
the BSP delivered with the module.
X1A1
X1
X1A90
X1B90
X1B1
X2
X2A1
X2A90
X2B90
X2B1
X3
X3A1
X3A90
X3B1
X3B90