Radstone PME 68-1B User manual

PME 68-1B Manual
Rev. 2
Issue 5
Publication No. 421/HH/23144/000
Radstone Technology plc
Water Lane,
Towcester,
Northants.,
NN12 7JN
Telephone: [phone]
Telex: 31628 RADSTN G
© Radstone Technology plc 1990
Issue 1 © The Plessey Company plc 1985
Issue 2 © The Plessey Company plc 1987
Issue 3 © The Plessey Company plc 1988
Issue 4 © Radstone Technology plc 1989
This publication is issued to provide outline information only which (unless agreed by the
Company in writing) may not be used, applied or reproduced for any purpose or form part
of anyorder or contract or be regarded as a representation relating to products or services
concerned.The Companyreservesthe right to alter without notice the specification,design,
price or conditions of supply of any product or service.
January 1990

Trademarks
RADSTONE the RADSTONE symbol, PME, and PLUM are trademarks of
Radstone Technology plc.
VERSAdos is a trademark of Motorola.
Board Identification
All Radstone baoards can be identified by a label fitted to the component side of P1.
This publication describes the PME 68-1B at Revision state Rev.2 (all letter codes).
Unique board serial number
MADE IN ENGLAND SERIAL NUMBER REV NO.
Drawing list number, used
during manufacture
Part/variant number, all PME
board numbers begin with 421/1/
so this is not shown
Revision number,
e.g. C or 2F, revision
1 number is not shown

Table of Contents
Chapter 1 - Introduction
Introduction ......................................................................................................... 1
Operational Overview ........................................................................................ 7
Features .......................................................................................................... 7
I/O Facilities .................................................................................................. 8
Memory .......................................................................................................... 8
R eal Time Operation ................................................................................... 8
Chapter 2 - Specification
G eneral ................................................................................................................. 9
Operating.............................................................................................................. 10
MTBF .................................................................................................................... 10
Storage .................................................................................................................. 10
Chapter 3 - Functional Description
H ardware Overview ............................................................................................ 11
Front Panel .................................................................................................... 11
68000 Hardware Description ...................................................................... 12
Processor ........................................................................................................ 12
Memory................................................................................................................. 14
R AM Area ..................................................................................................... 15
R AM R efresh ................................................................................................ 15
Local I/O and Control Devices.......................................................................... 18
Serial I/O ....................................................................................................... 18
Terminal Interface ........................................................................................ 18
Address Assignment of Terminal Interface ............................................. 20
R emote Interface .......................................................................................... 20
Address Assignment - R emote Interface .................................................. 21
H ost Interface ................................................................................................ 21
Address Assignment - H ost Interface ........................................................ 22
Serial I/O Interface Summary ..................................................................... 24
ACIA Access Time ...................................................................................... 25
R eal Time Clock.................................................................................................. 26
Addressing the R TC ..................................................................................... 26
R TC Interrupts .............................................................................................. 27
R TC Summary .............................................................................................. 27
Parallel I/O Interface .......................................................................................... 28
PI/T Addressing............................................................................................. 28
PI/T Interrupts ............................................................................................... 29
Centronics Type Interface ........................................................................... 30
PI/T Summary ............................................................................................... 30
Interrupt H andling .............................................................................................. 31
On-board Interrupt Sources ........................................................................ 31
Software ABO RT Switch ............................................................................. 32
ACFAIL ......................................................................................................... 32
Interrupt E xception Sequence .................................................................... 32
VME bus Interrupt H andling....................................................................... 35
PME68-1B Manual
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VME bus Arbitration .................................................................................... 36
U sing PME 68-1B as the System Bus Arbiter........................................... 37
Bus R elease Functions ................................................................................ 38
VME BU S Interface ........................................................................................... 39
SYSCLK Signal ............................................................................................ 39
SYSR ESET* Signal ...................................................................................... 39
R ESE T Switch ............................................................................................... 39
SYSFAIL* Signal .......................................................................................... 39
Address Modifier Codes .............................................................................. 39
Function Codes ............................................................................................. 41
Short I/O Address Modifier Code .............................................................. 41
Bus E rror Function ....................................................................................... 41
Connectors ........................................................................................................... 42
VMEbus P1 Connector ................................................................................ 42
P2 Pin Assignments....................................................................................... 43
P3 Pin Assignments ...................................................................................... 44
P4/P5 Pin Assignments................................................................................. 44
Chapter 4 - Configuration
Preparation For U se ........................................................................................... 45
Fitting a Battery................................................................................................... 45
Link Settings ........................................................................................................ 47
R AM/PR OM/E PR OM Area............................................................................. 52
System Area ................................................................................................... 52
System Connections...................................................................................... 52
U ser Area ....................................................................................................... 54
Access Speed Select ...................................................................................... 56
Local I/O and Control Devices.......................................................................... 57
Terminal Interface ........................................................................................ 57
R emote Interface .......................................................................................... 58
H ost Interface ................................................................................................ 59
Baud R ate Selection ..................................................................................... 60
R TC Interrupts .................................................................................................... 62
Parallel I/O Interface and Timer ....................................................................... 63
Centronics Type Interface ........................................................................... 63
Interrupt H andling .............................................................................................. 66
ACFAIL Interrupt ........................................................................................ 66
VME bus Interrupt H andling....................................................................... 66
VME bus Arbitration........................................................................................... 67
On-Board D TB Slave Bus Arbitration....................................................... 67
Off-Board Arbitration .................................................................................. 68
Bus-R elease Functions ................................................................................ 68
VME BU S Interface ............................................................................................ 69
SYSCLK Signal ............................................................................................. 69
SYSR ESET* Signal ...................................................................................... 69
SYSFAIL* Signal .......................................................................................... 70
BCLR * Signal ................................................................................................ 70
Short I/O Address Modifier Code .............................................................. 71
Bus E rror Function ....................................................................................... 73
PME68-1B Manual
(ii)

Chapter 5 - PME68/Monitor
Software Capabilities.......................................................................................... 75
G eneral System O verview.................................................................................. 77
Power-U p Sequence ..................................................................................... 77
R ESE T Switch ............................................................................................... 77
ABOR T Switch .............................................................................................. 77
Vectors and E rrors........................................................................................ 78
Interrupt Level Assignment......................................................................... 79
Return to the Monitor .................................................................................. 80
The H ALT Indicator .................................................................................... 80
PME68/Monitor Memory Map ................................................................... 81
Operation of the PME 68/Monitor .................................................................... 82
System Operation .......................................................................................... 82
Terminal Control Characters ...................................................................... 83
Command Line Format ................................................................................ 83
Monitor Commands ............................................................................................ 85
BLO CK FILL ME MOR Y .....................................................BF ................ 86
BLO CK MOVE .....................................................................BM ............... 86
G ET/DISPLAY BR EAKPO INT ........................................BR ............... 87
BLO CK SE AR CH ..................................................................BS ................ 88
BLO CK TE ST OF ME MOR Y ............................................BT ................ 89
DATA CO NVE RSION ........................................................DC ............... 89
DU MP ME MO RY ................................................................DU ............... 90
G O E XE CU TE PR OG RAM ...............................................G O ............... 91
GO DIRECT TO EXE CUTE PROG RAM ......................GD ............... 91
G O U NTIL BR EAKPOINT ................................................G T ............... 92
H ELP ........................................................................................H E ............... 93
LOAD OBJECT FILE ..........................................................LO ............... 94
MEMORY DISPLAY ...........................................................MD .............. 95
ME MOR Y MODIFY ............................................................MM .............. 96
ME MOR Y SE T .....................................................................MS ............... 98
R EMOVE BR EAKPOINT ...................................................NO BR ......... 98
DE TACH PR INTE R ............................................................NOPA ......... 99
OFFSET ...................................................................................OF ................ 99
ATTACH PR INTE R ............................................................PA ................ 100
POR T FOR MAT ...................................................................PF ................ 100
TR ANSPAR ENT MODE ....................................................TM ............... 101
TR ACE ....................................................................................TR ............... 102
TR ACE TO TE MPO RAR Y BR EAKPO INT ..................TT ................ 103
VE RIFY ..................................................................................VE ............... 104
DISPLAY/SE T R EG ISTE R ................................................A0 - .A7....... 105
MEMORY DISPLAY DISASSEMBLER ........................MD ...;DI ....105
MEMORY MODIFY DISASSEMBLER/ASSEMBLER MM...;DI ..106
U sing the Assembler/Disassembler .................................................................. 107
Introduction ................................................................................................... 107
68000 Assembly Language ........................................................................... 107
Directives ....................................................................................................... 108
Source Program Coding ............................................................................... 108
Disassembled Source Line ........................................................................... 108
PME68-1B Manual
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Mnemonics and D elimiters ......................................................................... 109
Character Set ................................................................................................. 110
Source Code Format..................................................................................... 110
Assembler Language Format ...................................................................... 110
DC.W D efine Constant Directive .............................................................. 112
Entering and Modifying Source Programs ................................................ 112
Calling the Assembler/Disassembler ......................................................... 112
Program Input................................................................................................ 113
Disassembled Program Listings .................................................................. 113
Saving Programs ............................................................................................ 114
Download from a H ost ................................................................................. 114
U ser Application Software E xamples .............................................................. 116
Data Transfer (From and To) an ACIA........................................................... 116
Output of One Line to the RE MOTE ACIA ........................................... 116
Input of One Line from the Remote ACIA ............................................. 117
Initialisation of the Real-time Clock ................................................................118
Address Assignment of I/O Devices ................................................................. 119
6850 ACIA ( Terminal ) ............................................................................... 119
6850 ACIA ( H ost )....................................................................................... 119
6850 ACIA (Remote) ................................................................................... 119
68230 PI/T (Parallel Interface/Timer) .................................................... 120
58167A RTC (R eal Time Clock) .............................................................. 121
Error Messages and Monitor Messages ........................................................... 122
E rror Message ............................................................................................... 122
Monitor Messages ......................................................................................... 122
Addresses of the Main System R outines ......................................................... 123
S-R ecord Format ................................................................................................. 124
PME68-1B Manual
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Chapter 1 - Introduction
The PME 68-1B CPU is a single board computer which combines a powerful 16 bit mi-
croprocessor, the Motorola 68000, with 128k or 512k bytes of dynamic RAM (DRAM),
up to 256k bytes of EPROM or EPROM + SRAM, a programmable real time clock,
plus three serial and one parallel input/output (I/O) interfaces. It provides reliable, high
speed processing at low cost, in addition to providing 3 interfaces; typically two would be
used for a host computer and terminal, and the third for a remote interface for a second
terminal, printer, or back-up peripheral.
Access to all these on-board devices is provided by an EPROM resident Monitor,
(PME68 or PLUM) which is supplied with the board. This powerful software package
can be used for program development and debugging.
The PME 68-1B is supported by Radstone VERSAdos operating system. This software
provides for Realtime, Multiuser, Multitasking systems.
The PME 68-1B is a sophisticated VMEbus CPU board which may be used in a multi-
processor environment. It may also be used as a single board computer using its on-
board I/O and timer functions.
Vari ants
The nature of the board variant is indicated by the last three digits of the part number.
e.g. ---/-/-----/XXX
The first digit:
/1XX= Standard board with PME68/Monitor
/2XX= VERSAdos + VERSAdos support with PLUM Monitor
/3XX= Special Variants
The third digit identifies processor speed and DRAM combination:
XX0 = 68000 8 MHz. 128k DRAM
XX1 = 68000 10 MHz. 128k DRAM
XX2 = 68000 8 MHz. 512k DRAM
XX3 = 68000 10 MHz. 512k DRAM
PME 68-1B Manual
Page 1 Issue 5

Figure 1 The PME 68-1B Board
Photograph not available in PDF
PME 68-1B Manual
Page 2 Issue 5

PME68-1B is available with an 8 MHz or 10 MHz, 68000 CPU and various capacities of
DRAM. The standard variants are:
Order No. Description Part No.
PME68-1B/100 8 MHz 68000, 128k bytes of DRAM 421/1/23144/100
PME68-1B/101 10 MHz 68000, 128k bytes of DRAM 421/1/23144/101
PME68-1B/102 8 MHz 68000, 512k bytes of DRAM 421/1/23144/102
PME68-1B/103 10 MHz 68000, 512k bytes of DRAM 421/1/23144/103
This manual provides a general operating description of all variants of the PME 68-1B
and includes information for installation and troubleshooting in Chapter 4, plus details
of the PME68/Monitor in Chapter 5.
Certain ‘application specific’ boards are factory configured for individual users. For rea-
sons of confidentiality, detailed reference is not made to these boards, but default (fac-
tory set) link information is given.
Details of the 68000 Processor and the Parallel I/O Interface and Timer are given in the
respective Motorola data sheets available on request from your supplier.
Accessing the VME bus after a power-up reset
Occasionally, after a power-up reset, access to the VME bus may be denied. To over-
come this feature a dummy access to any PIT register should be made prior to accessing
the VME bus.
WARNING: See Chapter 4 before installing the battery.
PME 68-1B Manual
Page 3 Issue 5

Figure 2 The PME 68-1B Front Panel
RESET
ABORT
HALT LED
REMOTE
TERMINAL
HOST
Port 3
(P5)
Port 1
(P4)
(P3)
Port 2
PME 68-1B
RADSTONE
TECHNOLOGY
PME 68-1B Manual
Page 4 Issue 5

Figure 3 PME 68-1B Functional Block Diagram
VMEbus
Arbitration
CPU
68000
8/10 MHz.
Real
Time
Clock
User
128k byte
DRAM
Controller
Wire-
Wire-
Wire-
Wire-
Wire-
Wire-
VMEbus
Arbiter
Dynamic
RAM
128k byte
(512k byte)
Parallel
I/O
Interface
VMEbus
Interface
Port 3
(P5)
Port 1
(P4)
Port 2
(P3)
REMOTE
TERMINAL
HOST
RESET
ABORT
HALT
Area
Interrupt
and
Control
Logic
System
Area
128k byte
Battery
Back-up
P1
P2
Control
Data
Address
ACIA
6850
ACIA
6850
ACIA
6850
Wrap
Wrap
Wrap
Wrap
Wrap
Wrap
PME 68-1B Manual
Page 5 Issue 5

Figure 4 Component Layout Diagram
P5
P4
P3
BAT
PME 68-1B Manual
Page 6 Issue 5

Operational Overview
The operation of the PME 68-1B board is based around an 8 MHz or 10 MHz 68000 mi-
croprocessor unit with an asynchronous 16-bit data bus and 24-bit address bus. The
address bus provides a direct memory addressing range of 16M bytes. The CPU
communicates with on-board memory and I/O devices via an on-board local bus.
The address range from $000008 to $0FFFFF (1M byte) is assigned to on-board mem-
ory and I/O devices. All other addresses are external on the VMEbus.
The PME 68-1B board contains a number of features that allow it to act as the CPU of a
powerful system, one of a number of CPUs in a multi-processor system, or as a single
board computer.
Features
The PME 68-1B board contains the following features:
·Motorola 68000 CPU with 8 MH z clock, variants 100 and 102 or with 10 MHz
clock, variants 101 and 103
·Fully implemented VMEbus interface
·128k bytes of DRAM using 64k bit devices
512k bytes DRAM using 256k bit devices. Access time 280ns. Distributed refresh
300ns every 15ms
·Up to 128k bytes of EPROM for system firmware
·Up to 64k bytes of SRAM/or 128k byte EPROM for the user
·Real time clock with battery back-up
·Three RS-232C serial interfaces, 110 to 38400 baud
·Up/down load to/from a host computer (S Record format)
·Parallel interface and 24-bit timer with 5 bit prescaler
·Local interrupt handling via auto-interrupt vectors
·Freely selectable address range for short I/O address accesses
·Single level bus arbiter (Can be disabled to use an external arbiter)
·Powerful Monitor firmware including a line by line assembler/disassembler,
register/memory manipulation routines and special I/O handling routines
·RESET and ABORT switches
·Transparent mode
The hardware specification of the PME 68-1B is given in Chapter 2.
PME 68-1B Manual
Page 7 Issue 5

I/O Facilities
PME68-1B boards have three RS-232C interfaces, identified as Terminal (Port 1), Host
(Port 2) and Remote (Port 3) as shown in Figures 2 and 3.
Port 1 (connector P4) may be connected to a standard terminal to load and debug user
programs under control of the Monitor firmware.
Port 2 (connector P3) may be used for up/down loading of user programs and data, or in
the transparent mode to directly interface the Port 1 connected terminal to a host
computer.
Port 3 (connector P5) is a universal port capable of supporting: a serial printer, a floppy
disk system, a second terminal (multiuser station), or an external user task.
A 64-pin male connector (P2) located at the rear of the board, gives access to the
Parallel Interface and Timer module (PIT). The PIT provides 24 I/O lines and 4
control lines plus a 24-bit timer with 5-bit prescaler. P2 can be configured to give access
to all selected signals of the 3 serial ports.
Memory
The board is normally supplied with a 64k byte EPROM containing the PME68/ Moni-
tor. PLUM is supplied with variants 2XX or on request. Two additional JEDEC compat-
ible sockets are available and will accept either additional EPROMs or SRAMs. Details
of the firmware options are available from your supplier.
On-board DRAM is provided in the form of high performance, 64k bit or 256k bit de-
vices.
Real Time Operation
The programmable Real Time Clock can be used in conjunction with a multiuser/
multitasking operating system for real time applications.
PME 68-1B Manual
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Chapter 2 - Specification
General
Microprocessor Motorola 68000L Type
8 MHz on Variants 100 and 102
10 MHz on Variants 101 and 103
Bus Compliance VMEbus Rev. C.1
Data D08, D16
Address A16, A24
Parallel I/O and Timer 68230 type PIT
16 data lines and 8 control lines, configurable as a Centronics
type parallel interface
Timer, one 24-bit timer with 5-bit prescaler
Serial I/O Three 6850 type ACIAs configured as RS-232C interfaces.
Strap selectable baud rates 110 to 9600 baud or
440 to 38400 baud
Real Time Clock 58167A programmable real time clock, optional battery
back-up using a 3.0V lithium battery, such as a Varta CR 1/3 N
DRAM 128k bytes or 512k bytes
EPROM 128k byte system area part occupied by monitor
Up to 128k bytes user definable; alternatively up to 64k byte
SRAM
Power requirements + 5V 2.8A
+ 12V 220mA
-12V 200mA
Board dimensions Double Eurocard 234 x 160 mm
9.2 x 6.3 inches
Weight 0.55 kg 1.21 lb
PME68-1B Manual
Page 9 Issue 5

The PME 68-1B is designed to meet the following environmental specifications:
Operating
Temperature Range 0°C to + 55°C (ambient)
Cooling Requirements A linear airflow of not less than 500 ft/min across the board
is recommended
Relative humidity Up to 95% (non-condensing)
Thermal shock ±5°C per minute
Altitude -300 to + 3,000m (-1,000 to + 10,000 feet approx)
Vibration 5-100Hz. with 2g acceleration
Mechanical Shock 20g for 6ms (half sine) when mounted in a suitable racking
system
MTBF
The calculated mean time between failures for the PME 68-1B is 80,000 hrs. The failure
rates used in this calculation have been derived from the British Telecom Reliability
Handbook using method HRD4, MIL-HDBK-217D and in-house data.
Storage
Temperature -55°C to + 85°C
Relative humidity 0 to 95% (non-condensing)
Thermal shock ±10°C per minute
Altitude -300 to + 16,000m (-1,000 to 50,000 feet approx)
Vibration 0 to 500Hz, 2g acceleration
Mechanical Shock 20g for 6 ms (half-sine)
PME68-1B Manual
Page 10 Issue 5

Chapter 3 - Functional Description
This Chapter describes the features and function of the PME 68-1B board. Configura-
tion details are given in Chapter 4, and the PME68/Monitor details in Chapter 5. Details
of the PLUM Monitor are given in the Radstone Manual, publication number
651/HH/19050/000.
Copies of the circuit diagrams are available by completing the form at the back of this
manual. Please contact your supplier for PAL information.
Hardware Overview
Front Panel
The front panel of the PME 68-1B is shown in Figure 2 and contains:
(1) Reset Switch; a toggle switch, that is user defined to carry out a general VMEbus
reset or a reset of all on-board devices only.
(2) Abort Switch; a toggle switch used to abort the user program and return to the
resident Monitor.
(3) Halt Indicator; indicates the state of the CPU.
(4) Remote Interface Connector; used for connecting external equipment, e.g. serial
printer.
(5) Terminal Interface Connector; used to communicate with a standard terminal.
(6) Host Interface Connector; used to interface the terminal (connected in 5 above)
directly to a host computer.
(7) Ejector handles for easy insertion and retrieval of the board when rack mounted.
PME68-1B Manual
Page 11 Issue 5

68000 Hardware Description
Processor
The 68000 processor contains sixteen 32-bit registers, one 32-bit program counter and a
16 bit status register. The first eight registers (D0 to D7) are used as data registers for
byte (8-bit), word (16-bit) and long word (2 x 16-bit) data operations. The set of seven
address registers (A0 to A6) and the supervisor stack pointer may be used as software
stack pointers and base address registers. In addition, all 16 registers may be used for
word and long word address operations, or as index registers. Table 1 shows the
vector layout of the 68000.
Features of the 68000 CPU include:
·8 x 32-bit data registers
·7 x 32-bit address registers
·32-bit supervisor stack pointer or 32-bit user stack pointer
·16-bit status register
·16Mbyte direct addressing range
·56 powerful instruction types
·14 different addressing modes
·5 main data types
·Memory mapped I/O
·Asynchronous bus structure
For further details refer to the Motorola 68000 Data Sheet available from your supplier.
PME68-1B Manual
Page 12 Issue 5

Table 1 68000 Vector Table
Vector Address
No.(s) Decimal H ex Space Assignment
0 0 000 SP Reset: Initial SSP
- 4 004 SP Reset: Initial PC
2 8 008 SD Bus Error
3 12 00C SD Address Error
4 16 010 SD Illegal Instruction
5 20 014 SD Zero Divide
6 24 018 SD CHK Instruction
7 28 01C SD TRAPV Instruction
8 32 020 SD Privilege Violation
9 36 024 SD Trace
10 40 028 SD Line 1010 Emulator
11 44 02C SD Line 1111 Emulator
12* 48 030 SD Unassigned (Reserved)
13* 52 034 SD Unassigned (Reserved)
14* 56 038 SD Unassigned (Reserved)
15 60 03C SD Uninitialised Interrupt Vector
16 to 23* 64 040 SD Unassigned (Reserved)
95 05F
24 96 060 SD Spurious Interrupt
25 100 064 SD Level 1 Interrupt Auto-vector
26 104 068 SD Level 2 Interrupt Auto-vector
27 108 06C SD Level 3 Interrupt Auto-vector
28 112 070 SD Level 4 Interrupt Auto-vector
29 116 074 SD Level 5 Interrupt Auto-vector
30 120 078 SD Level 6 Interrupt Auto-vector
31 124 07C SD Level 7 Interrupt Auto-vector
32 to 47 128 080 SD Trap Instruction vectors
191 OBF
48 to 63* 191 0C0 SD Unassigned (Reserved)
255 0FF
65 to 255 256 100 SD User Interrupt Vectors
1023 3FF
SP = Supervisor Program
SD = Supervisor Data
* = Vector numbers 12, 13, 14, 16 to 23 and 48 to 63 are reserved by Motorola for
future enhancements. No user peripheral devices should be assigned to these
numbers.
PME68-1B Manual
Page 13 Issue 5

Memory
Figure 5 Memory Map of the PME 68-1B
000 000
: ROM Initialisation Vectors from SYSTEM EPROM
000 007
000 008
: SYSTEM DRAM Area (Reserved)
000 FFF
001 000
: USER DRAM Area (128k byte: variants 100 and 101)
01F FFF
: USER DRAM Area (512k byte: variants 102 and 103)
07F FFF
080 000 (080 000 - 080 007 used for stack 1 Prog. Counter data.)
: SYSTEM EPROM Area (128k byte)
09F FFF
0A0 000
: USER EPROM Area (128k byte)
0BF FFF
0C0 041
: RS-232C Interface (Host)
0C0 043
0C0 080
: RS-232C Interface (Terminal)
0C0 082
0C0 101
: RS-232C Interface (Remote)
0C0 103
0C0 401
:RTC
0C0 42F
0E0 001
:PIT
0E0 035
100 000
: OFF BOARD ADDRESSES
FFF FFF
PME68-1B Manual
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