Realtek RTL8169 User manual

RTL8169
2002/03/27 Rev.1.21
1
REALTEK GIGABIT
ETHERNET MEDIA ACCESS
CONTROLLER
WITH POWER MANAGEMENT
RTL8169
1. Features........................................................................ 2
2. General Description .................................................... 3
3. Block Diagram............................................................. 4
4. Pin Assignments .......................................................... 5
5. Pin Description ............................................................ 6
5.1 Power Management/Isolation Interface ................. 6
5.2 PCI Interface .......................................................... 7
5.3 FLASH/BootPROM/EEPROM/MII Interface ....... 9
5.4 LED Interface....................................................... 10
5.5 GMII, TBI, PHY CP ............................................ 10
5.6 Clock and NC Pins............................................... 12
5.7 Power Pins ........................................................... 12
6. Register Descriptions ................................................ 13
6.1 DTCCR: Dump Tally Counter Command............ 15
6.2 FLASH: Flash Memory Read/Write .................... 16
6.3 ERSR: Early Rx Status......................................... 16
6.4 Command ............................................................. 17
6.5 TPPoll: Transmit Priority Polling......................... 17
6.6 Interrupt Mask...................................................... 18
6.7 Interrupt Status..................................................... 19
6.8 Transmit Configuration ........................................ 20
6.9 Receive Configuration ......................................... 21
6.10 9346CR: 93C46 (93C56) Command.................. 23
6.11 CONFIG 0.......................................................... 23
6.12 CONFIG 1.......................................................... 24
6.13 CONFIG 2.......................................................... 25
6.14 CONFIG 3.......................................................... 25
6.15 CONFIG 4.......................................................... 26
6.16 CONFIG 5.......................................................... 27
6.17 Multiple Interrupt Select .................................... 28
6.18 PHYAR: PHY Access ........................................ 28
6.19 TBICSR: Ten Bit Interface Control and Status.. 28
6.20 TBI_ANAR: TBI Auto-Negotiation Advertisement .. 29
6. 21 TBI_LPAR: TBI Auto-Negotiation Link Partner Ability ....... 29
6.22 PHYStatus: PHY(GMII or TBI) Status.............. 30
6.23 RMS: Receive (Rx) Packet Maximum Size ....... 30
6.24 C+CR: C+ Command......................................... 31
6.25 RDSAR: Receive Descriptor Start Address....... 31
6.26 ETThR: Early Transmit Threshold..................... 31
6.27 Function Event ................................................... 32
6.28 Function Event Mask ......................................... 32
6.29 Function Preset State.......................................... 33
6.30 Function Force Event ......................................... 33
7. EEPROM (93C46 or 93C56) Contents ................... 34
7.1 EEPROM Registers.............................................. 35
7.2 EEPROM Power Management Registers............. 35
8. PCI Configuration Space Registers......................... 36
8.1 PCI Bus Interface ................................................. 36
8.1.1 Byte Ordering ............................................... 36
8.1.2 Interrupt Control........................................... 36
8.1.3 Latency Timer............................................... 36
8.1.4 64-Bit Data Operation .................................. 37
8.1.5 64-Bit Addressing......................................... 37
8.2 Bus Operation ...................................................... 37
8.2.1 Target Read................................................... 37
8.2.2 Target Write.................................................. 38
8.2.3 Master Read.................................................. 38
8.2.4 Master Write................................................. 39
8.2.5 Configuration Access ................................... 40
8.3 Packet Buffering .................................................. 40
8.3.1 Transmit Buffer Manager ............................. 40
8.3.2 Receive Buffer Manager............................... 40
8.3.3 Packet Recognition....................................... 40
8.4 PCI Configuration Space Table............................ 41
8.5 PCI Configuration Space Functions..................... 42
8.6 Default Value After Power-on (RSTB Asserted). 46
8.7 Power Management functions.............................. 47
8.8 Vital Product Data (VPD) .................................... 49
9. Functional Description ............................................. 50
9.1 Transmit & Receive Operations........................... 50
9.1.1 Transmit........................................................ 50
9.1.2 Receive ......................................................... 55
9.2 Loopback Operation............................................. 58
9.3 Collision............................................................... 58
9.4 Flow Control ........................................................ 58
9.4.1. Control Frame Transmission ....................... 58
9.4.2. Control Frame Reception ............................ 58
9.5 Memory Functions ............................................... 59
9.5.1 Memory Read Line (MRL) .......................... 59
9.5.2 Memory Read Multiple (MRM)................... 59
9.5.3 Memory Write and Invalidate (MWI) .......... 60
9.5.4 Dual Address Cycle (DAC).......................... 60
9.6 LED Functions..................................................... 61
9.6.1 Link Monitor ................................................ 61
9.6.2 Rx LED ........................................................ 61
9.6.3 Tx LED......................................................... 62
9.6.4 Tx/Rx LED................................................... 62
9.6.5 LINK/ACT LED........................................... 63
9.7 Physical Layer Interfaces ..................................... 64
9.7.1 Media Independent Interface (MII).............. 64
9.7.2 Gigabit Media Independent Interface (GMII) ...... 64
9.7.3 Ten Bit Interface (TBI)................................. 64
9.7.4 MII/GMII Management Interface................. 64
10. Application Diagrams............................................. 65
10.1 10/100/1000Base-T Application........................ 65
10.2 1000Base-X Application.................................... 65
11. Electrical Characteristics ....................................... 66
11.1 Temperature Limit Ratings................................. 66
11.2 DC Characteristics ............................................. 66
11.3 AC Characteristics ............................................. 67
11.3.1 FLASH/BOOT ROM Timing..................... 67
11.3.2 Serial EEPROM Interface Timing .............. 69
11.3.3 PCI Bus Operation Timing ......................... 70
11.3.4 MII Timing ................................................. 87
11.3.5 GMII Timing .............................................. 89
11.3.6 TBI Timing ................................................. 90
12. Mechanical Dimensions.......................................... 91

RTL8169
2002/03/27 Rev.1.21
2
1. Features
 208 pin QFP
 Supports descriptor-based buffer management
 Supports Microsoft* NDIS5 Checksum Offloads (IP,
TCP, UDP), and Largesend Offload
 Supports IEEE 802.1Q VLAN tagging
 Supports Transmit (Tx) Priority Queue for QoS, CoS
applications
 Supports major Tally Counters
 10Mbps, 100Mbps, and 1000Mbps operation at
MII/GMII, and 1000Mbps at TBI interfaces
 Supports 10Mbps, 100Mbps, and 1000Mbps N-way
Auto-negotiation operation
 PCI local bus single-chip Fast Ethernet controller
 Compliant to PCI Revision 2.2
 Supports both Little-Endian and Big-Endian
 Supports 16.75MHz-66MHz PCI clock
 Supports both 32-bit and 64-bit PCI bus
 Supports PCI target fast back-to-back transaction
 Supports Memory Read Line, Memory Read
Multiple, Memory Write and Invalidate, and
Dual Address Cycle
 Provides PCI bus master data transfers and PCI
memory space or I/O space mapped data
transfers of the RTL8169 operational registers
 Supports PCI VPD (Vital Product Data)
 Supports ACPI, PCI power management
 Supports optional PCI multi-function with
additional slave mode only functions
 Supports CardBus. The CIS can be stored in 93C56 or
expansion ROM
 Supports Boot ROM interface. Up to 128K bytes Boot
ROM interface for both EPROM and Flash memory
can be supported
 Supports 125MHz OSC as the internal clock source or
125MHz clock provided from external PHYceiver
 Compliant to PC97, PC98, PC99 and PC2001 standards
 Supports Wake-On-LAN function and remote wake-up
(Magic Packet*, LinkChg and Microsoft®wake-up
frame)
 Supports 4 Wake-On-LAN (WOL) signals (active high,
active low, positive pulse, and negative pulse)
 Supports auxiliary power-on internal reset, to be ready
for remote wake-up when main power still remains off
 Supports auxiliary power auto-detect, and sets the
related capability of power management registers in PCI
configuration space
 Advanced power saving mode when LAN function or
wakeup function is not used
 3.3V and 1.8V power supplies needed
 5V tolerant I/Os
 Includes a programmable, PCI burst size and early
Tx/Rx threshold
 Supports a 32-bit general-purpose timer with the
external PCI clock as clock source, to generate
timer-interrupt
 Contains two large independent transmit (8KB) and
receive (48KB) FIFO devices
 Uses 93C46 (64*16-bit EEPROM) or 93C56
(128*16-bit EEPROM) to store resource configuration,
ID parameter, and VPD data. The 93C56 can also be
used to store the CIS data structure for CardBus
applications
 Supports LED pins for various network activity
indications
 Supports both digital and external analog loopback
 Half/Full duplex capability (only Full duplex operation
at 1000Mbps)
 Supports Full Duplex Flow Control (IEEE 802.3x)
* Third-party brands and names are the property of their
respective owners.
These specifications are subject to change without notice.

RTL8169
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3
2. General Description
The Realtek RTL8169 is a highly integrated, high performance PCI Gigabit Ethernet Media Access Controller for use in network
adapters for servers and personal computers. The RTL8169 fully implements the 33/66MHz, 32/64-bit PCI v2.2 bus interface for
host communications with power management and is compliant with the IEEE 802.3 specification for 10/100Mbps Ethernet and
the IEEE 802.3z specification for 1000Mbps Ethernet. The RTL8169 supports the auxiliary power auto-detect function, and will
auto-configure related bits of the PCI power management registers in PCI configuration space.
It also supports the Advanced Configuration Power management Interface (ACPI), PCI power management for modern
operating systems that are capable of Operating System directed Power Management (OSPM) to achieve the most efficient
power management system possible.
In addition to the ACPI feature, the RTL8169 also supports remote wake-up (including AMD Magic Packet, LinkChg, and
Microsoft®wake-up frame) in both ACPI and APM environments. The RTL8169 is capable of performing an internal reset
through the application of auxiliary power. When the auxiliary power is applied and the main power remains off, the RTL8169 is
ready and waiting for the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin provides four different
output signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8169 LWAKE pin
provides motherboards with Wake-On-LAN (WOL) functionality.
The PCI specification is inherently little-endian. The RTL8169 contains the ability to do little-endian to big-endian swaps. It is
also possible that the RTL8169 can be used as a basis for a RISC CPU platform which expect the data to be in a big-endian
format. This feature allows for maximum flexibility.
PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies hardware (i.e., the RTL8169
LAN card). The information may consist of part number, serial number, and other detailed information.
The RTL8169 is fully compliant to Microsoft®NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task-offload features, and
supports IEEE802.1Q Virtual bridged Local Area Network (VLAN). All the above RTL8169 features contribute to lowering
CPU utilization, which is a benefit in operation as a server network card. Also, the RTL8169 boosts its PCI performance by
supporting PCI Memory Read Line & Memory Read Multiple when transmitting, and Memory Write and Invalidate when
receiving. To be better qualified as a server card, the RTL8169 also supports the PCI Dual Address Cycle (DAC) command,
when the assigned buffers reside at a physical memory addresses higher than 4 Gigabytes. For QoS, CoS requirements, the
RTL8169 supports hardware high priority queues to reduce software implementation effort and significantly improve
performance.
The RTL8169 keeps network maintenance costs low and eliminates usage barriers. It is the easiest way to upgrade a network
from 10/100Mbps to 1000Mbps. It also supports full-duplex operation, making possible 2000Mbps of bandwidth at no
additional cost. For special applications, the RTL8169 also supports a TBI interface, which can be used to provide a connection
to a Fiber channel, using a Fiber transceiver.

RTL8169
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3. Block Diagram
MII/GMII/TBI
Interface
Interrupt
Control
Logic
FIFO
Transmit/
Receive
Logic
Interface
Early Interrupt
Control Logic
FIFO
Control
Logic
Packet Type
Discriminator
Power Control Logic
PCI Interface + Register
Packet Length
Register
Early Interrupt
Threshold
Register
Boot ROM
Interface
EEPROM
Interface LED Driver
PCI Interface
MAC

RTL8169
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4. Pin Assignments
RTL8169
131 VDD33
138 TXD4
139 TXD3
140 TXD2
141 TXD1
142 TXD0
143 TXEN
144 VDD33
145 GTXCLK
146 TX8
147 TXCLK
148 CRS
149 GND
150 GND
151 COL
152 RXER
153 NC
154 RXCLK1
155 NC
156 RXCLK
157 RXDV
158 RXD0
159 RXD1
160 RXD2
161 RXD3
162 RXD4
163 RXD5
164 RXD6
165 RXD7
166 VDD18
167 VDD33
168 CLOCK125
169 MDC
170 MDIO
171 GND
172 ISOLATEB
173 M66EN
174 INTAB
175 RSTB
176 CLK
178 REQB
179 VDD33
180 AD31
181 AD30
182 AD29
183 AD28
184 GND
185 AD27
186 AD26
187 AD25
188 AD24
189 VDD33
190 CBE3B
191 IDSEL
192 AD23
193 AD22
194 AD21
195 GND
196 AD20
197 AD19
198 AD18
199 AD17
200 VDD33
201 AD16
202 CBE2B
203 FRAMEB
204 IRDYB
205 TRDYB
206 GND
207 DEVSELB
208 STOPB
1 PERRB
2NC
3 SERRB
4NC
5 PAR
6NC
7 CBE1B
130 OEB
129 WEB
128 ROMCSB
127 MD0
126 MD1
125 MD2
124 MD3
123 MD4
122 MD5
121 MD6
120 VDD18
119 MD7
118 LED0
117 GND
116 LED1
115 LED2
114 LED3
113 VDD33
112 MA16
111 MA15
110 MA14
109 MA13
108 NC
107 MA12
106 NC
105 MA11
102 MA9
101 MA8
100 MA7
99 MA6
98 GND
97 MA5
96 MA4
95 MA3
94 GND
93 EECS
92 MA2
91 MA1
90 MA0
89 VDD33
88 LWAKE
87 PMEB
86 CLKRUNB
85 AD32
84 AD33
83 AD34
82 GND
81 AD35
80 AD36
79 AD37
78 AD38
77 VDD33
76 AD39
75 AD40
74 AD41
73 AD42
72 GND
71 GND
70 AD43
69 AD44
68 VDD18
67 AD45
66 AD46
65 VDD33
64 AD47
63 AD48
62 AD49
61 AD50
60 GND
59 AD51
58 AD52
57 AD53
56 AD54
55 VDD33
54 AD55
53 AD56
52 AD57
51 NC
50 AD58
49 NC
48 GND
47 NC
46 AD59
45 NC
44 AD60
43 AD61
42 AD62
41 VDD33
40 AD63
39 PAR64
38 CBE4B
37 CBE5B
36 GND
35 CBE6B
34 CBE7B
33 GND
32 REQ64B
31 ACK64B
30 VDD33
29 AD0
28 AD1
27 VDD18
8 VDD33
9 AD15
10 AD14
11 AD13
12 AD12
13 GND
14 AD11
15 AD10
16 AD9
17 AD8
18 VDD33
19 CBE0B
20 AD7
21 AD6
22 AD5
23 GND
24 AD4
25 AD3
26 AD2
132 RSTPHYB
133 TBILBK
134 GND
135 TXD7
136 TXD6
137 TXD5
103 NC
177 GNTB
104 MA10

RTL8169
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5. Pin Description
In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are
separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation.
5.1 Power Management/Isolation Interface
Symbol Type Pin No Description
PMEB
(PME#)
O/D 87
Power Management Event: Open drain, active low. Used by the
RTL8169 to request a change in its current power management state
and/or to indicate that a power management event has occurred.
ISOLATEB
(ISOLATE#)
I 172
Isolate Pin: Active low. Used to isolate the RTL8169 from the PCI bus.
The RTL8169 does not drive its PCI outputs (excluding PME#) and
does not sample its PCI input (including RST# and PCICLK) as long as
the Isolate pin is asserted.
LWAKE/
CSTSCHG
O 88
LAN WAKE-UP Signal (When CardB_En=0, bit2 Config3):This
signal is used to inform the motherboard to execute the wake-up
process. The motherboard must support Wake-On-LAN (WOL). There
are 4 choices of output, including active high, active low, positive pulse,
and negative pulse, that may be asserted from the LWAKE pin. Please
refer to LWACT bit in CONFIG1 register and LWPTN bit in CONFIG4
register for the setting of this output signal. The default output is an
active high signal. Once a PME event is received, the LWAKE and
PMEB assert at the same time when the LWPME (bit4, CONFIG4) is
set to 0. If the LWPME is set to 1, the LWAKE asserts only when the
PMEB asserts and the ISOLATEB is low.
CSTSCHG Signal (When CardB_En=1, bit2 Config3): This signal is
used in CardBus applications only and is used to inform the
motherboard to execute the wake-up process whenever a PME event
occurs. This is always an active high signal, and the setting of LWACT
(bit 4, Config1), LWPTN (bit2, Config4), and LWPME (bit4, Config4)
means nothing in this case.
This pin is a 3.3V signaling output pin.

RTL8169
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7
5.2 PCI Interface
Symbol Type Pin No Description
AD63-0 T/S 40, 42-44, 46, 50,
52-54, 56-59, 61-64,
66-67, 69-70, 73-76,
78-81, 83-85, 180-183,
185-188, 192-194,
196-199, 201, 9-12,
14-17, 20-22, 24-26,
28-29
AD31-0: Low 32-bit PCI address and data multiplexed pins. The
address phase is the first clock cycle in which FRAMEB is asserted. During
the address phase, AD31-0 contains a physical address (32 bits). For I/O,
this is a byte address, and for configuration and memory, it is a double-word
address. The RTL8169 supports both big-endian and little-endian byte
ordering. Write data is stable and valid when IRDYB is asserted. Read data
is stable and valid when TRDYB is asserted. Data I is transferred during
those clocks where both IRDYB and TRDYB are asserted.
AD63-32: High 32-bit PCI address and data multiplexed pins.
During an address phase (when using the DAC command or when
REQ64B is asserted), the upper 32-bits of a 64-bit address are
transferred; otherwise, these bits are reserved, and are stable and
indeterminate. During a data phase, an additional 32-bits of data are
transferred when a 64-bit transaction has been negotiated by the
assertion of REQ64B and ACK64B.
C/BE7-0B T/S 34-35, 37-38, 190, 202,
7, 19
PCI bus command and byte enables multiplexed pins. During the
address phase of a transaction, C/BE3-0 define the bus command.
During the data phase, C/BE3-0 are used as Byte Enables. The Byte
Enables are valid for the entire data phase and determine which byte
lanes carry meaningful data. C/BE0 applies to byte 0, and C/BE3
applies to byte 3.
During an address phase (when using DAC commands or when
REQ64B is asserted), the actual bus command is transferred on
C/BE7-4; otherwise, these bits are reserved and indeterminate. During a
data phase, C/BE7-4 are Byte Enables indicating which byte lanes carry
meaningful data when a 64-bit transaction has been negotiated by the
assertion of REQ64B and ACK64B. C/BE4 applies to byte 4 and
C/BE7 applies to byte 7.
CLK I 176
PCI clock: This clock input provides timing for all PCI transactions and
is input to the PCI device. Supports up to a 66MHz PCI clock.
CLKRUNB I/O 86 Clock Run: This signal is used by the RTL8169 to request starting (or
speeding up) the clock, CLK. CLKRUNB also indicates the clock
status. For the RTL8169, CLKRUNB is an open drain output as well as
an input. The RTL8169 requests the central resource to start, speed up,
or maintain the interface clock by the assertion of CLKRUNB. For the
host system, it is an S/T/S signal. The host system (central resource) is
responsible for maintaining CLKRUNB asserted, and for driving it high
to the negated (deasserted) state.
DEVSELB S/T/S 207 Device Select: As a bus master, the RTL8169 samples this signal to
insure that a PCI target recognizes the destination address for the data
transfer. As a target, the RTL8169 asserts this signal low when it
recognizes its target address after FRAMEB is asserted.
FRAMEB S/T/S 203 Cycle Frame: As a bus master, this pin indicates the beginning and
duration of an access. FRAMEB is asserted low to indicate the start of a
bus transaction. While FRAMEB is asserted, data transfer continues.
When FRAMEB is deasserted, the transaction is in the final data phase.
As a target, the device monitors this signal before decoding the address
to check if the current transaction is addressed to it.
cont...

RTL8169
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8
GNTB I 177
Grant: This signal is asserted low to indicate to the RTL8169 that the
central arbiter has granted the ownership of the bus to the RTL8169.
This input is used when the RTL8169 is acting as a bus master.
ACK64B S/T/S 31 Acknowledge 64-bit Transfer: This signal is asserted low by the
device that has positively decoded its address as the target of the current
access, indicates the target is willing to transfer data using 64 bits.
ACK64B has the same timing as DEVSELB.
REQB T/S 178
Request: The RTL8169 will assert this signal low to request the
ownership of the bus from the central arbiter.
REQ64B S/T/S 32 Request 64-bit Transfer: The RTL8169 asserts this signal low to
indicate that it wants to perform a 64-bit data transfer.
If the RTL8169 sees the REQ64B asserted on the rising edge of PCI
RSTB, the RTL8169 is on 64-bit slot and is capable of 64-bit
transaction. Otherwise, the RTL8169 is on 32-bit slot.
IDSEL I 191
Initialization Device Select: This pin allows the RTL8169 to identify
when configuration read/write transactions are intended for it.
INTAB O/D 174
Interrupt A: Used to request an interrupt. It is asserted low when an
interrupt condition occurs, as defined by the Interrupt Status, Interrupt
Mask.
IRDYB S/T/S 204 Initiator Ready: This indicates the initiating agent’s ability to complete
the current data phase of the transaction.
As a bus master, this signal will be asserted low when the RTL8169 is
ready to complete the current data phase transaction. This signal is used
in conjunction with the TRDYB signal. Data transaction takes place at
the rising edge of CLK when both IRDYB and TRDYB are asserted
low. As a target, this signal indicates that the master has put data on the
bus.
TRDYB S/T/S 205 Target Ready: This indicates the target agent’s ability to complete the
current phase of the transaction.
As a bus master, this signal indicates that the target is ready for the data
during write operations and with the data during read operations. As a
target, this signal will be asserted low when the (slave) device is ready
to complete the current data phase transaction. This signal is used in
conjunction with the IRDYB signal. Data transaction takes place at the
rising edge of CLK when both IRDYB and TRDYB are asserted low.
PAR T/S 5
Parity: This signal indicates even parity across AD31-0 and C/BE3-0
including the PAR pin. PAR is stable and valid one clock after each
address phase. For data phase, PAR is stable and valid one clock after
either IRDYB is asserted on a write transaction or TRDYB is asserted
on a read transaction. Once PAR is valid, it remains valid until one clock
after the completion of the current data phase. As a bus master, PAR is
asserted during address and write data phases. As a target, PAR is
asserted during read data phases.
PAR64 T/S 39
Parity Upper Double Word: This signal indicates even parity across
AD63-32 and C/BE7-4 including the PAR64 pin. PAR64 is valid one
clock after each address phase on any transaction in which REQ64B is
asserted. PAR64 is stable and valid for 64-bit data phase one clock after
either IRDYB is asserted on a write transaction or TRDYB is asserted
on a read transaction. As a bus master, PAR64 is asserted during address
and write data phases. As a target, the RTL8169 only supports 32-bit
transfers, so it will not assert PAR64.
cont...

RTL8169
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M66EN I 173
66MHZ_ENABLE: This pin indicates to the RTL8169 whether the bus
segment is operating at 66 or 33MHz. When this pin (active high) is
asserted, the current PCI bus segment that the RTL8169 resides on
operates in 66-MHz mode. If this pin is deasserted, the current PCI bus
segment operates in 33-MHz mode.
PERRB S/T/S 1 Parity Error: This pin is used to report data parity errors during all PCI
transactions except a Special Cycle. PERRB Is driven active (low) two
clocks after a data parity error is detected by the device receiving data,
and the minimum duration of PERRB is one clock for each data phase
with parity error detected.
SERRB O/D 3 System Error: If an address parity error is detected and Configuration
Space Status register bit 15 (detected parity error) is enabled, the
RTL8169 asserts the SERRB pin low and bit 14 of Status register in
Configuration Space.
STOPB S/T/S 208 Stop: Indicates that the current target is requesting the master to stop the
current transaction.
RSTB I 175
Reset: When RSTB is asserted low, the RTL8169 performs an internal
system hardware reset. RSTB must be held for a minimum of 120 ns
periods.
5.3 FLASH/BootPROM/EEPROM/MII Interface
Symbol Type Pin No Description
MA[16:9], MA7,
MA[5:3]
MA8
MA6
O
O, I
O, I
112-109, 107,
105-104, 102, 100,
97-95
101
99
Boot PROM Address Bus: These pins are used to access up to a
128k-byte flash memory or EPROM.
MA16-3: Output pins to the Boot PROM address bus.
MA8: Input pin as Aux. Power detect pin to detect if Aux. Power exists
or not, when initial power-on. Besides connecting this pin to Boot
PROM, it should be pulled high to the Aux. Power via a resistor to
detect Aux. power. If this pin is not pulled high to Aux. Power, the
RTL8169 assumes that no Aux. power exists. To support wakeup from
ACPI D3cold or APM power-down, this pin must be pulled high to aux.
power via a resistor.
MA6/9356SEL: Input pin as 9356 select pin at initial power-up. When
this pin is pulled high with a 10KΩresistor, the 93C56 EEPROM is
used to store the resource data and CIS for the RTL8169. The RTL8169
latches the status of this pin at power-up to determine what EEPROM
(93C46 or 93C56) is used, afterwards, this pin is used as MA6
MA2/EESK O 92
MA1/EEDI O 91
MA0/EEDO O, I 90
MA2-0: The MA2-0 pins are switched to EESK, EEDI, EEDO in
93C46 (93C56) programming or auto-load mode.
EECS O 93
EEPROM Chip Select: 93C46 (93C56) chip select
MD7-0 I/O 119, 121-127 Boot PROM data bus during Boot PROM mode.
ROMCSB O 128
ROM Chip Select: This is the chip select signal of the Boot PROM.
OEB O 130
Output Enable: This enables the output buffer of the Boot PROM or
Flash memory during a read operation.
WEB O 129
Write Enable: This signal strobes data into the Flash memory during a
write cycle.

RTL8169
2002/03/27 Rev.1.21
10
5.4 LED Interface
Symbol Type Pin No Description
LED3-0 O 114-116, 118
LED pins (Active low)
1000BaseT mode:
LEDS1-
0
00 01 10 11
LED0 Tx/Rx ACT(Tx/Rx) Tx LINK10/ACT
LED1 LINK100 LINK10/100/
1000
LINK10/100/
1000
LINK100/ACT
LED2 LINK10 FULL Rx FULL
LED3 LINK1000 - FULL LINK1000/ACT
TBI mode:
LEDS1-
0
00 01 10 11
LED0 ACT ACT Tx -
LED1 - LINK LINK -
LED2 - FULL Rx FULL
LED3 LINK - FULL LINK
During power down mode, the LED signals are logic high.
5.5 GMII, TBI, PHY CP
Gigabit Media Independent Interface, Ten Bit Interface, PHY Control Pin
Symbol Type Pin No Description
GTxCLK O 145
Gigabit Tx clock: In GMII mode (1000Mbps Tx clock), GTxCLK is a
continuous clock used for operation at 1000Mbps. GTxCLK provides
the timing reference for the transfer of the TxEN, TxER, and TxD
signals. The values of TxEN, TxER, and TxDs are sampled by the PHY
on the rising edge of GTxCLK.
In GMII mode or TBI mode, the GTxCLK can be used as a 125MHz
reference clock, and it used as the 125MHz transmit clock to an external
PMD and is the reference for transmit TBI signaling.
TxCLK I 147
Transmit Clock (MII mode only): TxCLK is a continuous clock that
provides a timing reference for the transfer of TxD[3:0], TxEN. In MII
mode, it uses the 25MHz or 2.5MHz supplied by the external PMD
device.
TxEN/
Tx[9]
O 143
Transmit Enable: In GMII mode (or MII mode), the assertion of TxEN
indicates that the RTL8169 is presenting data on the GMII (or MII) for
transmission. TxEn is asserted synchronously with the first octet (or
nibble) of the preamble and remains asserted while all octets (or
nibbles) to be transmitted are presented to the GMII (or MII).
This signal is synchronous to TxCLK and provides precise framing for
data carried on TXD3-0/TXD7-0 for the external PMD. It is asserted
when TXD3-0/TXD7-0 contains valid data to be transmitted.
Tx[9]: In TBI mode, Tx[9] is the MSB of the 10-bit vector representing
one transmission code-group. Tx[0] is the first bit to be transmitted, and
Tx[9] is the last bit to be transmitted.
Tx[8] O 146
Tx[8] (TBI mode only): In TBI mode, Tx[8] is one of the 10-bit vector
representing one transmission code-group.
cont...

RTL8169
2002/03/27 Rev.1.21
11
TxD[7:0]/
Tx[7:0]
O 135-142
Transmit Data: In GMII mode, TxD[7:0] is a bundle of eight data
signals, representing a data byte on GMII for PHY to transmit. In MII
mode, only TxD[3:0] represent a data nibble on MII for PHY to
transmit. TxD[7:0] or TxD[3:0] transition synchronously with respect
to GTxCLK or TxCLK.
Tx[7:0]: In TBI mode, TxD[7:0] is part of the 10-bit vector (TxD[9:0])
representing one transmission code-group.
RxCLK/
RxCLK0
I 156
Receive Clock(0): RxCLK: In GMII mode or MII mode, the receive
clock is a continuous clock that provides the timing reference for the
transfer of the RxDV, RxER, and RxD from PHY device. RxDV, RxER,
and RxD are sampled on the rising edge of RxCLK.
RxCLK0: In TBI mode, the 62.5MHz receive clock is a continuous
clock and provides timing reference for the RTL8169 to latch
odd-numbered receive code-groups from PHY device.
RxCLK1 I 154
Receive Clock1: RxCLK1: In TBI mode, the 62.5MHz receive clock is
a continuous clock and provides timing reference for the RTL8169 to
latch even-numbered receive code-groups from PHY device.
RxER/
Rx[9]
I 152
Receive Coding Error: In GMII or MII mode, this pin is asserted
synchronously with respect to RxCLK, to indicate that the PHY device
detected a symbol that is not part of the valid data or delimiter set
somewhere in the frame being received. The RxER may be asserted for
one or more clock cycles.
Rx[9]: In TBI mode, Rx[9] is the MSB of the 10-bit vector representing
one receive code-group. Rx[0] is the first bit received, and Rx[9] is the
last bit received.
RxDV/
Rx[8]
I 157
Receive Data Valid: In GMII or MII mode, this input pin is asserted
synchronously with respect to RxCLK, to indicate that the PHY is
presenting recovered, decoded, and valid data to the RTL8169. RxDV
remains asserted while valid data is being presented by the PHY.
Rx[8]: In TBI mode, Rx[8] is a bit of the 10-bit vector representing one
receive code-group. Rx[0] is the first bit received, and Rx[9] is the last
bit received.
RxD[7:0]/
Rx[7:0]
I 165-158
Receive Data: In GMII mode, RxD[7:0] is a bundle of eight data
signals, representing a data byte transmitted from PHY to the RTL8169
on GMII. In MII mode, only RxD[3:0] represent a data nibble
transmitted from PHY to the RTL8169 on MII. RxD[7:0] or RxD[3:0]
transition synchronously with respect to RxCLK.
Rx[7:0]: In TBI mode, RxD[7:0] is part of the 10-bit vector (RxD[9:0])
representing one receive code-group.
COL I 151
Collision Detected: In GMII or MII mode, this input pin is asserted
high by PHY to indicate the detection of a collision on the twisted pair
medium, and remains asserted while the collision condition persists. In
full duplex mode, this pin’s status is ignored by the RTL8169. The COL
transitions asynchronously with respect to RxCLK, GTxCLK, or
TxCLK.
In TBI mode, this pin’s status is ignored by the RTL8169.
cont...

RTL8169
2002/03/27 Rev.1.21
12
CRS I 148
Carrier Sense: In GMII or MII mode, this pin is asserted high by the
GMII/MII PHY device whenever the transmit or receive medium is not
idle, and is deasserted when both transmit and receive media are idle.
The CRS remains asserted throughout the duration of a collision
condition. The CRS transitions asynchronously with respect to RxCLK,
GTxCLK, or TxCLK.
In TBI mode, this pin’s status is ignored by the RTL8169.
MDC O 169
Management Data Clock: In GMII or MII mode, it is a synchronous
clock to the MDIO management data input/output serial interface (about
3.125MHz) which may be asynchronous to transmit and receive clocks.
In TBI mode, this pin is a reserved pin.
MDIO I/O 170
Management Data Input/Output: Bi-directional signal used to
transfer or receive control and status information from the PHY device.
MDIO is driven and sampled synchronously with respect to MDC.
In TBI mode, this pin is a reserved pin.
TBILBK O 133
TBI LoopBack: The RTL8169 asserts this pin high when the TBI is in
loopback mode.
RSTPHYB O 132 PHY Reset pin: An active low signal used by the RTL8169 to force
hardware reset to external PHYceiver at initial power-on.
5.6 Clock and NC Pins
Symbol Type Pin No Description
Clock125 I 168
125MHz clock input: The 125MHz reference clock for the RTL8169
comes from either external PHYceiver or 125MHz OSC.
NC - 2, 4, 6, 45, 47, 49, 51,
103, 106, 108, 153,
155,
Reserved
5.7 Power Pins
Symbol Type Pin No Description
VDD33 P 8, 18, 30, 41, 55, 65,
77, 89, 113, 131, 144,
167, 179, 189, 200
+3.3V
VDD18 P 27, 120, 68, 166 +1.8V
GND P 13, 23, 36, 48, 60, 71,
82, 98, 117, 134, 150,
171, 184, 195, 206, 33,
94, 72, 149
Ground

RTL8169
2002/03/27 Rev.1.21
13
6. Register Descriptions
The RTL8169 provides the following set of operational registers mapped into PCI memory space or I/O space.
Offset R/W Tag Description
0000h R/W IDR0 ID Register 0: The ID registers 0-5 are only permitted to write by
4-byte access. Read access can be byte, word, or double word access.
The initial value is autoloaded from EEPROM EthernetID field.
0001h R/W IDR1 ID Register 1
0002h R/W IDR2 ID Register 2
0003h R/W IDR3 ID Register 3
0004h R/W IDR4
ID Register 4
0005h R/W IDR5 ID Register 5
0006h-0007h - - Reserved
0008h R/W MAR0
Multicast Register 0: The MAR registers 0-7 are only permitted to
write by 4-bye access. Read access can be byte, word, or double word
access. Driver is responsible for initializing these registers.
0009h R/W MAR1
Multicast Register 1
000Ah R/W MAR2
Multicast Register 2
000Bh R/W MAR3
Multicast Register 3
000Ch R/W MAR4
Multicast Register 4
000Dh R/W MAR5
Multicast Register 5
000Eh R/W MAR6
Multicast Register 6
000Fh R/W MAR7
Multicast Register 7
0010h-0017h R/W DTCCR Dump Tally Counter Command Register (64-byte alignment)
0018h-001Fh - - Reserved
0020h-0027h R/W TNPDS Transmit Normal Priority Descriptors: Start address (64-bit).
(256-byte alignment)
0028h-002Fh R/W THPDS Transmit High Priority Descriptors: Start address (64-bit).
(256-byte alignment)
0030h-0033h R/W FLASH Flash memory read/write register
0034h-0035h R ERBCR Early Receive (Rx) Byte Count Register
0036h R ERSR
Early Rx Status Register
0037h R/W CR Command Register
0038h W TPPoll
Transmit Priority Polling register
0039h-003Bh - - Reserved
003Ch-003Dh R/W IMR Interrupt Mask Register
003Eh-003Fh R/W ISR Interrupt Status Register
0040h-0043h R/W TCR Transmit (Tx) Configuration Register
0044h-0047h R/W RCR Receive (Rx) Configuration Register
0048h-004Bh R/W TCTR Timer CounT Register: This register contains a 32-bit
general-purpose timer. Writing any value to this 32-bit register will
reset the original timer and begin the count from zero.
004Ch-004Fh R/W MPC Missed Packet Counter: This 24-bit counter indicates the number of
packets discarded due to Rx FIFO overflow. After a s/w reset, MPC is
cleared. Only the lower 3 bytes are valid.
When any value is written to MPC, it will be reset.
0050h R/W 9346CR
93C46 (93C56) Command Register
0051h R/W CONFIG0
Configuration Register 0
0052h R/W CONFIG1
Configuration Register 1
0053h R/W CONFIG2
Configuration Register 2
0054h R/W CONFIG3
Configuration Register 3
cont...

RTL8169
2002/03/27 Rev.1.21
14
0055h R/W CONFIG4
Configuration Register 4
0056h R/W CONFIG5
Configuration Register 5
0057h - - Reserved
0058h-005Bh R /W TimerInt Timer Interrupt Register: Once having written a nonzero value to
this register, the Timeout bit of ISR register will be set whenever the
TCTR reaches to this value. The Timeout bit will never be set as long
as TimerInt register is zero.
005Ch-005Dh R/W MULINT Multiple Interrupt Select
005Eh-005Fh - - Reserved
0060h-0063h R/W PHYAR PHY Access Register
0064h-0067h R/W TBICSR0 TBI Control and Status Register
0068h-0069h R/W TBI_ANAR
TBI Auto-Negotiation Advertisement Register
006Ah-006Bh R TBI_LPAR
TBI Auto-Negotiation Link Partner Ability Register
006Ch R PHYStatus PHY(GMII, MII, or TBI) Status Register
006Dh-0081h - - Reserved
0082-0083h - - Reserved
0084h–008Bh R/W Wakeup0 Power Management wakeup frame0 (64bit)
008Ch–0093h R/W Wakeup1 Power Management wakeup frame1 (64bit)
0094h–009Bh R/W Wakeup2LD Power Management wakeup frame2 (128bit), low D-Word
009Ch–00A3h R/W Wakeup2HD Power Management wakeup frame2, high D-Word
00A4h–00ABh R/W Wakeup3LD Power Management wakeup frame3 (128bit), low D-Word
00ACh–00B3h R/W Wakeup3HD Power Management wakeup frame3, high D-Word
00B4h–00BBh R/W Wakeup4LD Power Management wakeup frame4 (128bit), low D-Word
00BCh–00C3h R/W Wakeup4HD Power Management wakeup frame4, high D-Word
00C4h-00C5h R/W CRC0 16-bit CRC of wakeup frame 0
00C6h-00C7h R/W CRC1 16-bit CRC of wakeup frame 1
00C8h-00C9h R/W CRC2 16-bit CRC of wakeup frame 2
00CAh-00CBh R/W CRC3 16-bit CRC of wakeup frame 3
00CCh-00CDh R/W CRC4 16-bit CRC of wakeup frame 4
00CEh-00D9h - - Reserved
00DAh-00DBh R/W RMS Rx packet Maximum Size
00DCh-00DFh - - Reserved
00E0h-00E1h R/W C+CR C+ Command Register
00E2h-00E3h - - Reserved
00E4h-00EBh R/W RDSAR Receive Descriptor Start Address Register (256-byte alignment)
00ECh R/W ETThR
Early Transmit Threshold Register
00EDh-00EFh - - Reserved
00F0h-00F3h R/W FER Function Event Register (Cardbus only)
00F4h-00F7h R/W FEMR Function Event Mask Register (CardBus only)
00F8h-00FBh R FPSR Function Present State Register (CardBus only)
00FCh-00FFh W FFER Function Force Event Register (CardBus only)

RTL8169
2002/03/27 Rev.1.21
15
6.1 DTCCR: Dump Tally Counter Command
(Offset 0010h-0017h, R/W)
Bit R/W Symbol Description
Starting address of the 12 Tally Counters being dumped to. (64-byte alignment
address, 64 bytes long)
Offset of
starting
address
Counter Description
0 TxOk 64-bit counter of Tx Ok packets.
8 RxOk 64-bit counter of Rx Ok packets.
16 TxER 64-bit packet counter of Tx errors including Tx
abort, carrier lost, Tx underrun, and out of window
collision.
24 RxEr 32-bit packet counter of Rx errors including CRC
error packets (should be larger than 8 bytes) and
missed packets.
28 MissPkt 16-bit counter of missed packets (CRC Ok)
resulted from Rx FIFO full.
30 FAE 16-bit counter of Frame Alignment Error packets
(MII mode only)
32 Tx1Col 32-bit counter of those Tx Ok packets with only 1
collision happened before Tx Ok.
36 TxMCol 32-bit counter of those Tx Ok packets with more
than 1, and less than 16 collisions happened before
Tx Ok.
40 RxOkPh
y
64-bit counter of all Rx Ok packets with physical
address matched destination ID.
48 RxOkBrd 64-bit counter of all Rx Ok packets with broadcast
destination ID.
56 RxOkMu
l
32-bit counter of all Rx Ok packets with multicast
destination ID.
60 TxAbt 16-bit counter of Tx abort packets.
63:6 R/W CntrAddr
62 TxUndrn 16-bit counter of Tx underrun and discard packets
(only possible on jumbo frames).
5:4 - - Reserved
3 R/W Cmd
Command: When set, the RTL8169 begins dumping 13 Tally counters to the address
specified above.
When this bit is reset by the RTL8169, the dumping has been completed.
2:0 - -
Reserved

RTL8169
2002/03/27 Rev.1.21
16
6.2 FLASH: Flash Memory Read/Write
(Offset 0030h-0033h, R)
Bit R/W Symbol Description
31:24 R/W MD7-MD0 Flash Memory Data Bus: These bits set and reflect the state of the
MD7 - MD0 pins during the write and read process respectively.
23:21 - - Reserved
20 W ROMCSB Chip Select: This bit sets the state of the ROMCSB pin.
19 W OEB Output Enable: This bit sets the state of the OEB pin.
18 W WEB Write Enable: This bit sets the state of the WEB pin.
17 W SWRWEn Enable software access to flash memory:
1: Enable read/write access to flash memory via software and
disable the EEPROM access during flash memory access via
software.
0: Disable read/write access to flash memory via software.
16:0 W MA16-MA0 Flash Memory Address Bus: These bits set the state of the MA16-0
pins.
6.3 ERSR: Early Rx Status
(Offset 0036h, R)
Bit R/W Symbol Description
7:4 - -
Reserved
3 R ERGood
Early Rx Good packet: This bit is set whenever a packet is completely
received and the packet is good. Writing a ‘1’ will clear this bit.
2 R ERBad
Early Rx Bad packet: This bit is set whenever a packet is completely
received and the packet is bad. Writing a ‘1’ will clear this bit.
1 R EROVW
Early Rx OverWrite: This bit is set when the RTL8169's local address
pointer is equal to CAPR. In the early mode, this is different from buffer
overflow. It happens when the RTL8169 detects an Rx error and wants
to fill another packet data from the beginning address of that error
packet. Writing a ‘1’ will clear this bit.
0 R EROK
Early Rx OK: The power-on value is 0. It is set when the Rx byte count
of the arriving packet exceeds the Rx threshold. After the whole packet
is received, the RTL8169 will set ROK or RER in ISR and clear this bit
simultaneously. Setting this bit will invoke a ROK interrupt.

RTL8169
2002/03/27 Rev.1.21
17
6.4 Command
(Offset 0037h, R/W)
Bit R/W Symbol Description
7:5 - -
Reserved
4 R/W RST
Reset: Setting this bit to 1 forces the RTL8169 into a software reset
state which disables the transmitter and receiver, reinitializes the FIFOs,
and resets the system buffer pointer to the initial value (the start address
of each descriptor group set in TNPDS, THPDS and RDSAR registers).
The values of IDR0-5, MAR0-7 and PCI configuration space will have
no changes. This bit is 1 during the reset operation, and is cleared to 0
by the RTL8169 when the reset operation is complete.
3 R/W RE
Receiver Enable
2 R/W TE
Transmit Enable
1:0 - -
Reserved
6.5 TPPoll: Transmit Priority Polling
(Offset 0038h, R/W)
Bit R/W Symbol Description
7 W HPQ High Priority Queue polling: Writing a ‘1’ to this bit will notify the
RTL8169 that there is a high priority packet(s) waiting to be
transmitted. The RTL8169 will clear this bit automatically after all
high priority packets have been transmitted.
Writing a ‘0’ to this bit has no effect.
6 W NPQ Normal Priority Queue polling: Writing a ‘1’ to this bit will notify
the RTL8169 that there is a normal priority packet(s) waiting to be
transmitted. The RTL8169 will clear this bit automatically after all
normal priority packets have been transmitted.
Writing a ‘0’ to this bit has no effect.
5:1 - - Reserved
0 W FSWInt Forced Software Interrupt: Writing a ‘1’ to this bit will trigger an
interrupt, and the SWInt bit (bit8, ISR, offset3Eh-3Fh) will set.
The RTL8169 will clear this bit automatically after the SWInt bit (bit8,
ISR) is cleared.
Writing a ‘0’ to this bit has no effect.

RTL8169
2002/03/27 Rev.1.21
18
6.6 Interrupt Mask
(Offset 003Ch-003Dh, R/W)
Bit R/W Symbol Description
15 R/W SERR
System Error Interrupt:
1: Enable; 0: Disable.
14 R/W TimeOut
Time Out Interrupt:
1: Enable; 0: Disable.
13:10 - -
Reserved
9 - -
Reserved
8 R/W SWInt
Software Interrupt:
1: Enable; 0: Disable.
7 R/W TDU
Tx Descriptor Unavailable Interrupt:
1: Enable; 0: Disable.
6 R/W FOVW
Rx FIFO Overflow Interrupt:
1: Enable; 0: Disable.
5 R/W PUN/LinkChg
Packet Underrun/Link Change Interrupt:
1: Enable; 0: Disable.
4 R/W RDU
Rx Buffer Overflow/Rx Descriptor Unavailable Interrupt:
1: Enable; 0: Disable.
3 R/W TER
Tx Error Interrupt:
1: Enable; 0: Disable.
2 R/W TOK
Tx Ok:
Transmit (Tx) OK: Indicates that a packet transmission is completed
successfully.
1: Enable; 0: Disable.
1 R/W RER
Rx Error Interrupt:
1: Enable; 0: Disable.
0 R/W ROK
Rx OK Interrupt:
1: Enable; 0: Disable.

RTL8169
2002/03/27 Rev.1.21
19
6.7 Interrupt Status
(Offset 003Eh-003Fh, R/W)
Bit R/W Symbol Description
15 R/W SERR
System Error: This bit is set to 1 when the RTL8169 signals a system
error on the PCI bus.
14 R/W TimeOut
Time Out: This bit is set to 1 when the TCTR register reaches the value
of the TimerInt register.
13:10 - -
Reserved
9 - - Reserved
8 R/W SWInt
Software Interrupt: This bit is set to 1 whenever a ‘1’ is written by
software to FSWInt (bit0, offset D9h, TPPoll register).
7 R/W TDU
Tx Descriptor Unavailable: When set, this bit indicates that the Tx
descriptor is unavailable.
6 R/W FOVW
Rx FIFO Overflow: This bit set to 1 is caused by RDU, poor PCI
performance, or overloaded PCI traffic.
5 R/W PUN/LinkChg
Packet Underrun/Link Change: This bit is set to 1 when CAPR is
written but the Rx buffer is empty, or when link status is changed.
4 R/W RDU
Rx Descriptor Unavailable: When set to 1, this bit indicates that the
Rx descriptor is unavailable.
The MPC (Missed Packet Counter, offset 4Ch-4Fh) indicates the
number of packets discarded after Rx FIFO overflowed.
3 R/W TER
Transmit (Tx) Error: This bit set to 1 indicates that a packet
transmission was aborted, due to excessive collisions, according to the
TXRR's setting in the TCR register.
2 R/W TOK
Transmit (Tx) OK: When set to 1, this bit indicates that a packet
transmission has been completed successfully.
1 R/W RER
Receive (Rx) Error: When set to 1, this bit indicates that a packet has
either a CRC error or a frame alignment error (FAE). A Rx error packet
of CRC error is determined according to the setting of RER8, AER, AR
bits in RCR register (offset 44h-47h).
0 R/W ROK
Receive (Rx) OK: In normal mode, this bit set to 1 indicates the
successful completion of a packet reception. In early mode, this bit set
to 1 indicates that the Rx byte count of the arriving packet exceeds the
early Rx threshold.
 Writing 1 to any bit in the ISR will reset that bit.

RTL8169
2002/03/27 Rev.1.21
20
6.8 Transmit Configuration
(Offset 0040h-0043h, R/W)
Bit R/W Symbol Description
31 - -
Reserved
Hardware Version ID0:
Bit30 Bit29 Bit28 Bit27 Bit26 Bit23
RTL8139 1 1 0 0 0 0
RTL8139A 1 1 1 0 0 0
RTL8139A-G 1 1 1 0 0 1
RTL8139B 1 1 1 1 0 0
RTL8130 1 1 1 1 1 0
RTL8139C 1 1 1 0 1 0
RTL8139C+ 1 1 1 0 1 1
RTL8100 1 1 1 1 0 1
RTL8169 0 0 0 0 0 0
Reserved All other combination
30:26 R HWVERID0
InterFrameGap Time: This field allows adjustment of the interframe
gap time to be longer than the standards of 9.6 µs for 10Mbps, 960 ns
for 100Mbps, and 96 ns for 1000Mbps. The time can be programmed
from 9.6 µs to 14.4 µs (10Mbps), 960ns to 1440ns (100Mbps), and 96ns
to 144ns (1000Mbps).
The setting of the inter frame gap is:
IFG[2:0] IFG@1000MHz
(ns)
IFG@100MHz
(ns)
IFG@10MHz
(µs)
0 1 1 96 960 9.6
1 0 1 96 + 8 960 + 8 * 10 9.6 + 8 * 0.1
1 1 1 96 + 16 960 + 16 * 10 9.6 + 16 * 0.1
0 0 1 96 + 24 960 + 24 * 10 9.6 + 24 * 0.1
0 1 0 96 + 48 960 + 48 * 10 9.6 + 48 * 0.1
25:24 R/W IFG1, 0
-Other values are reserved.
23 R HWVERID1
Hardware Version ID1: Please see HWVERID0.
22:20 -
Reserved
19 R/W IFG2
InterFrameGap2
18:17 R/W LBK1, LBK0
Loopback test: There will be no packets on the (G)MII or TBI interface
in Digital loopback mode, provided the external phyceiver is also set in
loopback mode. The digital loopback function is independent of the
current link status.
For analog loopback tests, software must force the external phyceiver
into loopback mode while the RTL8169 operates normally.
00 : Normal operation
01 : Digital loopback mode
10 : Reserved
11 : Reserved
16 R/W CRC
Append CRC: Setting this bit to 1 means that there is no CRC
appended at the end of a packet. Setting to 0 means that there is a CRC
appended at the end of a packet.
15:11 - -
Reserved
cont...